arch/arm/cpu/armv7/am33xx/ddr.c

   1 /*
   2  * DDR Configuration for AM33xx devices.
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/io.h>
  21 #include <asm/emif.h>
  22
  23 /**
  24  * Base address for EMIF instances
  25  */
  26 static struct emif_reg_struct *emif_reg = (void *)EMIF4_0_CFG_BASE;
  27
  28 /**
  29  * Base address for DDR instance
  30  */
  31 static struct ddr_regs *ddr_reg[2] = {
  32                                 (struct ddr_regs *)DDR_PHY_BASE_ADDR,
  33                                 (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
  34
  35 /**
  36  * Base address for ddr io control instances
  37  */
  38 static struct ddr_cmdtctrl *ioctrl_reg = {
  39                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  40
  41 /**
  42  * Configure SDRAM
  43  */
  44 void config_sdram(const struct emif_regs *regs)
  45 {
  46         writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
  47         writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
  48         if (regs->zq_config) {
  49                 writel(regs->zq_config, &emif_reg->emif_zq_config);
  50                 writel(regs->sdram_config, &cstat->emif_sdram_config);
  51         }
  52         writel(regs->sdram_config, &emif_reg->emif_sdram_config);
  53 }
  54
  55 /**
  56  * Set SDRAM timings
  57  */
  58 void set_sdram_timings(const struct emif_regs *regs)
  59 {
  60         writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
  61         writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
  62         writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
  63         writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
  64         writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
  65         writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
  66 }
  67
  68 /**
  69  * Configure DDR PHY
  70  */
  71 void config_ddr_phy(const struct emif_regs *regs)
  72 {
  73         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
  74         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
  75 }
  76
  77 /**
  78  * Configure DDR CMD control registers
  79  */
  80 void config_cmd_ctrl(const struct cmd_control *cmd)
  81 {
  82         writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
  83         writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
  84         writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
  85
  86         writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
  87         writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
  88         writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
  89
  90         writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
  91         writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
  92         writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
  93 }
  94
  95 /**
  96  * Configure DDR DATA registers
  97  */
  98 void config_ddr_data(int macrono, const struct ddr_data *data)
  99 {
 100         writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
 101         writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
 102         writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
 103         writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
 104         writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
 105         writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
 106         writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
 107         writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 108 }
 109
 110 void config_io_ctrl(unsigned long val)
 111 {
 112         writel(val, &ioctrl_reg->cm0ioctl);
 113         writel(val, &ioctrl_reg->cm1ioctl);
 114         writel(val, &ioctrl_reg->cm2ioctl);
 115         writel(val, &ioctrl_reg->dt0ioctl);
 116         writel(val, &ioctrl_reg->dt1ioctl);
 117 }