arch/arm/cpu/armv7/am33xx/ddr.c

   1 /*
   2  * DDR Configuration for AM33xx devices.
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated -
   5 http://www.ti.com/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/io.h>
  22 #include <asm/emif.h>
  23
  24 /**
  25  * Base address for EMIF instances
  26  */
  27 static struct emif_reg_struct *emif_reg[2] = {
  28                                 (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  29                                 (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
  30
  31 /**
  32  * Base addresses for DDR PHY cmd/data regs
  33  */
  34 static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  35                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  36                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
  37
  38 static struct ddr_data_regs *ddr_data_reg[2] = {
  39                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  40                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
  41
  42 /**
  43  * Base address for ddr io control instances
  44  */
  45 static struct ddr_cmdtctrl *ioctrl_reg = {
  46                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  47
  48 /**
  49  * Configure SDRAM
  50  */
  51 void config_sdram(const struct emif_regs *regs, int nr)
  52 {
  53         if (regs->zq_config) {
  54                 /*
  55                  * A value of 0x2800 for the REF CTRL will give us
  56                  * about 570us for a delay, which will be long enough
  57                  * to configure things.
  58                  */
  59                 writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
  60                 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  61                 writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
  62                 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  63                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  64                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  65         }
  66         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  67         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
  68         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  69 }
  70
  71 /**
  72  * Set SDRAM timings
  73  */
  74 void set_sdram_timings(const struct emif_regs *regs, int nr)
  75 {
  76         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
  77         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
  78         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
  79         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
  80         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
  81         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
  82 }
  83
  84 /**
  85  * Configure DDR PHY
  86  */
  87 void config_ddr_phy(const struct emif_regs *regs, int nr)
  88 {
  89         writel(regs->emif_ddr_phy_ctlr_1,
  90                 &emif_reg[nr]->emif_ddr_phy_ctrl_1);
  91         writel(regs->emif_ddr_phy_ctlr_1,
  92                 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
  93 }
  94
  95 /**
  96  * Configure DDR CMD control registers
  97  */
  98 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
  99 {
 100         writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
 101         writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
 102         writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 103
 104         writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
 105         writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
 106         writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 107
 108         writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
 109         writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
 110         writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 111 }
 112
 113 /**
 114  * Configure DDR DATA registers
 115  */
 116 void config_ddr_data(const struct ddr_data *data, int nr)
 117 {
 118         int i;
 119
 120         for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 121                 writel(data->datardsratio0,
 122                         &(ddr_data_reg[nr]+i)->dt0rdsratio0);
 123                 writel(data->datawdsratio0,
 124                         &(ddr_data_reg[nr]+i)->dt0wdsratio0);
 125                 writel(data->datawiratio0,
 126                         &(ddr_data_reg[nr]+i)->dt0wiratio0);
 127                 writel(data->datagiratio0,
 128                         &(ddr_data_reg[nr]+i)->dt0giratio0);
 129                 writel(data->datafwsratio0,
 130                         &(ddr_data_reg[nr]+i)->dt0fwsratio0);
 131                 writel(data->datawrsratio0,
 132                         &(ddr_data_reg[nr]+i)->dt0wrsratio0);
 133                 writel(data->datauserank0delay,
 134                         &(ddr_data_reg[nr]+i)->dt0rdelays0);
 135                 writel(data->datadldiff0,
 136                         &(ddr_data_reg[nr]+i)->dt0dldiff0);
 137         }
 138 }
 139
 140 void config_io_ctrl(unsigned long val)
 141 {
 142         writel(val, &ioctrl_reg->cm0ioctl);
 143         writel(val, &ioctrl_reg->cm1ioctl);
 144         writel(val, &ioctrl_reg->cm2ioctl);
 145         writel(val, &ioctrl_reg->dt0ioctl);
 146         writel(val, &ioctrl_reg->dt1ioctl);
 147 }