arch/arm/cpu/armv7/am33xx/ddr.c

   1 /*
   2  * DDR Configuration for AM33xx devices.
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/cpu.h>
  10 #include <asm/arch/ddr_defs.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/io.h>
  13 #include <asm/emif.h>
  14
  15 /**
  16  * Base address for EMIF instances
  17  */
  18 static struct emif_reg_struct *emif_reg[2] = {
  19                                 (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  20                                 (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
  21
  22 /**
  23  * Base addresses for DDR PHY cmd/data regs
  24  */
  25 static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  26                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  27                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
  28
  29 static struct ddr_data_regs *ddr_data_reg[2] = {
  30                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  31                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
  32
  33 /**
  34  * Base address for ddr io control instances
  35  */
  36 static struct ddr_cmdtctrl *ioctrl_reg = {
  37                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  38
  39 static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
  40 {
  41         u32 mr;
  42
  43         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  44         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  45
  46         mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
  47         debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
  48         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  49             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  50             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  51                 return mr & 0xff;
  52         else
  53                 return mr;
  54 }
  55
  56 static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
  57 {
  58         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  59         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  60         writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
  61 }
  62
  63 static void configure_mr(int nr, u32 cs)
  64 {
  65         u32 mr_addr;
  66
  67         while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  68                 ;
  69         set_mr(nr, cs, LPDDR2_MR10, 0x56);
  70
  71         set_mr(nr, cs, LPDDR2_MR1, 0x43);
  72         set_mr(nr, cs, LPDDR2_MR2, 0x2);
  73
  74         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  75         set_mr(nr, cs, mr_addr, 0x2);
  76 }
  77
  78 /*
  79  * Configure EMIF4D5 registers and MR registers For details about these magic
  80  * values please see the EMIF registers section of the TRM.
  81  */
  82 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  83 {
  84         writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  85         writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  86         writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  87
  88         writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
  89         writel(regs->emif_rd_wr_lvl_rmp_win,
  90                &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
  91         writel(regs->emif_rd_wr_lvl_rmp_ctl,
  92                &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  93         writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
  94         writel(regs->emif_rd_wr_exec_thresh,
  95                &emif_reg[nr]->emif_rd_wr_exec_thresh);
  96
  97         /*
  98          * for most SOCs these registers won't need to be changed so only
  99          * write to these registers if someone explicitly has set the
 100          * register's value.
 101          */
 102         if(regs->emif_cos_config) {
 103                 writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
 104                 writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
 105                 writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
 106                 writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
 107         }
 108
 109         /*
 110          * Sequence to ensure that the PHY is in a known state prior to
 111          * startting hardware leveling.  Also acts as to latch some state from
 112          * the EMIF into the PHY.
 113          */
 114         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 115         writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 116         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 117
 118         clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 119                         EMIF_REG_INITREF_DIS_MASK);
 120
 121         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 122         writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 123         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 124         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 125
 126         /* Perform hardware leveling. */
 127         udelay(1000);
 128         writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
 129                0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 130         writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
 131                0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 132
 133         writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
 134
 135         /* Enable read leveling */
 136         writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 137
 138         /*
 139          * Enable full read and write leveling.  Wait for read and write
 140          * leveling bit to clear RDWRLVLFULL_START bit 31
 141          */
 142         while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
 143                 ;
 144
 145         /* Check the timeout register to see if leveling is complete */
 146         if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
 147                 puts("DDR3 H/W leveling incomplete with errors\n");
 148
 149         if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
 150                 configure_mr(nr, 0);
 151                 configure_mr(nr, 1);
 152         }
 153 }
 154
 155 /**
 156  * Configure SDRAM
 157  */
 158 void config_sdram(const struct emif_regs *regs, int nr)
 159 {
 160         if (regs->zq_config) {
 161                 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 162                 writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 163                 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 164                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 165                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 166         }
 167         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 168         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 169         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 170 }
 171
 172 /**
 173  * Set SDRAM timings
 174  */
 175 void set_sdram_timings(const struct emif_regs *regs, int nr)
 176 {
 177         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
 178         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
 179         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
 180         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
 181         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
 182         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 183 }
 184
 185 /*
 186  * Configure EXT PHY registers for hardware leveling
 187  */
 188 static void ext_phy_settings(const struct emif_regs *regs, int nr)
 189 {
 190         /*
 191          * Enable hardware leveling on the EMIF.  For details about these
 192          * magic values please see the EMIF registers section of the TRM.
 193          */
 194         writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 195         writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
 196         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
 197         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
 198         writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
 199         writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
 200         writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
 201         writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
 202         writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
 203         writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
 204         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
 205         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
 206         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
 207         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
 208         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
 209         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
 210         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
 211         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
 212         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
 213         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
 214         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
 215         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
 216         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
 217         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
 218         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
 219         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
 220         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
 221         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
 222         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
 223         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
 224         writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 225         writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 226
 227         /*
 228          * Sequence to ensure that the PHY is again in a known state after
 229          * hardware leveling.
 230          */
 231         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 232         writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 233         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 234 }
 235
 236 /**
 237  * Configure DDR PHY
 238  */
 239 void config_ddr_phy(const struct emif_regs *regs, int nr)
 240 {
 241         /*
 242          * Disable initialization and refreshes for now until we
 243          * finish programming EMIF regs.
 244          * Also set time between rising edge of DDR_RESET to rising
 245          * edge of DDR_CKE to > 500us per memory spec.
 246          */
 247 #ifndef CONFIG_AM43XX
 248         setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 249                      EMIF_REG_INITREF_DIS_MASK);
 250 #endif
 251         if (regs->zq_config)
 252                 writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
 253
 254         writel(regs->emif_ddr_phy_ctlr_1,
 255                 &emif_reg[nr]->emif_ddr_phy_ctrl_1);
 256         writel(regs->emif_ddr_phy_ctlr_1,
 257                 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 258
 259         if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
 260                 ext_phy_settings(regs, nr);
 261 }
 262
 263 /**
 264  * Configure DDR CMD control registers
 265  */
 266 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 267 {
 268         if (!cmd)
 269                 return;
 270
 271         writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
 272         writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 273
 274         writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
 275         writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 276
 277         writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
 278         writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 279 }
 280
 281 /**
 282  * Configure DDR DATA registers
 283  */
 284 void config_ddr_data(const struct ddr_data *data, int nr)
 285 {
 286         int i;
 287
 288         if (!data)
 289                 return;
 290
 291         for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 292                 writel(data->datardsratio0,
 293                         &(ddr_data_reg[nr]+i)->dt0rdsratio0);
 294                 writel(data->datawdsratio0,
 295                         &(ddr_data_reg[nr]+i)->dt0wdsratio0);
 296                 writel(data->datawiratio0,
 297                         &(ddr_data_reg[nr]+i)->dt0wiratio0);
 298                 writel(data->datagiratio0,
 299                         &(ddr_data_reg[nr]+i)->dt0giratio0);
 300                 writel(data->datafwsratio0,
 301                         &(ddr_data_reg[nr]+i)->dt0fwsratio0);
 302                 writel(data->datawrsratio0,
 303                         &(ddr_data_reg[nr]+i)->dt0wrsratio0);
 304         }
 305 }
 306
 307 void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 308 {
 309         if (!ioregs)
 310                 return;
 311
 312         writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
 313         writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
 314         writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
 315         writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
 316         writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
 317 #ifdef CONFIG_AM43XX
 318         writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
 319         writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
 320         writel(ioregs->emif_sdram_config_ext,
 321                &ioctrl_reg->emif_sdram_config_ext);
 322 #endif
 323 }