4 * AM33XX emif4 configuration file
6 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
9 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
23 #include <asm/sizes.h>
24 #include <asm/arch/cpu.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/ddr3_defs.h>
27 #include <asm/arch/hardware.h>
28 #include <asm/arch/clock.h>
31 /* AM335X EMIF Register values */
32 #define VTP_CTRL_READY (0x1 << 5)
33 #define VTP_CTRL_ENABLE (0x1 << 6)
34 #define VTP_CTRL_LOCK_EN (0x1 << 4)
35 #define VTP_CTRL_START_EN (0x1 << 0)
38 * DDR3 force values. These are board dependent
41 * Invert clock adds an additional half cycle delay on the command
42 * interface. The additional half cycle, is usually meant to enable
43 * leveling in the situation that DQS is later than CK on the board. It
44 * also helps provide some additional margin for leveling.
46 * For the EVM this is helping us with additional room for the write
47 * leveling. Since the dqs delays are very small.
49 #define INVERT_CLOCK 0
52 * This represents the initial value for the leveling process. The
53 * value is a ratio - so 0x100 represents one cycle. The real delay
54 * is determined through the leveling process.
56 * During the leveling process, 0x20 is subtracted from the value, so
57 * we have added that to the value we want to set. We also set the
58 * values such that byte3 completes leveling after byte2 and byte1
61 #define WR_DQS_RATIO_0 0x20
62 #define WR_DQS_RATIO_1 0x20
65 * This represents the initial value for the leveling process. The
66 * value is a ratio - so 0x100 represents one cycle. The real delay
67 * is determined through the leveling process.
69 * During the leveling process, 0x20 is subtracted from the value, so
70 * we have added that to the value we want to set. We also set the
71 * values such that byte3 completes leveling after byte2 and byte1
74 #define RD_GATE_RATIO_0 0x20
75 #define RD_GATE_RATIO_1 0x20
78 * CMD_SLAVE_RATIO determines where is the command placed with respect
79 * to the clock edge. This is a ratio, implying 0x100 is one cycle.
80 * Ideally the command is centered so - this should be half cycle
81 * delay (0x80). But if invert clock is in use, an additional half
84 #define CMD_SLAVE_FROM_INV_CLOCK(i) (((i) == 0) ? 0x80 : 0x100)
85 #define CMD_SLAVE_RATIO CMD_SLAVE_FROM_INV_CLOCK(INVERT_CLOCK)
88 * EMIF Paramters. Refer the EMIF register documentation and the
89 * memory datasheet for details
91 /* For 303 MHz m_clk 3.3ns */
92 #define EMIF_TIM1 0x0668A3DB
94 * 000 0011 0011 0100 01010 001111 011 011
96 *28-25 reg_t_rp 3 - 13ns
97 *24-21 reg_t_rcd 3 - 13ns
98 *20-17 reg_t_wr 4 - 16ns
99 *16-12 reg_t_ras 10 - 36ns
100 *11-6 reg_t_rc 15 - 52ns
105 #define EMIF_TIM2 0x2A04011A
107 * 0 010 101 000000100 0000000100 011 010
109 *30-28 reg_t_xp 2 - 3nCK
110 *27-25 reg_t_odt 5 - 6nCK
111 *24-16 reg_t_xsnr 4 - 5nCK
112 *15-6 reg_t_xsrd 4 - 5nCK
113 *5-3 reg_t_rtp 3 - 4nCK
114 *2-0 reg_t_cke 2 - 3nCK
117 #define EMIF_TIM3 0x001F8309
119 * 00000000 000 111111 00 000110000 1001
121 *23-21 reg_t_ckesr 0 - LPDDR2
122 *20-15 reg_zq_zqcs 63 - 64nCK
123 *14-13 reg_t_tdqsckmax 0 - LPDDR2
124 *12-4 reg_t_rfc 48 - 161ns
128 #define EMIF_SDREF 0x20000C1A
130 * 0 0 1 0 0 000 00000000 C1A
132 *31 reg_initref_dis 0 Initialization
134 *29 reg_srt 1 extended temp.
135 *28 reg_asr 0 manual Self Refresh
139 *15-0 reg_refresh_rate C1A
142 #define EMIF_SDCFG 0x62A44AB2 /* 0x62A45032 */
144 * 011 00 010 1 01 0 01 00 01 0010 101 011 0 010
146 *31-29 reg_sdram_type 3 - DDR3
147 *28-27 reg_ibank_pos 0
148 *26-24 reg_ddr_term 2 - RZQ/2
149 *23 reg_ddr2_ddqs 1 - differential DQS
150 *22-21 reg_dyn_odt 1 - Dynamic ODT RZQ/4
151 *20 reg_ddr_disable_dll 0 - enable DLL
152 *19-18 reg_sdram_drive 1 - drive strength RZQ/7
153 *17-16 reg_cwl 0 - CAS write latency 5
154 *15-14 reg_narrow_mode 1 - 16-bit data bus width
155 *13-10 reg_cl 2 - CAS latency of 5
156 *9-7 reg_rowsize 5 - 14 row bits
157 *6-4 reg_ibank 3 - 8 banks
158 *3 reg_ebank 0 - 1 chip select
159 *2-0 reg_pagesize 2 - 10 column bits
162 #define EMIF_PHYCFG 0x0000010B
164 #define PHY_RANK_DELAY 0x01
165 #define DDR_IOCTRL_VALUE 0x18B
167 DECLARE_GLOBAL_DATA_PTR;
169 #define PHY_DLL_LOCK_DIFF 0x0f
171 struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
172 struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
173 struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
177 /* dram_init must store complete ramsize in gd->ram_size */
178 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
179 CONFIG_MAX_RAM_BANK_SIZE);
183 void dram_init_banksize(void)
185 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
186 gd->bd->bi_dram[0].size = gd->ram_size;
189 #ifdef CONFIG_SPL_BUILD
191 * Base address for EMIF instances
193 static struct emif_regs *emif_reg = {
194 (struct emif_regs *)EMIF4_0_CFG_BASE};
197 * Base address for DDR instance
199 static struct ddr_regs *ddr_reg = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
202 * Base address for ddr io control instances
204 static struct ddr_cmdtctrl *ioctrl_reg = {
205 (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
207 static void data_macro_config(void)
209 writel((WR_DQS_RATIO_0 << 10) | (WR_DQS_RATIO_0 << 0),
210 &ddr_reg->dt0.wiratio0);
211 writel((WR_DQS_RATIO_1 << 10) | (WR_DQS_RATIO_1 << 0),
212 &ddr_reg->dt1.wiratio0);
213 writel((RD_GATE_RATIO_0 << 10) | (RD_GATE_RATIO_0 << 0),
214 &ddr_reg->dt0.giratio0);
215 writel((RD_GATE_RATIO_1 << 10) | (RD_GATE_RATIO_1 << 0),
216 &ddr_reg->dt1.giratio0);
218 writel(PHY_DLL_LOCK_DIFF, &ddr_reg->dt0.dldiff0);
219 writel(PHY_DLL_LOCK_DIFF, &ddr_reg->dt1.dldiff0);
222 static void cmd_macro_config(void)
224 writel(PHY_DLL_LOCK_DIFF, &ddr_reg->cm0dldiff);
225 writel(PHY_DLL_LOCK_DIFF, &ddr_reg->cm1dldiff);
226 writel(PHY_DLL_LOCK_DIFF, &ddr_reg->cm2dldiff);
228 writel(INVERT_CLOCK, &ddr_reg->cm0iclkout);
229 writel(INVERT_CLOCK, &ddr_reg->cm1iclkout);
230 writel(INVERT_CLOCK, &ddr_reg->cm2iclkout);
233 static void config_vtp(void)
235 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
236 &vtpreg->vtp0ctrlreg);
237 writel(readl(&vtpreg->vtp0ctrlreg) & ~VTP_CTRL_START_EN,
238 &vtpreg->vtp0ctrlreg);
239 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
240 &vtpreg->vtp0ctrlreg);
243 while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
248 static void config_emif_ddr3(void)
250 /* Program EMIF0 CFG Registers */
251 writel(EMIF_PHYCFG, &emif_reg->ddrphycr);
252 writel(EMIF_PHYCFG, &emif_reg->ddrphycsr);
254 writel(EMIF_TIM1, &emif_reg->sdrtim1);
255 writel(EMIF_TIM1, &emif_reg->sdrtim1sr);
256 writel(EMIF_TIM2, &emif_reg->sdrtim2);
257 writel(EMIF_TIM2, &emif_reg->sdrtim2sr);
258 writel(EMIF_TIM3, &emif_reg->sdrtim3);
259 writel(EMIF_TIM3, &emif_reg->sdrtim3sr);
261 writel(EMIF_SDCFG, &emif_reg->sdrcr);
262 writel(EMIF_SDCFG, &emif_reg->sdrcr2);
263 writel(0x00004650, &emif_reg->sdrrcr);
264 writel(0x00004650, &emif_reg->sdrrcsr);
268 writel(EMIF_SDREF, &emif_reg->sdrrcr);
269 writel(EMIF_SDREF, &emif_reg->sdrrcsr);
272 void config_ddr(void)
274 enable_emif_clocks();
282 writel(PHY_RANK_DELAY, &ddrregs->dt0.rdelays0);
283 writel(PHY_RANK_DELAY, &ddrregs->dt1.rdelays0);
285 writel(DDR_IOCTRL_VALUE, &ioctrl_reg->cm0ioctl);
286 writel(DDR_IOCTRL_VALUE, &ioctrl_reg->cm1ioctl);
287 writel(DDR_IOCTRL_VALUE, &ioctrl_reg->cm2ioctl);
289 writel(DDR_IOCTRL_VALUE, &ioctrl_reg->dt0ioctl);
290 writel(DDR_IOCTRL_VALUE, &ioctrl_reg->dt1ioctl);
292 writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
293 writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);