arch/arm/cpu/armv7/am33xx/sys_info.c

   1 /*
   2  * sys_info.c
   3  *
   4  * System information functions
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * Derived from Beagle Board and 3430 SDP code by
   9  *      Richard Woodruff <r-woodruff2@ti.com>
  10  *      Syed Mohammed Khasim <khasim@ti.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #include <common.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/clock.h>
  20 #include <power/tps65910.h>
  21 #include <linux/compiler.h>
  22
  23 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
  24
  25 /**
  26  * get_cpu_rev(void) - extract rev info
  27  */
  28 u32 get_cpu_rev(void)
  29 {
  30         u32 id;
  31         u32 rev;
  32
  33         id = readl(DEVICE_ID);
  34         rev = (id >> 28) & 0xff;
  35
  36         return rev;
  37 }
  38
  39 /**
  40  * get_cpu_type(void) - extract cpu info
  41  */
  42 u32 get_cpu_type(void)
  43 {
  44         u32 id = 0;
  45         u32 partnum;
  46
  47         id = readl(DEVICE_ID);
  48         partnum = (id >> 12) & 0xffff;
  49
  50         return partnum;
  51 }
  52
  53 /**
  54  * get_board_rev() - setup to pass kernel board revision information
  55  * returns: 0 for the ATAG REVISION tag value.
  56  */
  57 u32 __weak get_board_rev(void)
  58 {
  59         return 0;
  60 }
  61
  62 /**
  63  * get_device_type(): tell if GP/HS/EMU/TST
  64  */
  65 u32 get_device_type(void)
  66 {
  67         int mode;
  68         mode = readl(&cstat->statusreg) & (DEVICE_MASK);
  69         return mode >>= 8;
  70 }
  71
  72 /**
  73  * get_sysboot_value(void) - return SYS_BOOT[4:0]
  74  */
  75 u32 get_sysboot_value(void)
  76 {
  77         int mode;
  78         mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
  79         return mode;
  80 }
  81
  82 #ifdef CONFIG_DISPLAY_CPUINFO
  83 static char *cpu_revs[] = {
  84                 "1.0",
  85                 "2.0",
  86                 "2.1"};
  87
  88
  89 static char *dev_types[] = {
  90                 "TST",
  91                 "EMU",
  92                 "HS",
  93                 "GP"};
  94
  95 /**
  96  * Print CPU information
  97  */
  98 int print_cpuinfo(void)
  99 {
 100         char *cpu_s, *sec_s, *rev_s;
 101
 102         switch (get_cpu_type()) {
 103         case AM335X:
 104                 cpu_s = "AM335X";
 105                 break;
 106         case TI81XX:
 107                 cpu_s = "TI81XX";
 108                 break;
 109         default:
 110                 cpu_s = "Unknown CPU type";
 111                 break;
 112         }
 113
 114         if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
 115                 rev_s = cpu_revs[get_cpu_rev()];
 116         else
 117                 rev_s = "?";
 118
 119         if (get_device_type() < ARRAY_SIZE(dev_types))
 120                 sec_s = dev_types[get_device_type()];
 121         else
 122                 sec_s = "?";
 123
 124         printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
 125
 126         return 0;
 127 }
 128 #endif  /* CONFIG_DISPLAY_CPUINFO */
 129
 130 #ifdef CONFIG_AM33XX
 131 int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
 132 {
 133         int sil_rev;
 134
 135         sil_rev = readl(&cdev->deviceid) >> 28;
 136
 137         if (sil_rev == 1)
 138                 /* PG 2.0, efuse may not be set. */
 139                 return MPUPLL_M_800;
 140         else if (sil_rev >= 2) {
 141                 /* Check what the efuse says our max speed is. */
 142                 int efuse_arm_mpu_max_freq;
 143                 efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
 144                 switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
 145                 case AM335X_ZCZ_1000:
 146                         return MPUPLL_M_1000;
 147                 case AM335X_ZCZ_800:
 148                         return MPUPLL_M_800;
 149                 case AM335X_ZCZ_720:
 150                         return MPUPLL_M_720;
 151                 case AM335X_ZCZ_600:
 152                 case AM335X_ZCE_600:
 153                         return MPUPLL_M_600;
 154                 case AM335X_ZCZ_300:
 155                 case AM335X_ZCE_300:
 156                         return MPUPLL_M_300;
 157                 }
 158         }
 159
 160         /* PG 1.0 or otherwise unknown, use the PG1.0 max */
 161         return MPUPLL_M_720;
 162 }
 163
 164 int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
 165 {
 166         /* For PG2.1 and later, we have one set of values. */
 167         if (sil_rev >= 2) {
 168                 switch (frequency) {
 169                 case MPUPLL_M_1000:
 170                         return TPS65910_OP_REG_SEL_1_3_2_5;
 171                 case MPUPLL_M_800:
 172                         return TPS65910_OP_REG_SEL_1_2_6;
 173                 case MPUPLL_M_720:
 174                         return TPS65910_OP_REG_SEL_1_2_0;
 175                 case MPUPLL_M_600:
 176                 case MPUPLL_M_300:
 177                         return TPS65910_OP_REG_SEL_1_1_3;
 178                 }
 179         }
 180
 181         /* Default to PG1.0/PG2.0 values. */
 182         return TPS65910_OP_REG_SEL_1_1_3;
 183 }
 184 #endif