arch/arm/cpu/armv7/exynos/exynos4_setup.h

   1 /*
   2  * Machine Specific Values for EXYNOS4012 based board
   3  *
   4  * Copyright (C) 2011 Samsung Electronics
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _ORIGEN_SETUP_H
  10 #define _ORIGEN_SETUP_H
  11
  12 #include <config.h>
  13 #include <version.h>
  14 #include <asm/arch/cpu.h>
  15
  16 #ifdef CONFIG_CLK_800_330_165
  17 #define DRAM_CLK_330
  18 #endif
  19 #ifdef CONFIG_CLK_1000_200_200
  20 #define DRAM_CLK_200
  21 #endif
  22 #ifdef CONFIG_CLK_1000_330_165
  23 #define DRAM_CLK_330
  24 #endif
  25 #ifdef CONFIG_CLK_1000_400_200
  26 #define DRAM_CLK_400
  27 #endif
  28
  29 /* Bus Configuration Register Address */
  30 #define ASYNC_CONFIG            0x10010350
  31
  32 /* CLK_SRC_CPU */
  33 #define MUX_HPM_SEL_MOUTAPLL            0x0
  34 #define MUX_HPM_SEL_SCLKMPLL            0x1
  35 #define MUX_CORE_SEL_MOUTAPLL           0x0
  36 #define MUX_CORE_SEL_SCLKMPLL           0x1
  37 #define MUX_MPLL_SEL_FILPLL             0x0
  38 #define MUX_MPLL_SEL_MOUTMPLLFOUT       0x1
  39 #define MUX_APLL_SEL_FILPLL             0x0
  40 #define MUX_APLL_SEL_MOUTMPLLFOUT       0x1
  41 #define CLK_SRC_CPU_VAL                 ((MUX_HPM_SEL_MOUTAPLL << 20) \
  42                                         | (MUX_CORE_SEL_MOUTAPLL << 16) \
  43                                         | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
  44                                         | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
  45
  46 /* CLK_DIV_CPU0 */
  47 #define APLL_RATIO              0x0
  48 #define PCLK_DBG_RATIO          0x1
  49 #define ATB_RATIO               0x3
  50 #define PERIPH_RATIO            0x3
  51 #define COREM1_RATIO            0x7
  52 #define COREM0_RATIO            0x3
  53 #define CORE_RATIO              0x0
  54 #define CLK_DIV_CPU0_VAL        ((APLL_RATIO << 24) \
  55                                 | (PCLK_DBG_RATIO << 20) \
  56                                 | (ATB_RATIO << 16) \
  57                                 | (PERIPH_RATIO << 12) \
  58                                 | (COREM1_RATIO << 8) \
  59                                 | (COREM0_RATIO << 4) \
  60                                 | (CORE_RATIO << 0))
  61
  62 /* CLK_DIV_CPU1 */
  63 #define HPM_RATIO               0x0
  64 #define COPY_RATIO              0x3
  65 #define CLK_DIV_CPU1_VAL        ((HPM_RATIO << 4) | (COPY_RATIO))
  66
  67 /* CLK_SRC_DMC */
  68 #define MUX_PWI_SEL_XXTI                0x0
  69 #define MUX_PWI_SEL_XUSBXTI             0x1
  70 #define MUX_PWI_SEL_SCLK_HDMI24M        0x2
  71 #define MUX_PWI_SEL_SCLK_USBPHY0        0x3
  72 #define MUX_PWI_SEL_SCLK_USBPHY1        0x4
  73 #define MUX_PWI_SEL_SCLK_HDMIPHY        0x5
  74 #define MUX_PWI_SEL_SCLKMPLL            0x6
  75 #define MUX_PWI_SEL_SCLKEPLL            0x7
  76 #define MUX_PWI_SEL_SCLKVPLL            0x8
  77 #define MUX_DPHY_SEL_SCLKMPLL           0x0
  78 #define MUX_DPHY_SEL_SCLKAPLL           0x1
  79 #define MUX_DMC_BUS_SEL_SCLKMPLL        0x0
  80 #define MUX_DMC_BUS_SEL_SCLKAPLL        0x1
  81 #define CLK_SRC_DMC_VAL                 ((MUX_PWI_SEL_XUSBXTI << 16) \
  82                                         | (MUX_DPHY_SEL_SCLKMPLL << 8) \
  83                                         | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
  84
  85 /* CLK_DIV_DMC0 */
  86 #define CORE_TIMERS_RATIO       0x1
  87 #define COPY2_RATIO             0x3
  88 #define DMCP_RATIO              0x1
  89 #define DMCD_RATIO              0x1
  90 #define DMC_RATIO               0x1
  91 #define DPHY_RATIO              0x1
  92 #define ACP_PCLK_RATIO          0x1
  93 #define ACP_RATIO               0x3
  94 #define CLK_DIV_DMC0_VAL        ((CORE_TIMERS_RATIO << 28) \
  95                                 | (COPY2_RATIO << 24) \
  96                                 | (DMCP_RATIO << 20) \
  97                                 | (DMCD_RATIO << 16) \
  98                                 | (DMC_RATIO << 12) \
  99                                 | (DPHY_RATIO << 8) \
 100                                 | (ACP_PCLK_RATIO << 4) \
 101                                 | (ACP_RATIO << 0))
 102
 103 /* CLK_DIV_DMC1 */
 104 #define DPM_RATIO               0x1
 105 #define DVSEM_RATIO             0x1
 106 #define PWI_RATIO               0x1
 107 #define CLK_DIV_DMC1_VAL        ((DPM_RATIO << 24) \
 108                                 | (DVSEM_RATIO << 16) \
 109                                 | (PWI_RATIO << 8))
 110
 111 /* CLK_SRC_TOP0 */
 112 #define MUX_ONENAND_SEL_ACLK_133        0x0
 113 #define MUX_ONENAND_SEL_ACLK_160        0x1
 114 #define MUX_ACLK_133_SEL_SCLKMPLL       0x0
 115 #define MUX_ACLK_133_SEL_SCLKAPLL       0x1
 116 #define MUX_ACLK_160_SEL_SCLKMPLL       0x0
 117 #define MUX_ACLK_160_SEL_SCLKAPLL       0x1
 118 #define MUX_ACLK_100_SEL_SCLKMPLL       0x0
 119 #define MUX_ACLK_100_SEL_SCLKAPLL       0x1
 120 #define MUX_ACLK_200_SEL_SCLKMPLL       0x0
 121 #define MUX_ACLK_200_SEL_SCLKAPLL       0x1
 122 #define MUX_VPLL_SEL_FINPLL             0x0
 123 #define MUX_VPLL_SEL_FOUTVPLL           0x1
 124 #define MUX_EPLL_SEL_FINPLL             0x0
 125 #define MUX_EPLL_SEL_FOUTEPLL           0x1
 126 #define MUX_ONENAND_1_SEL_MOUTONENAND   0x0
 127 #define MUX_ONENAND_1_SEL_SCLKVPLL      0x1
 128 #define CLK_SRC_TOP0_VAL                ((MUX_ONENAND_SEL_ACLK_133 << 28) \
 129                                         | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
 130                                         | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
 131                                         | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
 132                                         | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
 133                                         | (MUX_VPLL_SEL_FINPLL << 8) \
 134                                         | (MUX_EPLL_SEL_FINPLL << 4)\
 135                                         | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
 136
 137 /* CLK_SRC_TOP1 */
 138 #define VPLLSRC_SEL_FINPLL      0x0
 139 #define VPLLSRC_SEL_SCLKHDMI24M 0x1
 140 #define CLK_SRC_TOP1_VAL        (VPLLSRC_SEL_FINPLL)
 141
 142 /* CLK_DIV_TOP */
 143 #define ONENAND_RATIO           0x0
 144 #define ACLK_133_RATIO          0x5
 145 #define ACLK_160_RATIO          0x4
 146 #define ACLK_100_RATIO          0x7
 147 #define ACLK_200_RATIO          0x3
 148 #define CLK_DIV_TOP_VAL         ((ONENAND_RATIO << 16)  \
 149                                 | (ACLK_133_RATIO << 12)\
 150                                 | (ACLK_160_RATIO << 8) \
 151                                 | (ACLK_100_RATIO << 4) \
 152                                 | (ACLK_200_RATIO << 0))
 153
 154 /* CLK_SRC_LEFTBUS */
 155 #define MUX_GDL_SEL_SCLKMPLL    0x0
 156 #define MUX_GDL_SEL_SCLKAPLL    0x1
 157 #define CLK_SRC_LEFTBUS_VAL     (MUX_GDL_SEL_SCLKMPLL)
 158
 159 /* CLK_DIV_LEFTBUS */
 160 #define GPL_RATIO               0x1
 161 #define GDL_RATIO               0x3
 162 #define CLK_DIV_LEFTBUS_VAL     ((GPL_RATIO << 4) | (GDL_RATIO))
 163
 164 /* CLK_SRC_RIGHTBUS */
 165 #define MUX_GDR_SEL_SCLKMPLL    0x0
 166 #define MUX_GDR_SEL_SCLKAPLL    0x1
 167 #define CLK_SRC_RIGHTBUS_VAL    (MUX_GDR_SEL_SCLKMPLL)
 168
 169 /* CLK_DIV_RIGHTBUS */
 170 #define GPR_RATIO               0x1
 171 #define GDR_RATIO               0x3
 172 #define CLK_DIV_RIGHTBUS_VAL    ((GPR_RATIO << 4) | (GDR_RATIO))
 173
 174 /* CLK_SRS_FSYS: 6 = SCLKMPLL */
 175 #define SATA_SEL_SCLKMPLL       0
 176 #define SATA_SEL_SCLKAPLL       1
 177
 178 #define MMC_SEL_XXTI            0
 179 #define MMC_SEL_XUSBXTI         1
 180 #define MMC_SEL_SCLK_HDMI24M    2
 181 #define MMC_SEL_SCLK_USBPHY0    3
 182 #define MMC_SEL_SCLK_USBPHY1    4
 183 #define MMC_SEL_SCLK_HDMIPHY    5
 184 #define MMC_SEL_SCLKMPLL        6
 185 #define MMC_SEL_SCLKEPLL        7
 186 #define MMC_SEL_SCLKVPLL        8
 187
 188 #define MMCC0_SEL               MMC_SEL_SCLKMPLL
 189 #define MMCC1_SEL               MMC_SEL_SCLKMPLL
 190 #define MMCC2_SEL               MMC_SEL_SCLKMPLL
 191 #define MMCC3_SEL               MMC_SEL_SCLKMPLL
 192 #define MMCC4_SEL               MMC_SEL_SCLKMPLL
 193 #define CLK_SRC_FSYS_VAL        ((SATA_SEL_SCLKMPLL << 24) \
 194                                 | (MMCC4_SEL << 16) \
 195                                 | (MMCC3_SEL << 12) \
 196                                 | (MMCC2_SEL << 8) \
 197                                 | (MMCC1_SEL << 4) \
 198                                 | (MMCC0_SEL << 0))
 199
 200 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
 201 /* CLK_DIV_FSYS1 */
 202 #define MMC0_RATIO              0xF
 203 #define MMC0_PRE_RATIO          0x0
 204 #define MMC1_RATIO              0xF
 205 #define MMC1_PRE_RATIO          0x0
 206 #define CLK_DIV_FSYS1_VAL       ((MMC1_PRE_RATIO << 24) \
 207                                 | (MMC1_RATIO << 16) \
 208                                 | (MMC0_PRE_RATIO << 8) \
 209                                 | (MMC0_RATIO << 0))
 210
 211 /* CLK_DIV_FSYS2 */
 212 #define MMC2_RATIO              0xF
 213 #define MMC2_PRE_RATIO          0x0
 214 #define MMC3_RATIO              0xF
 215 #define MMC3_PRE_RATIO          0x0
 216 #define CLK_DIV_FSYS2_VAL       ((MMC3_PRE_RATIO << 24) \
 217                                 | (MMC3_RATIO << 16) \
 218                                 | (MMC2_PRE_RATIO << 8) \
 219                                 | (MMC2_RATIO << 0))
 220
 221 /* CLK_DIV_FSYS3 */
 222 #define MMC4_RATIO              0xF
 223 #define MMC4_PRE_RATIO          0x0
 224 #define CLK_DIV_FSYS3_VAL       ((MMC4_PRE_RATIO << 8) \
 225                                 | (MMC4_RATIO << 0))
 226
 227 /* CLK_SRC_PERIL0 */
 228 #define UART_SEL_XXTI           0
 229 #define UART_SEL_XUSBXTI        1
 230 #define UART_SEL_SCLK_HDMI24M   2
 231 #define UART_SEL_SCLK_USBPHY0   3
 232 #define UART_SEL_SCLK_USBPHY1   4
 233 #define UART_SEL_SCLK_HDMIPHY   5
 234 #define UART_SEL_SCLKMPLL       6
 235 #define UART_SEL_SCLKEPLL       7
 236 #define UART_SEL_SCLKVPLL       8
 237
 238 #define UART0_SEL               UART_SEL_SCLKMPLL
 239 #define UART1_SEL               UART_SEL_SCLKMPLL
 240 #define UART2_SEL               UART_SEL_SCLKMPLL
 241 #define UART3_SEL               UART_SEL_SCLKMPLL
 242 #define UART4_SEL               UART_SEL_SCLKMPLL
 243 #define CLK_SRC_PERIL0_VAL      ((UART4_SEL << 16) \
 244                                 | (UART3_SEL << 12) \
 245                                 | (UART2_SEL << 8) \
 246                                 | (UART1_SEL << 4) \
 247                                 | (UART0_SEL << 0))
 248
 249 /* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
 250 /* CLK_DIV_PERIL0 */
 251 #define UART0_RATIO             7
 252 #define UART1_RATIO             7
 253 #define UART2_RATIO             7
 254 #define UART3_RATIO             7
 255 #define UART4_RATIO             7
 256 #define CLK_DIV_PERIL0_VAL      ((UART4_RATIO << 16) \
 257                                 | (UART3_RATIO << 12) \
 258                                 | (UART2_RATIO << 8) \
 259                                 | (UART1_RATIO << 4) \
 260                                 | (UART0_RATIO << 0))
 261
 262 /* Clock Source CAM/FIMC */
 263 /* CLK_SRC_CAM */
 264 #define CAM0_SEL_XUSBXTI        1
 265 #define CAM1_SEL_XUSBXTI        1
 266 #define CSIS0_SEL_XUSBXTI       1
 267 #define CSIS1_SEL_XUSBXTI       1
 268
 269 #define FIMC_SEL_SCLKMPLL       6
 270 #define FIMC0_LCLK_SEL          FIMC_SEL_SCLKMPLL
 271 #define FIMC1_LCLK_SEL          FIMC_SEL_SCLKMPLL
 272 #define FIMC2_LCLK_SEL          FIMC_SEL_SCLKMPLL
 273 #define FIMC3_LCLK_SEL          FIMC_SEL_SCLKMPLL
 274
 275 #define CLK_SRC_CAM_VAL         ((CSIS1_SEL_XUSBXTI << 28) \
 276                                 | (CSIS0_SEL_XUSBXTI << 24) \
 277                                 | (CAM1_SEL_XUSBXTI << 20) \
 278                                 | (CAM0_SEL_XUSBXTI << 16) \
 279                                 | (FIMC3_LCLK_SEL << 12) \
 280                                 | (FIMC2_LCLK_SEL << 8) \
 281                                 | (FIMC1_LCLK_SEL << 4) \
 282                                 | (FIMC0_LCLK_SEL << 0))
 283
 284 /* SCLK CAM */
 285 /* CLK_DIV_CAM */
 286 #define FIMC0_LCLK_RATIO        4
 287 #define FIMC1_LCLK_RATIO        4
 288 #define FIMC2_LCLK_RATIO        4
 289 #define FIMC3_LCLK_RATIO        4
 290 #define CLK_DIV_CAM_VAL         ((FIMC3_LCLK_RATIO << 12) \
 291                                 | (FIMC2_LCLK_RATIO << 8) \
 292                                 | (FIMC1_LCLK_RATIO << 4) \
 293                                 | (FIMC0_LCLK_RATIO << 0))
 294
 295 /* SCLK MFC */
 296 /* CLK_SRC_MFC */
 297 #define MFC_SEL_MPLL            0
 298 #define MOUTMFC_0               0
 299 #define MFC_SEL                 MOUTMFC_0
 300 #define MFC_0_SEL               MFC_SEL_MPLL
 301 #define CLK_SRC_MFC_VAL         ((MFC_SEL << 8) | (MFC_0_SEL))
 302
 303
 304 /* CLK_DIV_MFC */
 305 #define MFC_RATIO               3
 306 #define CLK_DIV_MFC_VAL         (MFC_RATIO)
 307
 308 /* SCLK G3D */
 309 /* CLK_SRC_G3D */
 310 #define G3D_SEL_MPLL            0
 311 #define MOUTG3D_0               0
 312 #define G3D_SEL                 MOUTG3D_0
 313 #define G3D_0_SEL               G3D_SEL_MPLL
 314 #define CLK_SRC_G3D_VAL         ((G3D_SEL << 8) | (G3D_0_SEL))
 315
 316 /* CLK_DIV_G3D */
 317 #define G3D_RATIO               1
 318 #define CLK_DIV_G3D_VAL         (G3D_RATIO)
 319
 320 /* SCLK LCD0 */
 321 /* CLK_SRC_LCD0 */
 322 #define FIMD_SEL_SCLKMPLL       6
 323 #define MDNIE0_SEL_XUSBXTI      1
 324 #define MDNIE_PWM0_SEL_XUSBXTI  1
 325 #define MIPI0_SEL_XUSBXTI       1
 326 #define CLK_SRC_LCD0_VAL        ((MIPI0_SEL_XUSBXTI << 12) \
 327                                 | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
 328                                 | (MDNIE0_SEL_XUSBXTI << 4) \
 329                                 | (FIMD_SEL_SCLKMPLL << 0))
 330
 331 /* CLK_DIV_LCD0 */
 332 #define FIMD0_RATIO             4
 333 #define CLK_DIV_LCD0_VAL        (FIMD0_RATIO)
 334
 335 /* Required period to generate a stable clock output */
 336 /* PLL_LOCK_TIME */
 337 #define PLL_LOCKTIME            0x1C20
 338
 339 /* PLL Values */
 340 #define DISABLE                 0
 341 #define ENABLE                  1
 342 #define SET_PLL(mdiv, pdiv, sdiv)       ((ENABLE << 31)\
 343                                         | (mdiv << 16) \
 344                                         | (pdiv << 8) \
 345                                         | (sdiv << 0))
 346
 347 /* APLL_CON0 */
 348 #define APLL_MDIV               0xFA
 349 #define APLL_PDIV               0x6
 350 #define APLL_SDIV               0x1
 351 #define APLL_CON0_VAL           SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
 352
 353 /* APLL_CON1 */
 354 #define APLL_AFC_ENB            0x1
 355 #define APLL_AFC                0xC
 356 #define APLL_CON1_VAL           ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
 357
 358 /* MPLL_CON0 */
 359 #define MPLL_MDIV               0xC8
 360 #define MPLL_PDIV               0x6
 361 #define MPLL_SDIV               0x1
 362 #define MPLL_CON0_VAL           SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
 363
 364 /* MPLL_CON1 */
 365 #define MPLL_AFC_ENB            0x0
 366 #define MPLL_AFC                0x1C
 367 #define MPLL_CON1_VAL           ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
 368
 369 /* EPLL_CON0 */
 370 #define EPLL_MDIV               0x30
 371 #define EPLL_PDIV               0x3
 372 #define EPLL_SDIV               0x2
 373 #define EPLL_CON0_VAL           SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
 374
 375 /* EPLL_CON1 */
 376 #define EPLL_K                  0x0
 377 #define EPLL_CON1_VAL           (EPLL_K >> 0)
 378
 379 /* VPLL_CON0 */
 380 #define VPLL_MDIV               0x35
 381 #define VPLL_PDIV               0x3
 382 #define VPLL_SDIV               0x2
 383 #define VPLL_CON0_VAL           SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
 384
 385 /* VPLL_CON1 */
 386 #define VPLL_SSCG_EN            DISABLE
 387 #define VPLL_SEL_PF_DN_SPREAD   0x0
 388 #define VPLL_MRR                0x11
 389 #define VPLL_MFR                0x0
 390 #define VPLL_K                  0x400
 391 #define VPLL_CON1_VAL           ((VPLL_SSCG_EN << 31)\
 392                                 | (VPLL_SEL_PF_DN_SPREAD << 29) \
 393                                 | (VPLL_MRR << 24) \
 394                                 | (VPLL_MFR << 16) \
 395                                 | (VPLL_K << 0))
 396
 397 /* DMC */
 398 #define DIRECT_CMD_NOP  0x07000000
 399 #define DIRECT_CMD_ZQ   0x0a000000
 400 #define DIRECT_CMD_CHIP1_SHIFT  (1 << 20)
 401 #define MEM_TIMINGS_MSR_COUNT   4
 402 #define CTRL_START      (1 << 0)
 403 #define CTRL_DLL_ON     (1 << 1)
 404 #define AREF_EN         (1 << 5)
 405 #define DRV_TYPE        (1 << 6)
 406
 407 struct mem_timings {
 408         unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
 409         unsigned timingref;
 410         unsigned timingrow;
 411         unsigned timingdata;
 412         unsigned timingpower;
 413         unsigned zqcontrol;
 414         unsigned control0;
 415         unsigned control1;
 416         unsigned control2;
 417         unsigned concontrol;
 418         unsigned prechconfig;
 419         unsigned memcontrol;
 420         unsigned memconfig0;
 421         unsigned memconfig1;
 422         unsigned dll_resync;
 423         unsigned dll_on;
 424 };
 425
 426 /* MIU */
 427 /* MIU Config Register Offsets*/
 428 #define APB_SFR_INTERLEAVE_CONF_OFFSET  0x400
 429 #define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
 430 #define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
 431 #define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
 432 #define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET   0x810
 433 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET        0x818
 434 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET  0x820
 435 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET        0x828
 436 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET  0x830
 437
 438 #ifdef CONFIG_ORIGEN
 439 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
 440 #define APB_SFR_INTERLEAVE_CONF_VAL     0x20001507
 441 #define APB_SFR_ARBRITATION_CONF_VAL    0x00000001
 442 #endif
 443
 444 #define INTERLEAVE_ADDR_MAP_START_ADDR  0x40000000
 445 #define INTERLEAVE_ADDR_MAP_END_ADDR    0xbfffffff
 446 #define INTERLEAVE_ADDR_MAP_EN          0x00000001
 447
 448 #ifdef CONFIG_MIU_1BIT_INTERLEAVED
 449 /* Interleave_bit0: 0xC*/
 450 #define APB_SFR_INTERLEAVE_CONF_VAL     0x0000000c
 451 #endif
 452 #ifdef CONFIG_MIU_2BIT_INTERLEAVED
 453 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
 454 #define APB_SFR_INTERLEAVE_CONF_VAL     0x2000150c
 455 #endif
 456 #define SLAVE0_SINGLE_ADDR_MAP_START_ADDR       0x40000000
 457 #define SLAVE0_SINGLE_ADDR_MAP_END_ADDR         0x7fffffff
 458 #define SLAVE1_SINGLE_ADDR_MAP_START_ADDR       0x80000000
 459 #define SLAVE1_SINGLE_ADDR_MAP_END_ADDR         0xbfffffff
 460 /* Enable SME0 and SME1*/
 461 #define APB_SFR_SLV_ADDR_MAP_CONF_VAL           0x00000006
 462
 463 #define FORCE_DLL_RESYNC        3
 464 #define DLL_CONTROL_ON          1
 465
 466 #define DIRECT_CMD1     0x00020000
 467 #define DIRECT_CMD2     0x00030000
 468 #define DIRECT_CMD3     0x00010002
 469 #define DIRECT_CMD4     0x00000328
 470
 471 #define CTRL_ZQ_MODE_NOTERM     (0x1 << 0)
 472 #define CTRL_ZQ_START           (0x1 << 1)
 473 #define CTRL_ZQ_DIV             (0 << 4)
 474 #define CTRL_ZQ_MODE_DDS        (0x7 << 8)
 475 #define CTRL_ZQ_MODE_TERM       (0x2 << 11)
 476 #define CTRL_ZQ_FORCE_IMPN      (0x5 << 14)
 477 #define CTRL_ZQ_FORCE_IMPP      (0x6 << 17)
 478 #define CTRL_DCC                (0xE38 << 20)
 479 #define ZQ_CONTROL_VAL          (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
 480                                 | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
 481                                 | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
 482                                 | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
 483
 484 #define ASYNC                   (0 << 0)
 485 #define CLK_RATIO               (1 << 1)
 486 #define DIV_PIPE                (1 << 3)
 487 #define AWR_ON                  (1 << 4)
 488 #define AREF_DISABLE            (0 << 5)
 489 #define DRV_TYPE_DISABLE        (0 << 6)
 490 #define CHIP0_NOT_EMPTY         (0 << 8)
 491 #define CHIP1_NOT_EMPTY         (0 << 9)
 492 #define DQ_SWAP_DISABLE         (0 << 10)
 493 #define QOS_FAST_DISABLE        (0 << 11)
 494 #define RD_FETCH                (0x3 << 12)
 495 #define TIMEOUT_LEVEL0          (0xFFF << 16)
 496 #define CONCONTROL_VAL          (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
 497                                 | AREF_DISABLE | DRV_TYPE_DISABLE\
 498                                 | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
 499                                 | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
 500                                 | RD_FETCH | TIMEOUT_LEVEL0)
 501
 502 #define CLK_STOP_DISABLE        (0 << 1)
 503 #define DPWRDN_DISABLE          (0 << 2)
 504 #define DPWRDN_TYPE             (0 << 3)
 505 #define TP_DISABLE              (0 << 4)
 506 #define DSREF_DIABLE            (0 << 5)
 507 #define ADD_LAT_PALL            (1 << 6)
 508 #define MEM_TYPE_DDR3           (0x6 << 8)
 509 #define MEM_WIDTH_32            (0x2 << 12)
 510 #define NUM_CHIP_2              (1 << 16)
 511 #define BL_8                    (0x3 << 20)
 512 #define MEMCONTROL_VAL          (CLK_STOP_DISABLE | DPWRDN_DISABLE\
 513                                 | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
 514                                 | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
 515                                 | NUM_CHIP_2 | BL_8)
 516
 517
 518 #define CHIP_BANK_8             (0x3 << 0)
 519 #define CHIP_ROW_14             (0x2 << 4)
 520 #define CHIP_COL_10             (0x3 << 8)
 521 #define CHIP_MAP_INTERLEAVED    (1 << 12)
 522 #define CHIP_MASK               (0xe0 << 16)
 523 #ifdef CONFIG_MIU_LINEAR
 524 #define CHIP0_BASE              (0x40 << 24)
 525 #define CHIP1_BASE              (0x60 << 24)
 526 #else
 527 #define CHIP0_BASE              (0x20 << 24)
 528 #define CHIP1_BASE              (0x40 << 24)
 529 #endif
 530 #define MEMCONFIG0_VAL          (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
 531                                 | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
 532 #define MEMCONFIG1_VAL          (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
 533                                 | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
 534
 535 #define TP_CNT                  (0xff << 24)
 536 #define PRECHCONFIG             TP_CNT
 537
 538 #define CTRL_OFF                (0 << 0)
 539 #define CTRL_DLL_OFF            (0 << 1)
 540 #define CTRL_HALF               (0 << 2)
 541 #define CTRL_DFDQS              (1 << 3)
 542 #define DQS_DELAY               (0 << 4)
 543 #define CTRL_START_POINT        (0x10 << 8)
 544 #define CTRL_INC                (0x10 << 16)
 545 #define CTRL_FORCE              (0x71 << 24)
 546 #define CONTROL0_VAL            (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
 547                                 | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
 548                                 | CTRL_INC | CTRL_FORCE)
 549
 550 #define CTRL_SHIFTC             (0x6 << 0)
 551 #define CTRL_REF                (8 << 4)
 552 #define CTRL_SHGATE             (1 << 29)
 553 #define TERM_READ_EN            (1 << 30)
 554 #define TERM_WRITE_EN           (1 << 31)
 555 #define CONTROL1_VAL            (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
 556                                 | TERM_READ_EN | TERM_WRITE_EN)
 557
 558 #define CONTROL2_VAL            0x00000000
 559
 560 #ifdef CONFIG_ORIGEN
 561 #define TIMINGREF_VAL           0x000000BB
 562 #define TIMINGROW_VAL           0x4046654f
 563 #define TIMINGDATA_VAL          0x46400506
 564 #define TIMINGPOWER_VAL         0x52000A3C
 565 #else
 566 #define TIMINGREF_VAL           0x000000BC
 567 #ifdef DRAM_CLK_330
 568 #define TIMINGROW_VAL           0x3545548d
 569 #define TIMINGDATA_VAL          0x45430506
 570 #define TIMINGPOWER_VAL         0x4439033c
 571 #endif
 572 #ifdef DRAM_CLK_400
 573 #define TIMINGROW_VAL           0x45430506
 574 #define TIMINGDATA_VAL          0x56500506
 575 #define TIMINGPOWER_VAL         0x5444033d
 576 #endif
 577 #endif
 578 #endif