arch/arm/cpu/armv7/keystone/clock-k2hk.c

   1 /*
   2  * Keystone2: get clk rate for K2HK
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/clock_defs.h>
  13
  14 const struct keystone_pll_regs keystone_pll_regs[] = {
  15         [CORE_PLL]      = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
  16         [PASS_PLL]      = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
  17         [TETRIS_PLL]    = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
  18         [DDR3A_PLL]     = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
  19         [DDR3B_PLL]     = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
  20 };
  21
  22 /**
  23  * pll_freq_get - get pll frequency
  24  * Fout = Fref * NF(mult) / NR(prediv) / OD
  25  * @pll:        pll identifier
  26  */
  27 static unsigned long pll_freq_get(int pll)
  28 {
  29         unsigned long mult = 1, prediv = 1, output_div = 2;
  30         unsigned long ret;
  31         u32 tmp, reg;
  32
  33         if (pll == CORE_PLL) {
  34                 ret = external_clk[sys_clk];
  35                 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
  36                         /* PLL mode */
  37                         tmp = __raw_readl(KS2_MAINPLLCTL0);
  38                         prediv = (tmp & PLL_DIV_MASK) + 1;
  39                         mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
  40                                 (pllctl_reg_read(pll, mult) &
  41                                  PLLM_MULT_LO_MASK)) + 1;
  42                         output_div = ((pllctl_reg_read(pll, secctl) >>
  43                                        PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
  44
  45                         ret = ret / prediv / output_div * mult;
  46                 }
  47         } else {
  48                 switch (pll) {
  49                 case PASS_PLL:
  50                         ret = external_clk[pa_clk];
  51                         reg = KS2_PASSPLLCTL0;
  52                         break;
  53                 case TETRIS_PLL:
  54                         ret = external_clk[tetris_clk];
  55                         reg = KS2_ARMPLLCTL0;
  56                         break;
  57                 case DDR3A_PLL:
  58                         ret = external_clk[ddr3a_clk];
  59                         reg = KS2_DDR3APLLCTL0;
  60                         break;
  61                 case DDR3B_PLL:
  62                         ret = external_clk[ddr3b_clk];
  63                         reg = KS2_DDR3BPLLCTL0;
  64                         break;
  65                 default:
  66                         return 0;
  67                 }
  68
  69                 tmp = __raw_readl(reg);
  70
  71                 if (!(tmp & PLLCTL_BYPASS)) {
  72                         /* Bypass disabled */
  73                         prediv = (tmp & PLL_DIV_MASK) + 1;
  74                         mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
  75                         output_div = ((tmp >> PLL_CLKOD_SHIFT) &
  76                                       PLL_CLKOD_MASK) + 1;
  77                         ret = ((ret / prediv) * mult) / output_div;
  78                 }
  79         }
  80
  81         return ret;
  82 }
  83
  84 unsigned long clk_get_rate(unsigned int clk)
  85 {
  86         switch (clk) {
  87         case core_pll_clk:      return pll_freq_get(CORE_PLL);
  88         case pass_pll_clk:      return pll_freq_get(PASS_PLL);
  89         case tetris_pll_clk:    return pll_freq_get(TETRIS_PLL);
  90         case ddr3a_pll_clk:     return pll_freq_get(DDR3A_PLL);
  91         case ddr3b_pll_clk:     return pll_freq_get(DDR3B_PLL);
  92         case sys_clk0_1_clk:
  93         case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
  94         case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
  95         case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
  96         case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
  97         case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
  98         case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
  99         case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
 100         case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
 101         case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
 102         case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
 103         case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
 104         case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
 105         case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
 106         case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
 107         case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
 108         default:
 109                 break;
 110         }
 111
 112         return 0;
 113 }