arch/arm/cpu/armv7/keystone/clock-k2l.c

   1 /*
   2  * Keystone2: get clk rate for K2L
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/clock_defs.h>
  13
  14 const struct keystone_pll_regs keystone_pll_regs[] = {
  15         [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
  16         [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
  17         [TETRIS_PLL] = {KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
  18         [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
  19 };
  20
  21 int dev_speeds[] = {
  22         SPD800,
  23         SPD1000,
  24         SPD1200,
  25         SPD800,
  26         SPD800,
  27         SPD800,
  28         SPD800,
  29         SPD800,
  30         SPD1200,
  31         SPD1000,
  32         SPD800,
  33         SPD800,
  34         SPD800,
  35 };
  36
  37 int arm_speeds[] = {
  38         SPD800,
  39         SPD1000,
  40         SPD1200,
  41         SPD1350,
  42         SPD1400,
  43         SPD800,
  44         SPD1400,
  45         SPD1350,
  46         SPD1200,
  47         SPD1000,
  48         SPD800,
  49         SPD800,
  50         SPD800,
  51 };
  52
  53 /**
  54  * pll_freq_get - get pll frequency
  55  * Fout = Fref * NF(mult) / NR(prediv) / OD
  56  * @pll:        pll identifier
  57  */
  58 static unsigned long pll_freq_get(int pll)
  59 {
  60         unsigned long mult = 1, prediv = 1, output_div = 2;
  61         unsigned long ret;
  62         u32 tmp, reg;
  63
  64         if (pll == CORE_PLL) {
  65                 ret = external_clk[sys_clk];
  66                 if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
  67                         /* PLL mode */
  68                         tmp = __raw_readl(KS2_MAINPLLCTL0);
  69                         prediv = (tmp & PLL_DIV_MASK) + 1;
  70                         mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
  71                                 (pllctl_reg_read(pll, mult) &
  72                                 PLLM_MULT_LO_MASK)) + 1;
  73                         output_div = ((pllctl_reg_read(pll, secctl) >>
  74                                         PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
  75
  76                         ret = ret / prediv / output_div * mult;
  77                 }
  78         } else {
  79                 switch (pll) {
  80                 case PASS_PLL:
  81                         ret = external_clk[pa_clk];
  82                         reg = KS2_PASSPLLCTL0;
  83                         break;
  84                 case TETRIS_PLL:
  85                         ret = external_clk[tetris_clk];
  86                         reg = KS2_ARMPLLCTL0;
  87                         break;
  88                 case DDR3_PLL:
  89                         ret = external_clk[ddr3_clk];
  90                         reg = KS2_DDR3APLLCTL0;
  91                         break;
  92                 default:
  93                         return 0;
  94                 }
  95
  96                 tmp = __raw_readl(reg);
  97                 if (!(tmp & PLLCTL_BYPASS)) {
  98                         /* Bypass disabled */
  99                         prediv = (tmp & PLL_DIV_MASK) + 1;
 100                         mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
 101                         output_div = ((tmp >> PLL_CLKOD_SHIFT) &
 102                                       PLL_CLKOD_MASK) + 1;
 103                         ret = ((ret / prediv) * mult) / output_div;
 104                 }
 105         }
 106
 107         return ret;
 108 }
 109
 110 unsigned long clk_get_rate(unsigned int clk)
 111 {
 112         switch (clk) {
 113         case core_pll_clk:      return pll_freq_get(CORE_PLL);
 114         case pass_pll_clk:      return pll_freq_get(PASS_PLL);
 115         case tetris_pll_clk:    return pll_freq_get(TETRIS_PLL);
 116         case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
 117         case sys_clk0_1_clk:
 118         case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
 119         case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
 120         case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
 121         case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
 122         case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
 123         case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
 124         case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
 125         case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
 126         case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
 127         case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
 128         case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
 129         case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
 130         case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
 131         case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
 132         case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
 133         default:
 134                 break;
 135         }
 136
 137         return 0;
 138 }