arch/arm/cpu/armv7/keystone/clock.c

   1 /*
   2  * Keystone2: pll initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/clock_defs.h>
  13
  14 static void wait_for_completion(const struct pll_init_data *data)
  15 {
  16         int i;
  17         for (i = 0; i < 100; i++) {
  18                 sdelay(450);
  19                 if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
  20                         break;
  21         }
  22 }
  23
  24 void init_pll(const struct pll_init_data *data)
  25 {
  26         u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
  27
  28         pllm = data->pll_m - 1;
  29         plld = (data->pll_d - 1) & PLL_DIV_MASK;
  30         pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
  31
  32         if (data->pll == MAIN_PLL) {
  33                 /* The requered delay before main PLL configuration */
  34                 sdelay(210000);
  35
  36                 tmp = pllctl_reg_read(data->pll, secctl);
  37
  38                 if (tmp & (PLLCTL_BYPASS)) {
  39                         setbits_le32(keystone_pll_regs[data->pll].reg1,
  40                                      BIT(MAIN_ENSAT_OFFSET));
  41
  42                         pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
  43                                            PLLCTL_PLLENSRC);
  44                         sdelay(340);
  45
  46                         pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
  47                         pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
  48                         sdelay(21000);
  49
  50                         pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
  51                 } else {
  52                         pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
  53                                            PLLCTL_PLLENSRC);
  54                         sdelay(340);
  55                 }
  56
  57                 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
  58
  59                 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
  60                                 PLLM_MULT_HI_SMASK, (pllm << 6));
  61
  62                 /* Set the BWADJ     (12 bit field)  */
  63                 tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
  64                 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
  65                                 PLL_BWADJ_LO_SMASK,
  66                                 (tmp_ctl << PLL_BWADJ_LO_SHIFT));
  67                 clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
  68                                 PLL_BWADJ_HI_MASK,
  69                                 (tmp_ctl >> 8));
  70
  71                 /*
  72                  * Set the pll divider (6 bit field) *
  73                  * PLLD[5:0] is located in MAINPLLCTL0
  74                  */
  75                 clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
  76                                 PLL_DIV_MASK, plld);
  77
  78                 /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
  79                 pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
  80                                (pllod << PLL_CLKOD_SHIFT));
  81                 wait_for_completion(data);
  82
  83                 pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
  84                 pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
  85                 pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
  86                 pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
  87                 pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
  88
  89                 pllctl_reg_setbits(data->pll, alnctl, 0x1f);
  90
  91                 /*
  92                  * Set GOSET bit in PLLCMD to initiate the GO operation
  93                  * to change the divide
  94                  */
  95                 pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
  96                 sdelay(1500); /* wait for the phase adj */
  97                 wait_for_completion(data);
  98
  99                 /* Reset PLL */
 100                 pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
 101                 sdelay(21000);  /* Wait for a minimum of 7 us*/
 102                 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
 103                 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
 104
 105                 pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
 106
 107                 tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
 108
 109 #ifndef CONFIG_SOC_K2E
 110         } else if (data->pll == TETRIS_PLL) {
 111                 bwadj = pllm >> 1;
 112                 /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
 113                 setbits_le32(keystone_pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
 114                 /*
 115                  * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
 116                  * only applicable for Kepler
 117                  */
 118                 clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
 119                 /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
 120                 setbits_le32(keystone_pll_regs[data->pll].reg1 ,
 121                              PLL_PLLRST | PLLCTL_ENSAT);
 122
 123                 /*
 124                  * 3 Program PLLM and PLLD in PLLCTL0 register
 125                  * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
 126                  * PLLCTL1 register. BWADJ value must be set
 127                  * to ((PLLM + 1) >> 1) – 1)
 128                  */
 129                 tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
 130                         (pllm << 6) |
 131                         (plld & PLL_DIV_MASK) |
 132                         (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
 133                 __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 134
 135                 /* Set BWADJ[11:8] bits */
 136                 tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 137                 tmp &= ~(PLL_BWADJ_HI_MASK);
 138                 tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
 139                 __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 140                 /*
 141                  * 5 Wait for at least 5 us based on the reference
 142                  * clock (PLL reset time)
 143                  */
 144                 sdelay(21000);  /* Wait for a minimum of 7 us*/
 145
 146                 /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
 147                 clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
 148                 /*
 149                  * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
 150                  * (PLL lock time)
 151                  */
 152                 sdelay(105000);
 153                 /* 8 disable bypass */
 154                 clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 155                 /*
 156                  * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
 157                  * only applicable for Kepler
 158                  */
 159                 setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
 160 #endif
 161         } else {
 162                 setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
 163                 /*
 164                  * process keeps state of Bypass bit while programming
 165                  * all other DDR PLL settings
 166                  */
 167                 tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
 168                 tmp &= PLLCTL_BYPASS;   /* clear everything except Bypass */
 169
 170                 /*
 171                  * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
 172                  * bypass disabled
 173                  */
 174                 bwadj = pllm >> 1;
 175                 tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) |
 176                         (pllm << PLL_MULT_SHIFT) |
 177                         (plld & PLL_DIV_MASK) |
 178                         (pllod << PLL_CLKOD_SHIFT);
 179                 __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
 180
 181                 /* Set BWADJ[11:8] bits */
 182                 tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
 183                 tmp &= ~(PLL_BWADJ_HI_MASK);
 184                 tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
 185
 186                 /* set PLL Select (bit 13) for PASS PLL */
 187                 if (data->pll == PASS_PLL)
 188                         tmp |= PLLCTL_PAPLL;
 189
 190                 __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
 191
 192                 /* Reset bit: bit 14 for both DDR3 & PASS PLL */
 193                 tmp = PLL_PLLRST;
 194                 /* Set RESET bit = 1 */
 195                 setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 196                 /* Wait for a minimum of 7 us*/
 197                 sdelay(21000);
 198                 /* Clear RESET bit */
 199                 clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
 200                 sdelay(105000);
 201
 202                 /* clear BYPASS (Enable PLL Mode) */
 203                 clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
 204                 sdelay(21000);  /* Wait for a minimum of 7 us*/
 205         }
 206
 207         /*
 208          * This is required to provide a delay between multiple
 209          * consequent PPL configurations
 210          */
 211         sdelay(210000);
 212 }
 213
 214 void init_plls(int num_pll, struct pll_init_data *config)
 215 {
 216         int i;
 217
 218         for (i = 0; i < num_pll; i++)
 219                 init_pll(&config[i]);
 220 }