3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
29 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
30 [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
31 [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
32 [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
34 [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
38 #define AHB_CLK_ROOT 133333333
39 #define SZ_DEC_1M 1000000
40 #define PLL_PD_MAX 16 /* Actual pd+1 */
41 #define PLL_MFI_MAX 15
49 struct fixed_pll_mfd {
54 const struct fixed_pll_mfd fixed_mfd[] = {
65 #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
66 #define PLL_FREQ_MIN(ref_clk) \
67 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
68 #define MAX_DDR_CLK 420000000
69 #define NFC_CLK_MAX 34000000
71 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
73 int clk_enable(struct clk *clk)
80 if (clk->usecount++ == 0) {
83 ret = clk->enable(clk);
90 void clk_disable(struct clk *clk)
95 if (!(--clk->usecount)) {
99 if (clk->usecount < 0) {
100 printf("%s: clk %p (%s) underflow\n", __func__, clk, clk->name);
105 int clk_get_usecount(struct clk *clk)
110 return clk->usecount;
113 u32 clk_get_rate(struct clk *clk)
121 struct clk *clk_get_parent(struct clk *clk)
129 int clk_set_rate(struct clk *clk, unsigned long rate)
131 if (clk && clk->set_rate)
132 clk->set_rate(clk, rate);
136 long clk_round_rate(struct clk *clk, unsigned long rate)
138 if (clk == NULL || !clk->round_rate)
141 return clk->round_rate(clk, rate);
144 int clk_set_parent(struct clk *clk, struct clk *parent)
146 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
147 clk ? clk->parent : NULL);
149 if (!clk || clk == parent)
152 if (clk->set_parent) {
155 ret = clk->set_parent(clk, parent);
159 clk->parent = parent;
163 void set_usboh3_clk(void)
165 clrsetbits_le32(&mxc_ccm->cscmr1,
166 MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
167 MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
168 clrsetbits_le32(&mxc_ccm->cscdr1,
169 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
170 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
171 MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
172 MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
175 void enable_usboh3_clk(unsigned char enable)
177 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
179 clrsetbits_le32(&mxc_ccm->CCGR2,
180 MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
181 MXC_CCM_CCGR2_USBOH3_60M(cg));
184 void ipu_clk_enable(void)
186 /* IPU root clock derived from AXI B */
187 clrsetbits_le32(&mxc_ccm->cbcmr, MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK,
188 MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(1));
190 setbits_le32(&mxc_ccm->CCGR5,
191 MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
193 /* Handshake with IPU when certain clock rates are changed. */
194 clrbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
196 /* Handshake with IPU when LPM is entered as its enabled. */
197 clrbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
200 void ipu_clk_disable(void)
202 clrbits_le32(&mxc_ccm->CCGR5,
203 MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK));
205 /* Handshake with IPU when certain clock rates are changed. */
206 setbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK);
208 /* Handshake with IPU when LPM is entered as its enabled. */
209 setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS);
212 void ipu_di_clk_enable(int di)
216 setbits_le32(&mxc_ccm->CCGR6,
217 MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
220 setbits_le32(&mxc_ccm->CCGR6,
221 MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
224 printf("%s: Invalid DI index %d\n", __func__, di);
228 void ipu_di_clk_disable(int di)
232 clrbits_le32(&mxc_ccm->CCGR6,
233 MXC_CCM_CCGR6_IPU_DI0(MXC_CCM_CCGR_CG_MASK));
236 clrbits_le32(&mxc_ccm->CCGR6,
237 MXC_CCM_CCGR6_IPU_DI1(MXC_CCM_CCGR_CG_MASK));
240 printf("%s: Invalid DI index %d\n", __func__, di);
245 void ldb_clk_enable(int ldb)
249 setbits_le32(&mxc_ccm->CCGR6,
250 MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
253 setbits_le32(&mxc_ccm->CCGR6,
254 MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
257 printf("%s: Invalid LDB index %d\n", __func__, ldb);
261 void ldb_clk_disable(int ldb)
265 clrbits_le32(&mxc_ccm->CCGR6,
266 MXC_CCM_CCGR6_LDB_DI0(MXC_CCM_CCGR_CG_MASK));
269 clrbits_le32(&mxc_ccm->CCGR6,
270 MXC_CCM_CCGR6_LDB_DI1(MXC_CCM_CCGR_CG_MASK));
273 printf("%s: Invalid LDB index %d\n", __func__, ldb);
278 #ifdef CONFIG_I2C_MXC
279 /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
280 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
284 #if defined(CONFIG_MX51)
286 #elif defined(CONFIG_MX53)
290 mask = MXC_CCM_CCGR_CG_MASK <<
291 (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
293 setbits_le32(&mxc_ccm->CCGR1, mask);
295 clrbits_le32(&mxc_ccm->CCGR1, mask);
300 void set_usb_phy_clk(void)
302 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
305 #if defined(CONFIG_MX51)
306 void enable_usb_phy1_clk(unsigned char enable)
308 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
310 clrsetbits_le32(&mxc_ccm->CCGR2,
311 MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
312 MXC_CCM_CCGR2_USB_PHY(cg));
315 void enable_usb_phy2_clk(unsigned char enable)
317 /* i.MX51 has a single USB PHY clock, so do nothing here. */
319 #elif defined(CONFIG_MX53)
320 void enable_usb_phy1_clk(unsigned char enable)
322 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
324 clrsetbits_le32(&mxc_ccm->CCGR4,
325 MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
326 MXC_CCM_CCGR4_USB_PHY1(cg));
329 void enable_usb_phy2_clk(unsigned char enable)
331 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
333 clrsetbits_le32(&mxc_ccm->CCGR4,
334 MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
335 MXC_CCM_CCGR4_USB_PHY2(cg));
340 * Calculate the frequency of PLLn.
342 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
344 uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
345 uint64_t refclk, temp;
348 ctrl = readl(&pll->ctrl);
350 if (ctrl & MXC_DPLLC_CTL_HFSM) {
351 mfn = readl(&pll->hfs_mfn);
352 mfd = readl(&pll->hfs_mfd);
353 op = readl(&pll->hfs_op);
355 mfn = readl(&pll->mfn);
356 mfd = readl(&pll->mfd);
357 op = readl(&pll->op);
360 mfd &= MXC_DPLLC_MFD_MFD_MASK;
361 mfn &= MXC_DPLLC_MFN_MFN_MASK;
362 pdf = op & MXC_DPLLC_OP_PDF_MASK;
363 mfi = MXC_DPLLC_OP_MFI_RD(op);
370 if (mfn >= 0x04000000) {
377 if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
380 do_div(refclk, pdf + 1);
381 temp = refclk * mfn_abs;
382 do_div(temp, mfd + 1);
395 * This function returns the Frequency Pre-Multiplier clock.
397 static u32 get_fpm(void)
400 u32 ccr = readl(&mxc_ccm->ccr);
402 if (ccr & MXC_CCM_CCR_FPM_MULT)
407 return MXC_CLK32 * mult;
412 * This function returns the low power audio clock.
414 static u32 get_lp_apm(void)
417 u32 ccsr = readl(&mxc_ccm->ccsr);
419 if (ccsr & MXC_CCM_CCSR_LP_APM)
420 #if defined(CONFIG_MX51)
422 #elif defined(CONFIG_MX53)
423 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
434 u32 get_mcu_main_clk(void)
438 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
439 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
440 return freq / (reg + 1);
444 * Get the rate of peripheral's root clock.
446 u32 get_periph_clk(void)
450 reg = readl(&mxc_ccm->cbcdr);
451 if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
452 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
453 reg = readl(&mxc_ccm->cbcmr);
454 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
456 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
458 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
468 * Get the rate of ipg clock.
470 static u32 get_ipg_clk(void)
472 uint32_t freq, reg, div;
474 freq = get_ahb_clk();
476 reg = readl(&mxc_ccm->cbcdr);
477 div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
483 * Get the rate of ipg_per clock.
485 static u32 get_ipg_per_clk(void)
487 u32 freq, pred1, pred2, podf;
489 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
490 return get_ipg_clk();
492 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
495 freq = get_periph_clk();
496 podf = readl(&mxc_ccm->cbcdr);
497 pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
498 pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
499 podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
500 return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
503 /* Get the output clock rate of a standard PLL MUX for peripherals. */
504 static u32 get_standard_pll_sel_clk(u32 clk_sel)
508 switch (clk_sel & 0x3) {
510 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
513 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
516 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
527 * Get the rate of uart clk.
529 static u32 get_uart_clk(void)
531 unsigned int clk_sel, freq, reg, pred, podf;
533 reg = readl(&mxc_ccm->cscmr1);
534 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
535 freq = get_standard_pll_sel_clk(clk_sel);
537 reg = readl(&mxc_ccm->cscdr1);
538 pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
539 podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
540 freq /= (pred + 1) * (podf + 1);
546 * get cspi clock rate.
548 static u32 imx_get_cspiclk(void)
550 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
551 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
552 u32 cscdr2 = readl(&mxc_ccm->cscdr2);
554 pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
555 pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
556 clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
557 freq = get_standard_pll_sel_clk(clk_sel);
558 ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
563 * get esdhc clock rate.
565 static u32 get_esdhc_clk(u32 port)
567 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
568 u32 cscmr1 = readl(&mxc_ccm->cscmr1);
569 u32 cscdr1 = readl(&mxc_ccm->cscdr1);
573 clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
574 pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
575 podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
578 clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
579 pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
580 podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
583 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
584 return get_esdhc_clk(1);
586 return get_esdhc_clk(0);
588 if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
589 return get_esdhc_clk(1);
591 return get_esdhc_clk(0);
596 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
600 static u32 get_axi_a_clk(void)
602 u32 cbcdr = readl(&mxc_ccm->cbcdr);
603 u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
605 return get_periph_clk() / (pdf + 1);
608 static u32 get_axi_b_clk(void)
610 u32 cbcdr = readl(&mxc_ccm->cbcdr);
611 u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
613 return get_periph_clk() / (pdf + 1);
616 static u32 get_emi_slow_clk(void)
618 u32 cbcdr = readl(&mxc_ccm->cbcdr);
619 u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
620 u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
623 return get_ahb_clk() / (pdf + 1);
625 return get_periph_clk() / (pdf + 1);
628 static u32 get_ddr_clk(void)
631 u32 cbcmr = readl(&mxc_ccm->cbcmr);
632 u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
634 u32 cbcdr = readl(&mxc_ccm->cbcdr);
635 if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
636 u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
638 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
639 ret_val /= ddr_clk_podf + 1;
644 switch (ddr_clk_sel) {
646 ret_val = get_axi_a_clk();
649 ret_val = get_axi_b_clk();
652 ret_val = get_emi_slow_clk();
655 ret_val = get_ahb_clk();
665 * The API of get mxc clocks.
667 unsigned int mxc_get_clock(enum mxc_clock clk)
671 return get_mcu_main_clk();
673 return get_ahb_clk();
675 return get_ipg_clk();
678 return get_ipg_per_clk();
680 return get_uart_clk();
682 return imx_get_cspiclk();
684 return get_esdhc_clk(0);
686 return get_esdhc_clk(1);
688 return get_esdhc_clk(2);
690 return get_esdhc_clk(3);
692 return get_ipg_clk();
694 return get_ahb_clk();
696 return get_ddr_clk();
703 u32 imx_get_uartclk(void)
705 return get_uart_clk();
708 u32 imx_get_fecclk(void)
710 return get_ipg_clk();
713 static int gcd(int m, int n)
728 * This is to calculate various parameters based on reference clock and
729 * targeted clock based on the equation:
730 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
731 * This calculation is based on a fixed MFD value for simplicity.
733 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
735 u64 pd, mfi = 1, mfn, mfd, t1;
736 u32 n_target = target;
740 * Make sure targeted freq is in the valid range.
741 * Otherwise the following calculation might be wrong!!!
743 if (n_target < PLL_FREQ_MIN(ref) ||
744 n_target > PLL_FREQ_MAX(ref)) {
745 printf("Targeted peripheral clock should be within [%d - %d]\n",
746 PLL_FREQ_MIN(ref) / SZ_DEC_1M,
747 PLL_FREQ_MAX(ref) / SZ_DEC_1M);
751 for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
752 if (fixed_mfd[i].ref_clk_hz == ref) {
753 mfd = fixed_mfd[i].mfd;
758 if (i == ARRAY_SIZE(fixed_mfd))
761 /* Use n_target and n_ref to avoid overflow */
762 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
764 do_div(t1, (4 * n_ref));
766 if (mfi > PLL_MFI_MAX)
773 * Now got pd and mfi already
775 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
783 debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
784 ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
798 #define calc_div(tgt_clk, src_clk, limit) ({ \
800 if (((src_clk) % (tgt_clk)) <= 100) \
801 v = (src_clk) / (tgt_clk); \
803 v = ((src_clk) / (tgt_clk)) + 1;\
809 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
811 __raw_writel(0x1232, &pll->ctrl); \
812 __raw_writel(0x2, &pll->config); \
813 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
815 __raw_writel(fn, &(pll->mfn)); \
816 __raw_writel((fd) - 1, &pll->mfd); \
817 __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
819 __raw_writel(fn, &pll->hfs_mfn); \
820 __raw_writel((fd) - 1, &pll->hfs_mfd); \
821 __raw_writel(0x1232, &pll->ctrl); \
822 while (!__raw_readl(&pll->ctrl) & 0x1) \
826 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
828 u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
829 struct mxc_pll_reg *pll = mxc_plls[index];
833 /* Switch ARM to PLL2 clock */
834 __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
835 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
836 pll_param->mfi, pll_param->mfn,
839 __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
842 /* Switch to pll2 bypass clock */
843 __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
844 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
845 pll_param->mfi, pll_param->mfn,
848 __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
851 /* Switch to pll3 bypass clock */
852 __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
853 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
854 pll_param->mfi, pll_param->mfn,
857 __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
861 /* Switch to pll4 bypass clock */
862 __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
863 CHANGE_PLL_SETTINGS(pll, pll_param->pd,
864 pll_param->mfi, pll_param->mfn,
867 __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
877 /* Config CPU clock */
878 static int config_core_clk(u32 ref, u32 freq)
881 struct pll_param pll_param;
883 memset(&pll_param, 0, sizeof(struct pll_param));
885 /* The case that periph uses PLL1 is not considered here */
886 ret = calc_pll_params(ref, freq, &pll_param);
888 printf("Error: Can't find pll parameters for %u.%03uMHz ref %u.%03uMHz\n",
889 freq / 1000000, freq / 1000 % 1000,
890 ref / 1000000, ref / 1000 % 1000);
894 return config_pll_clk(PLL1_CLOCK, &pll_param);
897 static int config_nfc_clk(u32 nfc_clk)
899 u32 parent_rate = get_emi_slow_clk();
904 div = parent_rate / nfc_clk;
907 if (parent_rate / div > NFC_CLK_MAX)
909 clrsetbits_le32(&mxc_ccm->cbcdr,
910 MXC_CCM_CBCDR_NFC_PODF_MASK,
911 MXC_CCM_CBCDR_NFC_PODF(div - 1));
912 while (readl(&mxc_ccm->cdhipr) != 0)
917 void enable_nfc_clk(unsigned char enable)
919 unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
921 clrsetbits_le32(&mxc_ccm->CCGR5,
922 MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
923 MXC_CCM_CCGR5_EMI_ENFC(cg));
926 /* Config main_bus_clock for periphs */
927 static int config_periph_clk(u32 ref, u32 freq)
930 struct pll_param pll_param;
932 memset(&pll_param, 0, sizeof(struct pll_param));
934 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
935 ret = calc_pll_params(ref, freq, &pll_param);
937 printf("Error:Can't find pll parameters: %d\n",
941 switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
942 readl(&mxc_ccm->cbcmr))) {
944 return config_pll_clk(PLL1_CLOCK, &pll_param);
947 return config_pll_clk(PLL3_CLOCK, &pll_param);
957 static int config_ddr_clk(u32 emi_clk)
960 s32 shift = 0, clk_sel, div = 1;
961 u32 cbcmr = readl(&mxc_ccm->cbcmr);
963 if (emi_clk > MAX_DDR_CLK) {
964 printf("Warning:DDR clock should not exceed %d MHz\n",
965 MAX_DDR_CLK / SZ_DEC_1M);
966 emi_clk = MAX_DDR_CLK;
969 clk_src = get_periph_clk();
970 /* Find DDR clock input */
971 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
989 if ((clk_src % emi_clk) < 10000000)
990 div = clk_src / emi_clk;
992 div = (clk_src / emi_clk) + 1;
996 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
997 while (readl(&mxc_ccm->cdhipr) != 0)
999 writel(0x0, &mxc_ccm->ccdr);
1005 * This function assumes the expected core clock has to be changed by
1006 * modifying the PLL. This is NOT true always but for most of the times,
1007 * it is. So it assumes the PLL output freq is the same as the expected
1008 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1009 * In the latter case, it will try to increase the presc value until
1010 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1011 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1012 * on the targeted PLL and reference input clock to the PLL. Lastly,
1013 * it sets the register based on these values along with the dividers.
1014 * Note 1) There is no value checking for the passed-in divider values
1015 * so the caller has to make sure those values are sensible.
1016 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1017 * exceed NFC_CLK_MAX.
1018 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
1019 * 177MHz for higher voltage, this function fixes the max to 133MHz.
1020 * 4) This function should not have allowed diag_printf() calls since
1021 * the serial driver has been stoped. But leave then here to allow
1022 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1024 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1030 if (config_core_clk(ref, freq))
1033 case MXC_PERIPH_CLK:
1034 if (config_periph_clk(ref, freq))
1038 if (config_ddr_clk(freq))
1042 if (config_nfc_clk(freq))
1046 printf("Warning:Unsupported or invalid clock type\n");
1054 * The clock for the external interface can be set to use internal clock
1055 * if fuse bank 4, row 3, bit 2 is set.
1056 * This is an undocumented feature and it was confirmed by Freescale's support:
1057 * Fuses (but not pins) may be used to configure SATA clocks.
1058 * Particularly the i.MX53 Fuse_Map contains the next information
1059 * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C)
1060 * '00' - 100MHz (External)
1061 * '01' - 50MHz (External)
1062 * '10' - 120MHz, internal (USB PHY)
1065 void mxc_set_sata_internal_clock(void)
1068 (u32 *)(IIM_BASE_ADDR + 0x180c);
1072 clrsetbits_le32(tmp_base, 0x6, 0x4);
1077 * Dump some core clockes.
1079 #define pr_clk_val(c, v) { \
1080 printf("%-11s %3lu.%03lu MHz\n", #c, \
1081 (v) / 1000000, (v) / 1000 % 1000); \
1084 #define pr_clk(c) { \
1085 unsigned long __clk = mxc_get_clock(MXC_##c##_CLK); \
1086 pr_clk_val(c, __clk); \
1089 int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1093 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
1094 pr_clk_val(PLL1, freq);
1095 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
1096 pr_clk_val(PLL2, freq);
1097 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
1098 pr_clk_val(PLL3, freq);
1100 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
1101 pr_clk_val(PLL4, freq);
1109 #ifdef CONFIG_MXC_SPI
1115 /***************************************************/
1118 clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,