2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
11 #include <generated/asm-offsets.h>
12 #include <linux/linkage.h>
14 .section ".text.init", "x"
16 .macro init_arm_erratum
17 /* ARM erratum ID #468414 */
18 mrc 15, 0, r1, c1, c0, 1
19 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
20 mcr 15, 0, r1, c1, c0, 1
24 * L2CC Cache setup/invalidation/disable
27 /* explicitly disable L2 cache */
28 mrc 15, 0, r0, c1, c0, 1
30 mcr 15, 0, r0, c1, c0, 1
32 /* reconfigure L2 cache aux control reg */
33 ldr r0, =0xC0 | /* tag RAM */ \
34 0x4 | /* data RAM */ \
35 1 << 24 | /* disable write allocate delay */ \
36 1 << 23 | /* disable write allocate combine */ \
37 1 << 22 /* disable write allocate */
39 #if defined(CONFIG_MX51)
40 ldr r3, [r4, #ROM_SI_REV]
43 /* disable write combine for TO 2 and lower revs */
44 orrls r0, r0, #1 << 25
47 mcr 15, 1, r0, c9, c0, 2
50 /* AIPS setup - Only setup MPROTx registers.
51 * The PACR default values are good.*/
54 * Set all MPROTx to be non-bufferable, trusted for R/W,
55 * not forced to user-mode.
57 ldr r0, =AIPS1_BASE_ADDR
61 ldr r0, =AIPS2_BASE_ADDR
65 * Clear the on and off peripheral modules Supervisor Protect bit
66 * for SDMA to access them. Did not change the AIPS control registers
67 * (offset 0x20) access type
74 /* VPU and IPU given higher priority (0x4)
75 * IPU accesses with ID=0x1 given highest priority (=0xA)
77 ldr r0, =M4IF_BASE_ADDR
93 .macro setup_pll pll, freq
105 str r1, [r3, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
107 str r1, [r3, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
109 ldr r1, [r2, #W_DP_OP]
110 str r1, [r3, #PLL_DP_OP]
111 str r1, [r3, #PLL_DP_HFS_OP]
113 ldr r1, [r2, #W_DP_MFD]
114 str r1, [r3, #PLL_DP_MFD]
115 str r1, [r3, #PLL_DP_HFS_MFD]
117 ldr r1, [r2, #W_DP_MFN]
118 str r1, [r3, #PLL_DP_MFN]
119 str r1, [r3, #PLL_DP_HFS_MFN]
122 str r1, [r3, #PLL_DP_CTL]
123 1: ldr r1, [r3, #PLL_DP_CTL]
127 /* r10 saved upper lr */
130 .macro setup_pll_errata pll, freq
132 str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
134 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
135 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
140 str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
141 str r5, [r2, #PLL_DP_HFS_MFN]
144 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
146 2: ldr r1, [r2, #PLL_DP_CONFIG]
150 ldr r1, =100 /* Wait at least 4 us */
155 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
159 ldr r0, =CCM_BASE_ADDR
160 #if defined (CONFIG_MX51)
161 /* Gate off clocks to the peripherals first */
163 str r1, [r0, #CLKCTL_CCGR0]
164 str r4, [r0, #CLKCTL_CCGR1]
165 str r4, [r0, #CLKCTL_CCGR2]
166 str r4, [r0, #CLKCTL_CCGR3]
169 str r1, [r0, #CLKCTL_CCGR4]
171 str r1, [r0, #CLKCTL_CCGR5]
173 str r1, [r0, #CLKCTL_CCGR6]
175 /* Disable IPU and HSC dividers */
177 str r1, [r0, #CLKCTL_CCDR]
179 /* Make sure to switch the DDR away from PLL 1 */
181 str r1, [r0, #CLKCTL_CBCDR]
182 /* make sure divider effective */
183 1: ldr r1, [r0, #CLKCTL_CDHIPR]
187 /* Switch ARM to step clock */
189 str r1, [r0, #CLKCTL_CCSR]
191 #if defined(CONFIG_MX51_PLL_ERRATA)
192 setup_pll PLL1_BASE_ADDR, 864
193 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
195 #if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
196 setup_pll PLL1_BASE_ADDR, 800
197 #elif CONFIG_SYS_CPU_CLK == 600
198 setup_pll PLL1_BASE_ADDR, 600
200 #error Unsupported CONFIG_SYS_CPU_CLK value
204 setup_pll PLL3_BASE_ADDR, 665
206 /* Switch peripheral to PLL 3 */
207 ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
208 str r1, [r0, #CLKCTL_CBCMR]
210 str r1, [r0, #CLKCTL_CBCDR]
211 setup_pll PLL2_BASE_ADDR, 665
213 /* Switch peripheral to PLL2 */
215 str r1, [r0, #CLKCTL_CBCDR]
216 ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
217 str r1, [r0, #CLKCTL_CBCMR]
219 setup_pll PLL3_BASE_ADDR, 216
221 /* Set the platform clock dividers */
222 ldr r0, =ARM_BASE_ADDR
226 ldr r0, =CCM_BASE_ADDR
228 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
229 ldr r3, [r4, #ROM_SI_REV]
234 str r1, [r0, #CLKCTL_CACRR]
236 /* Switch ARM back to PLL 1 */
237 str r4, [r0, #CLKCTL_CCSR]
240 /* Use lp_apm (24MHz) source for perclk */
241 ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
242 str r1, [r0, #CLKCTL_CBCMR]
243 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
244 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
245 str r1, [r0, #CLKCTL_CBCDR]
247 /* Restore the default values in the Gate registers */
249 str r1, [r0, #CLKCTL_CCGR0]
250 str r1, [r0, #CLKCTL_CCGR1]
251 str r1, [r0, #CLKCTL_CCGR2]
252 str r1, [r0, #CLKCTL_CCGR3]
253 str r1, [r0, #CLKCTL_CCGR4]
254 str r1, [r0, #CLKCTL_CCGR5]
255 str r1, [r0, #CLKCTL_CCGR6]
257 /* Use PLL 2 for UART's, get 66.5MHz from it */
259 str r1, [r0, #CLKCTL_CSCMR1]
261 str r1, [r0, #CLKCTL_CSCDR1]
262 /* make sure divider effective */
263 1: ldr r1, [r0, #CLKCTL_CDHIPR]
267 str r4, [r0, #CLKCTL_CCDR]
269 /* for cko - for ARM div by 8 */
271 add r1, r1, #0x00000F0
272 str r1, [r0, #CLKCTL_CCOSR]
273 #else /* CONFIG_MX53 */
274 /* Gate off clocks to the peripherals first */
276 str r1, [r0, #CLKCTL_CCGR0]
277 str r4, [r0, #CLKCTL_CCGR1]
278 str r4, [r0, #CLKCTL_CCGR2]
279 str r4, [r0, #CLKCTL_CCGR3]
280 str r4, [r0, #CLKCTL_CCGR7]
282 str r1, [r0, #CLKCTL_CCGR4]
284 str r1, [r0, #CLKCTL_CCGR5]
286 str r1, [r0, #CLKCTL_CCGR6]
288 /* Switch ARM to step clock */
290 str r1, [r0, #CLKCTL_CCSR]
292 #if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
293 setup_pll PLL1_BASE_ADDR, 800
294 #elif CONFIG_SYS_CPU_CLK == 600
295 setup_pll PLL1_BASE_ADDR, 600
297 #error Unsupported CONFIG_SYS_CPU_CLK value
300 setup_pll PLL3_BASE_ADDR, 400
302 /* Switch peripheral to PLL3 */
304 str r1, [r0, #CLKCTL_CBCMR]
306 str r1, [r0, #CLKCTL_CBCDR]
307 /* make sure change is effective */
308 1: ldr r1, [r0, #CLKCTL_CDHIPR]
312 setup_pll PLL2_BASE_ADDR, 400
314 /* Switch peripheral to PLL2 */
316 str r1, [r0, #CLKCTL_CBCDR]
319 str r1, [r0, #CLKCTL_CBCMR]
321 /* change uart clk parent to pll2 */
322 ldr r1, [r0, #CLKCTL_CSCMR1]
324 orr r1, r1, #(0x1 << 24)
325 str r1, [r0, #CLKCTL_CSCMR1]
327 /* make sure change is effective */
328 1: ldr r1, [r0, #CLKCTL_CDHIPR]
332 setup_pll PLL4_BASE_ADDR, 455
334 #else /* CONFIG_TX53 */
335 /* Switch peripheral to PLL 3 */
336 ldr r1, [r0, #CLKCTL_CBCMR]
338 orr r1, r1, #(1 << 12)
339 str r1, [r0, #CLKCTL_CBCMR]
341 ldr r1, [r0, #CLKCTL_CBCDR]
342 orr r1, r1, #(1 << 25)
343 str r1, [r0, #CLKCTL_CBCDR]
345 /* make sure change is effective */
346 ldr r1, [r0, #CLKCTL_CDHIPR]
350 #if CONFIG_SYS_SDRAM_CLK == 533
351 setup_pll PLL2_BASE_ADDR, 533
352 #elif CONFIG_SYS_SDRAM_CLK == 400
353 setup_pll PLL2_BASE_ADDR, 400
354 #elif CONFIG_SYS_SDRAM_CLK == 333
355 setup_pll PLL2_BASE_ADDR, 333
357 #error Unsupported CONFIG_SYS_SDRAM_CLK
360 /* Switch peripheral to PLL2 */
361 ldr r1, [r0, #CLKCTL_CBCDR]
363 str r1, [r0, #CLKCTL_CBCDR]
365 ldr r1, [r0, #CLKCTL_CBCMR]
368 str r1, [r0, #CLKCTL_CBCMR]
370 setup_pll PLL3_BASE_ADDR, 216
372 /* Set the platform clock dividers */
373 ldr r0, =ARM_BASE_ADDR
377 ldr r0, =CCM_BASE_ADDR
379 str r1, [r0, #CLKCTL_CACRR]
381 /* Switch ARM back to PLL 1. */
383 str r1, [r0, #CLKCTL_CCSR]
385 /* make uart div=6 */
386 ldr r1, [r0, #CLKCTL_CSCDR1]
389 str r1, [r0, #CLKCTL_CSCDR1]
390 /* make sure divider effective */
391 1: ldr r1, [r0, #CLKCTL_CDHIPR]
395 /* Restore the default values in the Gate registers */
397 str r1, [r0, #CLKCTL_CCGR0]
398 str r1, [r0, #CLKCTL_CCGR1]
399 str r1, [r0, #CLKCTL_CCGR2]
400 str r1, [r0, #CLKCTL_CCGR3]
401 str r1, [r0, #CLKCTL_CCGR4]
402 str r1, [r0, #CLKCTL_CCGR5]
403 str r1, [r0, #CLKCTL_CCGR6]
404 str r1, [r0, #CLKCTL_CCGR7]
407 str r1, [r0, #CLKCTL_CCDR]
409 /* for cko - for ARM div by 8 */
411 add r1, r1, #0x00000F0
412 str r1, [r0, #CLKCTL_CCOSR]
414 #endif /* CONFIG_MX53 */
418 ldr r0, =WDOG1_BASE_ADDR
425 mov r4, #0 /* Fix R4 to 0 */
427 #if defined(CONFIG_SYS_MAIN_PWR_ON)
428 ldr r0, =GPIO1_BASE_ADDR
448 ENDPROC(lowlevel_init)
450 /* Board level setting value */
451 #if defined(CONFIG_MX51_PLL_ERRATA)
452 W_DP_864: .word DP_OP_864
455 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
457 W_DP_800: .word DP_OP_800
461 #if defined(CONFIG_MX51)
462 W_DP_665: .word DP_OP_665
465 W_DP_600: .word DP_OP_600
469 W_DP_216: .word DP_OP_216
472 W_DP_400: .word DP_OP_400
475 W_DP_455: .word DP_OP_455
478 W_DP_533: .word DP_OP_533