2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/imx-regs.h>
24 #include <generated/asm-offsets.h>
25 #include <linux/linkage.h>
28 * L2CC Cache setup/invalidation/disable
31 /* explicitly disable L2 cache */
32 mrc 15, 0, r0, c1, c0, 1
34 mcr 15, 0, r0, c1, c0, 1
36 /* reconfigure L2 cache aux control reg */
37 mov r0, #0xC0 /* tag RAM */
38 add r0, r0, #0x4 /* data RAM */
39 orr r0, r0, #(1 << 24) /* disable write allocate delay */
40 orr r0, r0, #(1 << 23) /* disable write allocate combine */
41 orr r0, r0, #(1 << 22) /* disable write allocate */
43 #if defined(CONFIG_MX51)
45 ldr r3, [r1, #ROM_SI_REV]
48 /* disable write combine for TO 2 and lower revs */
49 orrls r0, r0, #(1 << 25)
52 mcr 15, 1, r0, c9, c0, 2
55 /* AIPS setup - Only setup MPROTx registers.
56 * The PACR default values are good.*/
59 * Set all MPROTx to be non-bufferable, trusted for R/W,
60 * not forced to user-mode.
62 ldr r0, =AIPS1_BASE_ADDR
66 ldr r0, =AIPS2_BASE_ADDR
70 * Clear the on and off peripheral modules Supervisor Protect bit
71 * for SDMA to access them. Did not change the AIPS control registers
72 * (offset 0x20) access type
79 /* VPU and IPU given higher priority (0x4)
80 * IPU accesses with ID=0x1 given highest priority (=0xA)
82 ldr r0, =M4IF_BASE_ADDR
99 .macro setup_pll pll, freq
102 str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
104 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
106 ldr r1, W_DP_OP_\freq
107 str r1, [r2, #PLL_DP_OP]
108 str r1, [r2, #PLL_DP_HFS_OP]
110 ldr r1, W_DP_MFD_\freq
111 str r1, [r2, #PLL_DP_MFD]
112 str r1, [r2, #PLL_DP_HFS_MFD]
114 ldr r1, W_DP_MFN_\freq
115 str r1, [r2, #PLL_DP_MFN]
116 str r1, [r2, #PLL_DP_HFS_MFN]
119 str r1, [r2, #PLL_DP_CTL]
121 ldr r1, [r2, #PLL_DP_CTL]
126 .macro setup_pll_errata pll, freq
129 str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
131 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
132 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
137 str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
138 str r5, [r2, #PLL_DP_HFS_MFN]
141 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
143 2: ldr r1, [r2, #PLL_DP_CONFIG]
147 ldr r1, =100 /* Wait at least 4 us */
152 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
156 ldr r0, =CCM_BASE_ADDR
158 #if defined(CONFIG_MX51)
159 /* Gate of clocks to the peripherals first */
161 str r1, [r0, #CLKCTL_CCGR0]
163 str r1, [r0, #CLKCTL_CCGR1]
164 str r1, [r0, #CLKCTL_CCGR2]
165 str r1, [r0, #CLKCTL_CCGR3]
168 str r1, [r0, #CLKCTL_CCGR4]
170 str r1, [r0, #CLKCTL_CCGR5]
172 str r1, [r0, #CLKCTL_CCGR6]
174 /* Disable IPU and HSC dividers */
176 str r1, [r0, #CLKCTL_CCDR]
178 /* Make sure to switch the DDR away from PLL 1 */
180 str r1, [r0, #CLKCTL_CBCDR]
181 /* make sure divider effective */
182 1: ldr r1, [r0, #CLKCTL_CDHIPR]
185 #elif defined(CONFIG_TX53)
186 @ CCGR registers have been setup via DCD
189 str r1, [r0, #CLKCTL_CCGR0]
191 str r1, [r0, #CLKCTL_CCGR1]
192 str r1, [r0, #CLKCTL_CCGR2]
193 str r1, [r0, #CLKCTL_CCGR3]
194 str r1, [r0, #CLKCTL_CCGR7]
197 str r1, [r0, #CLKCTL_CCGR4]
199 str r1, [r0, #CLKCTL_CCGR5]
201 str r1, [r0, #CLKCTL_CCGR6]
204 /* Switch ARM to step clock */
206 str r1, [r0, #CLKCTL_CCSR]
208 #if defined(CONFIG_MX51_PLL_ERRATA)
209 setup_pll PLL1_BASE_ADDR, 864
210 setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
212 #if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
213 setup_pll PLL1_BASE_ADDR, 800
214 #elif CONFIG_SYS_CPU_CLK == 600
215 setup_pll PLL1_BASE_ADDR, 600
217 #error Unsupported CONFIG_SYS_CPU_CLK value
221 #if defined(CONFIG_MX51)
222 setup_pll PLL3_BASE_ADDR, 665
224 /* Switch peripheral to PLL 3 */
226 orr r1, r1, #CONFIG_SYS_DDR_CLKSEL
227 str r1, [r0, #CLKCTL_CBCMR]
229 str r1, [r0, #CLKCTL_CBCDR]
230 setup_pll PLL2_BASE_ADDR, 665
232 /* Switch peripheral to PLL2 */
234 str r1, [r0, #CLKCTL_CBCDR]
236 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
237 str r1, [r0, #CLKCTL_CBCMR]
238 #elif defined(CONFIG_TX53)
239 setup_pll PLL3_BASE_ADDR, 400
241 /* Switch peripheral to PLL 3 */
242 ldr r1, [r0, #CLKCTL_CBCMR]
244 orr r1, r1, #(1 << 12)
245 str r1, [r0, #CLKCTL_CBCMR]
247 ldr r1, [r0, #CLKCTL_CBCDR]
248 orr r1, r1, #(1 << 25)
249 str r1, [r0, #CLKCTL_CBCDR]
251 /* make sure change is effective */
252 ldr r1, [r0, #CLKCTL_CDHIPR]
255 #if CONFIG_SYS_SDRAM_CLK == 400
256 setup_pll PLL2_BASE_ADDR, 400
257 #elif CONFIG_SYS_SDRAM_CLK == 333
258 setup_pll PLL2_BASE_ADDR, 333
260 #error Unsupported CONFIG_SYS_SDRAM_CLK
262 /* Switch peripheral to PLL2 */
263 ldr r0, =CCM_BASE_ADDR
264 ldr r1, [r0, #CLKCTL_CBCDR]
266 str r1, [r0, #CLKCTL_CBCDR]
268 ldr r1, [r0, #CLKCTL_CBCMR]
271 str r1, [r0, #CLKCTL_CBCMR]
273 /* make sure change is effective */
275 ldr r1, [r0, #CLKCTL_CDHIPR]
279 setup_pll PLL3_BASE_ADDR, 216
281 /* Set the platform clock dividers */
282 ldr r0, =ARM_BASE_ADDR
286 ldr r0, =CCM_BASE_ADDR
288 #if defined(CONFIG_MX51)
289 /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
291 ldr r3, [r1, #ROM_SI_REV]
298 str r1, [r0, #CLKCTL_CACRR]
299 /* Switch ARM back to PLL 1 */
301 str r1, [r0, #CLKCTL_CCSR]
303 #if defined(CONFIG_MX51)
305 /* Use lp_apm (24MHz) source for perclk */
307 orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
308 str r1, [r0, #CLKCTL_CBCMR]
309 /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
310 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
311 str r1, [r0, #CLKCTL_CBCDR]
314 /* Restore the default values in the Gate registers */
316 str r1, [r0, #CLKCTL_CCGR0]
317 str r1, [r0, #CLKCTL_CCGR1]
318 str r1, [r0, #CLKCTL_CCGR2]
319 str r1, [r0, #CLKCTL_CCGR3]
320 str r1, [r0, #CLKCTL_CCGR4]
321 str r1, [r0, #CLKCTL_CCGR5]
322 str r1, [r0, #CLKCTL_CCGR6]
323 #if defined(CONFIG_MX53)
324 str r1, [r0, #CLKCTL_CCGR7]
328 #if !defined(CONFIG_TX53)
329 #if defined(CONFIG_MX51)
330 /* Use PLL 2 for UART's, get 66.5MHz from it */
332 str r1, [r0, #CLKCTL_CSCMR1]
334 str r1, [r0, #CLKCTL_CSCDR1]
335 #elif defined(CONFIG_MX53)
336 /* Switch peripheral to PLL2 */
338 orr r1, r1, #(2 << 10)
339 orr r1, r1, #(0 << 16)
340 orr r1, r1, #(1 << 19)
341 str r1, [r0, #CLKCTL_CBCDR]
344 str r1, [r0, #CLKCTL_CBCMR]
345 /* Change uart clk parent to pll2*/
346 ldr r1, [r0, #CLKCTL_CSCMR1]
348 orr r1, r1, #(0x1 << 24)
349 str r1, [r0, #CLKCTL_CSCMR1]
350 ldr r1, [r0, #CLKCTL_CSCDR1]
353 str r1, [r0, #CLKCTL_CSCDR1]
355 /* make sure divider effective */
356 1: ldr r1, [r0, #CLKCTL_CDHIPR]
361 str r1, [r0, #CLKCTL_CCDR]
363 /* for cko - for ARM div by 8 */
365 add r1, r1, #0x00000F0
366 str r1, [r0, #CLKCTL_CCOSR]
370 ldr r0, =WDOG1_BASE_ADDR
375 .section ".text.init", "x"
378 #if defined(CONFIG_MX51)
379 ldr r0, =GPIO1_BASE_ADDR
381 orr r1, r1, #(1 << 23)
384 orr r1, r1, #(1 << 23)
396 /* r12 saved upper lr*/
398 ENDPROC(lowlevel_init)
400 /* Board level setting value */
401 W_DP_OP_864: .word DP_OP_864
402 W_DP_MFD_864: .word DP_MFD_864
403 W_DP_MFN_864: .word DP_MFN_864
404 W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
405 W_DP_OP_800: .word DP_OP_800
406 W_DP_MFD_800: .word DP_MFD_800
407 W_DP_MFN_800: .word DP_MFN_800
408 W_DP_OP_665: .word DP_OP_665
409 W_DP_MFD_665: .word DP_MFD_665
410 W_DP_MFN_665: .word DP_MFN_665
411 W_DP_OP_600: .word DP_OP_600
412 W_DP_MFD_600: .word DP_MFD_600
413 W_DP_MFN_600: .word DP_MFN_600
414 W_DP_OP_400: .word DP_OP_400
415 W_DP_MFD_400: .word DP_MFD_400
416 W_DP_MFN_400: .word DP_MFN_400
417 W_DP_OP_333: .word DP_OP_333
418 W_DP_MFD_333: .word DP_MFD_333
419 W_DP_MFN_333: .word DP_MFN_333
420 W_DP_OP_216: .word DP_OP_216
421 W_DP_MFD_216: .word DP_MFD_216
422 W_DP_MFN_216: .word DP_MFN_216