arch/arm/cpu/armv7/mx5/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/sys_proto.h>
  14
  15 #include <asm/errno.h>
  16 #include <asm/io.h>
  17 #include <asm/imx-common/boot_mode.h>
  18
  19 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
  20 #error "CPU_TYPE not defined"
  21 #endif
  22
  23 #ifdef CONFIG_HW_WATCHDOG
  24 #define wdog_base       ((void *)WDOG1_BASE_ADDR)
  25 #define WDOG_WCR        0x00
  26 #define WCR_WDE         (1 << 2)
  27 #define WDOG_WSR        0x02
  28
  29 void hw_watchdog_reset(void)
  30 {
  31         if (readw(wdog_base + WDOG_WCR) & WCR_WDE) {
  32                 static u16 toggle = 0xaaaa;
  33
  34                 writew(toggle, wdog_base + WDOG_WSR);
  35                 toggle ^= 0xffff;
  36         }
  37 }
  38 #endif
  39
  40 u32 get_cpu_rev(void)
  41 {
  42 #ifdef CONFIG_MX51
  43         int system_rev = 0x51000;
  44 #else
  45         int system_rev = 0x53000;
  46 #endif
  47         int reg = __raw_readl(ROM_SI_REV);
  48
  49 #if defined(CONFIG_MX51)
  50         switch (reg) {
  51         case 0x02:
  52                 system_rev |= CHIP_REV_1_1;
  53                 break;
  54         case 0x10:
  55                 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
  56                         system_rev |= CHIP_REV_2_5;
  57                 else
  58                         system_rev |= CHIP_REV_2_0;
  59                 break;
  60         case 0x20:
  61                 system_rev |= CHIP_REV_3_0;
  62                 break;
  63         default:
  64                 system_rev |= CHIP_REV_1_0;
  65                 break;
  66         }
  67 #else
  68         if (reg < 0x20)
  69                 system_rev |= CHIP_REV_1_0;
  70         else
  71                 system_rev |= reg;
  72 #endif
  73         return system_rev;
  74 }
  75
  76 #ifdef CONFIG_REVISION_TAG
  77 u32 __weak get_board_rev(void)
  78 {
  79         return get_cpu_rev();
  80 }
  81 #endif
  82
  83 #ifndef CONFIG_SYS_DCACHE_OFF
  84 void enable_caches(void)
  85 {
  86         /* Enable D-cache. I-cache is already enabled in start.S */
  87         dcache_enable();
  88 }
  89 #endif
  90
  91 #if defined(CONFIG_FEC_MXC)
  92 static void __imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  93 {
  94         int i;
  95         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  96         struct fuse_bank *bank = &iim->bank[1];
  97         struct fuse_bank1_regs *fuse =
  98                         (struct fuse_bank1_regs *)bank->fuse_regs;
  99
 100         for (i = 0; i < 6; i++)
 101                 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
 102 }
 103
 104 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 105         __attribute__((weak, alias("__imx_get_mac_from_fuse")));
 106
 107 #endif
 108
 109 void set_chipselect_size(int const cs_size)
 110 {
 111         unsigned int reg;
 112         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 113         reg = readl(&iomuxc_regs->gpr1);
 114
 115         switch (cs_size) {
 116         case CS0_128:
 117                 reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
 118                 reg |= 0x5;
 119                 break;
 120         case CS0_64M_CS1_64M:
 121                 reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
 122                 reg |= 0x1B;
 123                 break;
 124         case CS0_64M_CS1_32M_CS2_32M:
 125                 reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
 126                 reg |= 0x4B;
 127                 break;
 128         case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
 129                 reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
 130                 reg |= 0x249;
 131                 break;
 132         default:
 133                 printf("Unknown chip select size: %d\n", cs_size);
 134                 break;
 135         }
 136
 137         writel(reg, &iomuxc_regs->gpr1);
 138 }
 139
 140 #if 1
 141 void cpu_cache_initialization(void)
 142 {
 143         printf("Enabling L2 cache\n");
 144         asm volatile(
 145                 "mrc 15, 0, r0, c1, c0, 1\n"
 146                 "orr r0, r0, #0x2\n"
 147                 "mcr 15, 0, r0, c1, c0, 1\n"
 148                 : : : "r0", "memory"
 149                 );
 150 }
 151 #endif
 152
 153 #ifdef CONFIG_MX53
 154 void boot_mode_apply(unsigned cfg_val)
 155 {
 156         writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
 157 }
 158 /*
 159  * cfg_val will be used for
 160  * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 161  *
 162  * If bit 28 of LPGR is set upon watchdog reset,
 163  * bits[25:0] of LPGR will move to SBMR.
 164  */
 165 const struct boot_mode soc_boot_modes[] = {
 166         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 167         /* usb or serial download */
 168         {"usb",         MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
 169         {"sata",        MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
 170         {"escpi1:0",    MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
 171         {"escpi1:1",    MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
 172         {"escpi1:2",    MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
 173         {"escpi1:3",    MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
 174         /* 4 bit bus width */
 175         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
 176         {"esdhc2",      MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
 177         {"esdhc3",      MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
 178         {"esdhc4",      MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
 179         {NULL,          0},
 180 };
 181 #endif