arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_ARM,        /* PLL1: ARM PLL */
  18         PLL_528,        /* PLL2: System Bus PLL*/
  19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
  20         PLL_AUDIO,      /* PLL4: Audio PLL */
  21         PLL_VIDEO,      /* PLL5: Video PLL */
  22         PLL_ENET,       /* PLL6: ENET PLL */
  23         PLL_USB2,       /* PLL7: USB2 PLL */
  24         PLL_MLB,        /* PLL8: MLB PLL */
  25 };
  26
  27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
  28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
  29
  30 int clk_enable(struct clk *clk)
  31 {
  32         int ret = 0;
  33
  34         if (!clk)
  35                 return 0;
  36         if (clk->usecount == 0) {
  37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
  38                 ret = clk->enable(clk);
  39                 if (ret)
  40                         return ret;
  41                 clk->usecount++;
  42         }
  43         assert(clk->usecount > 0);
  44         return ret;
  45 }
  46
  47 void clk_disable(struct clk *clk)
  48 {
  49         if (!clk)
  50                 return;
  51
  52         assert(clk->usecount > 0);
  53         if (!(--clk->usecount)) {
  54                 if (clk->disable) {
  55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
  56                         clk->disable(clk);
  57                 }
  58         }
  59 }
  60
  61 int clk_get_usecount(struct clk *clk)
  62 {
  63         if (clk == NULL)
  64                 return 0;
  65
  66         return clk->usecount;
  67 }
  68
  69 u32 clk_get_rate(struct clk *clk)
  70 {
  71         if (!clk)
  72                 return 0;
  73
  74         return clk->rate;
  75 }
  76
  77 struct clk *clk_get_parent(struct clk *clk)
  78 {
  79         if (!clk)
  80                 return 0;
  81
  82         return clk->parent;
  83 }
  84
  85 int clk_set_rate(struct clk *clk, unsigned long rate)
  86 {
  87         if (clk && clk->set_rate)
  88                 clk->set_rate(clk, rate);
  89         return clk->rate;
  90 }
  91
  92 long clk_round_rate(struct clk *clk, unsigned long rate)
  93 {
  94         if (clk == NULL || !clk->round_rate)
  95                 return 0;
  96
  97         return clk->round_rate(clk, rate);
  98 }
  99
 100 int clk_set_parent(struct clk *clk, struct clk *parent)
 101 {
 102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
 103                 clk ? clk->parent : NULL);
 104
 105         if (!clk || clk == parent)
 106                 return 0;
 107
 108         if (clk->set_parent) {
 109                 int ret;
 110
 111                 ret = clk->set_parent(clk, parent);
 112                 if (ret)
 113                         return ret;
 114         }
 115         clk->parent = parent;
 116         return 0;
 117 }
 118
 119 #define PLL_LOCK_BIT            (1 << 31)
 120
 121 static inline int wait_pll_lock(u32 *reg)
 122 {
 123         int loops = 0;
 124         u32 val;
 125
 126         while (!((val = readl(reg)) & PLL_LOCK_BIT)) {
 127                 loops++;
 128                 if (loops > 1000)
 129                         break;
 130                 udelay(1);
 131         }
 132         if (!(val & PLL_LOCK_BIT) && !(readl(reg) & PLL_LOCK_BIT))
 133                 return -ETIMEDOUT;
 134         return 0;
 135 }
 136
 137 #ifdef CONFIG_MXC_OCOTP
 138 void enable_ocotp_clk(unsigned char enable)
 139 {
 140         u32 reg;
 141
 142         reg = __raw_readl(&imx_ccm->CCGR2);
 143         if (enable)
 144                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 145         else
 146                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 147         __raw_writel(reg, &imx_ccm->CCGR2);
 148 }
 149 #endif
 150
 151 #ifdef CONFIG_NAND_MXS
 152 void setup_gpmi_io_clk(u32 cfg)
 153 {
 154         /* Disable clocks per ERR007177 from MX6 errata */
 155         clrbits_le32(&imx_ccm->CCGR4,
 156                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 158                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 159                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 160                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 161
 162         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 163
 164         clrsetbits_le32(&imx_ccm->cs2cdr,
 165                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 166                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 167                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 168                         cfg);
 169
 170         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 171         setbits_le32(&imx_ccm->CCGR4,
 172                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 173                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 174                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 175                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 176                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 177 }
 178 #endif
 179
 180 void enable_usboh3_clk(unsigned char enable)
 181 {
 182         u32 reg;
 183
 184         reg = __raw_readl(&imx_ccm->CCGR6);
 185         if (enable)
 186                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
 187         else
 188                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
 189         __raw_writel(reg, &imx_ccm->CCGR6);
 190
 191 }
 192
 193 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 194 void enable_enet_clk(unsigned char enable)
 195 {
 196         u32 mask, *addr;
 197
 198         if (is_cpu_type(MXC_CPU_MX6UL)) {
 199                 mask = MXC_CCM_CCGR3_ENET_MASK;
 200                 addr = &imx_ccm->CCGR3;
 201         } else {
 202                 mask = MXC_CCM_CCGR1_ENET_MASK;
 203                 addr = &imx_ccm->CCGR1;
 204         }
 205
 206         if (enable)
 207                 setbits_le32(addr, mask);
 208         else
 209                 clrbits_le32(addr, mask);
 210 }
 211 #endif
 212
 213 #ifdef CONFIG_MXC_UART
 214 void enable_uart_clk(unsigned char enable)
 215 {
 216         u32 mask;
 217
 218         if (is_cpu_type(MXC_CPU_MX6UL))
 219                 mask = MXC_CCM_CCGR5_UART_MASK;
 220         else
 221                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 222
 223         if (enable)
 224                 setbits_le32(&imx_ccm->CCGR5, mask);
 225         else
 226                 clrbits_le32(&imx_ccm->CCGR5, mask);
 227 }
 228 #endif
 229
 230 #ifdef CONFIG_MMC
 231 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 232 {
 233         u32 mask;
 234
 235         if (bus_num > 3)
 236                 return -EINVAL;
 237
 238         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 239         if (enable)
 240                 setbits_le32(&imx_ccm->CCGR6, mask);
 241         else
 242                 clrbits_le32(&imx_ccm->CCGR6, mask);
 243
 244         return 0;
 245 }
 246 #endif
 247
 248 #ifdef CONFIG_SYS_I2C_MXC
 249 /* i2c_num can be from 0 - 3 */
 250 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 251 {
 252         u32 reg;
 253         u32 mask;
 254         u32 *addr;
 255
 256         if (i2c_num > 3)
 257                 return -EINVAL;
 258         if (i2c_num < 3) {
 259                 mask = MXC_CCM_CCGR_CG_MASK
 260                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 261                         + (i2c_num << 1));
 262                 reg = __raw_readl(&imx_ccm->CCGR2);
 263                 if (enable)
 264                         reg |= mask;
 265                 else
 266                         reg &= ~mask;
 267                 __raw_writel(reg, &imx_ccm->CCGR2);
 268         } else {
 269                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 270                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 271                         addr = &imx_ccm->CCGR6;
 272                 } else {
 273                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 274                         addr = &imx_ccm->CCGR1;
 275                 }
 276                 reg = __raw_readl(addr);
 277                 if (enable)
 278                         reg |= mask;
 279                 else
 280                         reg &= ~mask;
 281                 __raw_writel(reg, addr);
 282         }
 283         return 0;
 284 }
 285 #endif
 286
 287 /* spi_num can be from 0 - SPI_MAX_NUM */
 288 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 289 {
 290         u32 reg;
 291         u32 mask;
 292
 293         if (spi_num > SPI_MAX_NUM)
 294                 return -EINVAL;
 295
 296         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 297         reg = __raw_readl(&imx_ccm->CCGR1);
 298         if (enable)
 299                 reg |= mask;
 300         else
 301                 reg &= ~mask;
 302         __raw_writel(reg, &imx_ccm->CCGR1);
 303         return 0;
 304 }
 305
 306 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 307 {
 308         u32 div, post_div;
 309
 310         switch (pll) {
 311         case PLL_ARM:
 312                 div = __raw_readl(&anatop->pll_arm);
 313                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
 314                         /* Assume the bypass clock is always derived from OSC */
 315                         return infreq;
 316                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
 317
 318                 return infreq * div / 2;
 319         case PLL_528:
 320                 div = __raw_readl(&anatop->pll_528);
 321                 if (div & BM_ANADIG_PLL_528_BYPASS)
 322                         return infreq;
 323                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 324
 325                 return infreq * (20 + div * 2);
 326         case PLL_USBOTG:
 327                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
 328                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 329                         return infreq;
 330                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 331
 332                 return infreq * (20 + div * 2);
 333         case PLL_AUDIO:
 334                 div = __raw_readl(&anatop->pll_audio);
 335                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 336                         return infreq;
 337                 post_div = (div & BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT) >>
 338                         BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT;
 339                 post_div = 1 << (2 - post_div);
 340                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 341
 342                 return lldiv((u64)infreq * div, post_div);
 343         case PLL_VIDEO:
 344                 div = __raw_readl(&anatop->pll_video);
 345                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 346                         return infreq;
 347                 post_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
 348                         BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 349                 post_div = 1 << (2 - post_div);
 350                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 351
 352                 return lldiv((u64)infreq * div, post_div);
 353         case PLL_ENET:
 354                 div = __raw_readl(&anatop->pll_enet);
 355                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
 356                         return infreq;
 357                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 358
 359                 return 25000000 * (div + (div >> 1) + 1);
 360         case PLL_USB2:
 361                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
 362                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 363                         return infreq;
 364                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 365
 366                 return infreq * (20 + div * 2);
 367         case PLL_MLB:
 368                 div = __raw_readl(&anatop->pll_mlb);
 369                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
 370                         return infreq;
 371                 /* unknown external clock provided on MLB_CLK pin */
 372                 return 0;
 373         }
 374         return 0;
 375 }
 376
 377 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 378 {
 379         u32 div;
 380         u64 freq;
 381
 382         switch (pll) {
 383         case PLL_528:
 384                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
 385                         if (pfd_num == 3) {
 386                                 /* No PFD3 on PPL2 */
 387                                 return 0;
 388                         }
 389                 }
 390                 div = __raw_readl(&anatop->pfd_528);
 391                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
 392                 break;
 393         case PLL_USBOTG:
 394                 div = __raw_readl(&anatop->pfd_480);
 395                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 396                 break;
 397         default:
 398                 /* No PFD on other PLL */
 399                 return 0;
 400         }
 401
 402         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 403                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 404 }
 405
 406 static u32 get_mcu_main_clk(void)
 407 {
 408         u32 reg, freq;
 409
 410         reg = __raw_readl(&imx_ccm->cacrr);
 411         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 412         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 413         freq = decode_pll(PLL_ARM, MXC_HCLK);
 414
 415         return freq / (reg + 1);
 416 }
 417
 418 u32 get_periph_clk(void)
 419 {
 420         u32 reg, div = 0, freq = 0;
 421
 422         reg = __raw_readl(&imx_ccm->cbcdr);
 423         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 424                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 425                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 426                 reg = __raw_readl(&imx_ccm->cbcmr);
 427                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 428                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 429
 430                 switch (reg) {
 431                 case 0:
 432                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 433                         break;
 434                 case 1:
 435                 case 2:
 436                         freq = MXC_HCLK;
 437                         break;
 438                 }
 439         } else {
 440                 reg = __raw_readl(&imx_ccm->cbcmr);
 441                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 442                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 443
 444                 switch (reg) {
 445                 case 0:
 446                         freq = decode_pll(PLL_528, MXC_HCLK);
 447                         break;
 448                 case 1:
 449                         freq = mxc_get_pll_pfd(PLL_528, 2);
 450                         break;
 451                 case 2:
 452                         freq = mxc_get_pll_pfd(PLL_528, 0);
 453                         break;
 454                 case 3:
 455                         /* static / 2 divider */
 456                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
 457                         break;
 458                 }
 459         }
 460
 461         return freq / (div + 1);
 462 }
 463
 464 static u32 get_ipg_clk(void)
 465 {
 466         u32 reg, ipg_podf;
 467
 468         reg = __raw_readl(&imx_ccm->cbcdr);
 469         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 470         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 471
 472         return get_ahb_clk() / (ipg_podf + 1);
 473 }
 474
 475 static u32 get_ipg_per_clk(void)
 476 {
 477         u32 reg, perclk_podf;
 478
 479         reg = __raw_readl(&imx_ccm->cscmr1);
 480         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 481             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 482                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 483                         return MXC_HCLK; /* OSC 24Mhz */
 484         }
 485
 486         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 487
 488         return get_ipg_clk() / (perclk_podf + 1);
 489 }
 490
 491 static u32 get_uart_clk(void)
 492 {
 493         u32 reg, uart_podf;
 494         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 495         reg = __raw_readl(&imx_ccm->cscdr1);
 496
 497         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 498             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 499                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 500                         freq = MXC_HCLK;
 501         }
 502
 503         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 504         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 505
 506         return freq / (uart_podf + 1);
 507 }
 508
 509 static u32 get_cspi_clk(void)
 510 {
 511         u32 reg, cspi_podf;
 512
 513         reg = __raw_readl(&imx_ccm->cscdr2);
 514         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 515                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 516
 517         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
 518             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 519                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 520                         return MXC_HCLK / (cspi_podf + 1);
 521         }
 522
 523         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 524 }
 525
 526 static u32 get_axi_clk(void)
 527 {
 528         u32 root_freq, axi_podf;
 529         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 530
 531         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 532         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 533
 534         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 535                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 536                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 537                 else
 538                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 539         } else {
 540                 root_freq = get_periph_clk();
 541         }
 542         return  root_freq / (axi_podf + 1);
 543 }
 544
 545 static u32 get_emi_slow_clk(void)
 546 {
 547         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 548
 549         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 550         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 551         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 552         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 553         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 554
 555         switch (emi_clk_sel) {
 556         case 0:
 557                 root_freq = get_axi_clk();
 558                 break;
 559         case 1:
 560                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 561                 break;
 562         case 2:
 563                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
 564                 break;
 565         case 3:
 566                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
 567                 break;
 568         }
 569
 570         return root_freq / (emi_slow_podf + 1);
 571 }
 572
 573 static u32 get_nfc_clk(void)
 574 {
 575         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 576         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
 577                 MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 578         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
 579                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 580         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
 581                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 582         u32 root_freq;
 583
 584         switch (nfc_clk_sel) {
 585         case 0:
 586                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 587                 break;
 588         case 1:
 589                 root_freq = decode_pll(PLL_528, MXC_HCLK);
 590                 break;
 591         case 2:
 592                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 593                 break;
 594         case 3:
 595                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 596                 break;
 597         case 4:
 598                 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
 599                 break;
 600         default:
 601                 return 0;
 602         }
 603
 604         return root_freq / (pred + 1) / (podf + 1);
 605 }
 606
 607 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
 608                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
 609                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
 610
 611 static int set_nfc_clk(u32 ref, u32 freq_khz)
 612 {
 613         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 614         u32 podf;
 615         u32 pred;
 616         int nfc_clk_sel;
 617         u32 root_freq;
 618         u32 min_err = ~0;
 619         u32 nfc_val = ~0;
 620         u32 freq = freq_khz * 1000;
 621
 622         for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
 623                 u32 act_freq;
 624                 u32 err;
 625
 626                 if (ref < 4 && ref != nfc_clk_sel)
 627                         continue;
 628
 629                 switch (nfc_clk_sel) {
 630                 case 0:
 631                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
 632                         break;
 633                 case 1:
 634                         root_freq = decode_pll(PLL_528, MXC_HCLK);
 635                         break;
 636                 case 2:
 637                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 638                         break;
 639                 case 3:
 640                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 641                         break;
 642                 }
 643                 if (root_freq < freq)
 644                         continue;
 645
 646                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
 647                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
 648                 act_freq = root_freq / pred / podf;
 649                 err = (freq - act_freq) * 100 / freq;
 650                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
 651                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
 652                 if (act_freq > freq)
 653                         continue;
 654                 if (err < min_err) {
 655                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 656                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 657                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 658                         min_err = err;
 659                         if (err == 0)
 660                                 break;
 661                 }
 662         }
 663
 664         if (nfc_val == ~0 || min_err > 10)
 665                 return -EINVAL;
 666
 667         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
 668                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
 669                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
 670                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
 671                         &imx_ccm->cs2cdr);
 672         } else {
 673                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
 674         }
 675         return 0;
 676 }
 677
 678 static u32 get_mmdc_ch0_clk(void)
 679 {
 680         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 681         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 682
 683         u32 freq, podf, per2_clk2_podf;
 684
 685         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
 686             is_cpu_type(MXC_CPU_MX6SL)) {
 687                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 688                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 689                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 690                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 691                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 692                         if (is_cpu_type(MXC_CPU_MX6SL)) {
 693                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 694                                         freq = MXC_HCLK;
 695                                 else
 696                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 697                         } else {
 698                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 699                                         freq = decode_pll(PLL_528, MXC_HCLK);
 700                                 else
 701                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 702                         }
 703                 } else {
 704                         per2_clk2_podf = 0;
 705                         switch ((cbcmr &
 706                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 707                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 708                         case 0:
 709                                 freq = decode_pll(PLL_528, MXC_HCLK);
 710                                 break;
 711                         case 1:
 712                                 freq = mxc_get_pll_pfd(PLL_528, 2);
 713                                 break;
 714                         case 2:
 715                                 freq = mxc_get_pll_pfd(PLL_528, 0);
 716                                 break;
 717                         case 3:
 718                                 /* static / 2 divider */
 719                                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
 720                                 break;
 721                         }
 722                 }
 723                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 724         } else {
 725                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 726                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 727                 return get_periph_clk() / (podf + 1);
 728         }
 729 }
 730
 731 #ifdef CONFIG_FSL_QSPI
 732 /* qspi_num can be from 0 - 1 */
 733 void enable_qspi_clk(int qspi_num)
 734 {
 735         u32 reg = 0;
 736         /* Enable QuadSPI clock */
 737         switch (qspi_num) {
 738         case 0:
 739                 /* disable the clock gate */
 740                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 741
 742                 /* set 50M  : (50 = 396 / 2 / 4) */
 743                 reg = readl(&imx_ccm->cscmr1);
 744                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 745                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 746                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 747                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 748                 writel(reg, &imx_ccm->cscmr1);
 749
 750                 /* enable the clock gate */
 751                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 752                 break;
 753         case 1:
 754                 /*
 755                  * disable the clock gate
 756                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 757                  * disable both of them.
 758                  */
 759                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 760                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 761
 762                 /* set 50M  : (50 = 396 / 2 / 4) */
 763                 reg = readl(&imx_ccm->cs2cdr);
 764                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 765                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 766                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 767                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 768                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 769                 writel(reg, &imx_ccm->cs2cdr);
 770
 771                 /*enable the clock gate*/
 772                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 773                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 774                 break;
 775         default:
 776                 break;
 777         }
 778 }
 779 #endif
 780
 781 #ifdef CONFIG_FEC_MXC
 782 int enable_fec_anatop_clock(enum enet_freq freq)
 783 {
 784         u32 reg = 0;
 785         s32 timeout = 100000;
 786
 787         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 788                 return -EINVAL;
 789
 790         reg = readl(&anatop->pll_enet);
 791         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 792         reg |= freq;
 793
 794         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 795             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 796                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 797                 writel(reg, &anatop->pll_enet);
 798                 while (timeout--) {
 799                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 800                                 break;
 801                 }
 802                 if (timeout < 0)
 803                         return -ETIMEDOUT;
 804         }
 805
 806         /* Enable FEC clock */
 807         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 808         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 809         writel(reg, &anatop->pll_enet);
 810
 811 #ifdef CONFIG_SOC_MX6SX
 812         /*
 813          * Set enet ahb clock to 200MHz
 814          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 815          */
 816         reg = readl(&imx_ccm->chsccdr);
 817         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 818                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 819                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 820         /* PLL2 PFD2 */
 821         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 822         /* Div = 2*/
 823         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 824         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 825         writel(reg, &imx_ccm->chsccdr);
 826
 827         /* Enable enet system clock */
 828         reg = readl(&imx_ccm->CCGR3);
 829         reg |= MXC_CCM_CCGR3_ENET_MASK;
 830         writel(reg, &imx_ccm->CCGR3);
 831 #endif
 832         return 0;
 833 }
 834 #endif
 835
 836 static u32 get_usdhc_clk(u32 port)
 837 {
 838         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 839         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 840         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 841
 842         switch (port) {
 843         case 0:
 844                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 845                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 846                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 847
 848                 break;
 849         case 1:
 850                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 851                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 852                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 853
 854                 break;
 855         case 2:
 856                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 857                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 858                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 859
 860                 break;
 861         case 3:
 862                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 863                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 864                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 865
 866                 break;
 867         default:
 868                 break;
 869         }
 870
 871         if (clk_sel)
 872                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 873         else
 874                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 875
 876         return root_freq / (usdhc_podf + 1);
 877 }
 878
 879 u32 imx_get_uartclk(void)
 880 {
 881         return get_uart_clk();
 882 }
 883
 884 u32 imx_get_fecclk(void)
 885 {
 886         return mxc_get_clock(MXC_IPG_CLK);
 887 }
 888
 889 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 890 static int enable_enet_pll(uint32_t en)
 891 {
 892         u32 reg;
 893         s32 timeout = 100000;
 894
 895         /* Enable PLLs */
 896         reg = readl(&anatop->pll_enet);
 897         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 898         writel(reg, &anatop->pll_enet);
 899         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 900         while (timeout--) {
 901                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 902                         break;
 903         }
 904         if (timeout <= 0)
 905                 return -EIO;
 906         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 907         writel(reg, &anatop->pll_enet);
 908         reg |= en;
 909         writel(reg, &anatop->pll_enet);
 910         return 0;
 911 }
 912 #endif
 913
 914 #ifdef CONFIG_CMD_SATA
 915 static void ungate_sata_clock(void)
 916 {
 917         /* Enable SATA clock. */
 918         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 919 }
 920
 921 int enable_sata_clock(void)
 922 {
 923         ungate_sata_clock();
 924         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 925 }
 926
 927 void disable_sata_clock(void)
 928 {
 929         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 930 }
 931 #endif
 932
 933 #ifdef CONFIG_PCIE_IMX
 934 static void ungate_pcie_clock(void)
 935 {
 936         /* Enable PCIe clock. */
 937         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 938 }
 939
 940 int enable_pcie_clock(void)
 941 {
 942         u32 lvds1_clk_sel;
 943
 944         /*
 945          * Here be dragons!
 946          *
 947          * The register ANATOP_MISC1 is not documented in the Freescale
 948          * MX6RM. The register that is mapped in the ANATOP space and
 949          * marked as ANATOP_MISC1 is actually documented in the PMU section
 950          * of the datasheet as PMU_MISC1.
 951          *
 952          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 953          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 954          * for PCI express link that is clocked from the i.MX6.
 955          */
 956 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
 957 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
 958 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
 959 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
 960 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
 961
 962         if (is_cpu_type(MXC_CPU_MX6SX))
 963                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 964         else
 965                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
 966
 967         clrsetbits_le32(&anatop_regs->ana_misc1,
 968                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 969                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 970                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 971
 972         /* PCIe reference clock sourced from AXI. */
 973         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 974
 975         /* Party time! Ungate the clock to the PCIe. */
 976 #ifdef CONFIG_CMD_SATA
 977         ungate_sata_clock();
 978 #endif
 979         ungate_pcie_clock();
 980
 981         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
 982                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 983 }
 984 #endif
 985
 986 #ifdef CONFIG_SECURE_BOOT
 987 void hab_caam_clock_enable(unsigned char enable)
 988 {
 989         u32 reg;
 990
 991         /* CG4 ~ CG6, CAAM clocks */
 992         reg = __raw_readl(&imx_ccm->CCGR0);
 993         if (enable)
 994                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 995                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 996                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 997         else
 998                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 999                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1000                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1001         __raw_writel(reg, &imx_ccm->CCGR0);
1002
1003         /* EMI slow clk */
1004         reg = __raw_readl(&imx_ccm->CCGR6);
1005         if (enable)
1006                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1007         else
1008                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1009         __raw_writel(reg, &imx_ccm->CCGR6);
1010 }
1011 #endif
1012
1013 static void enable_pll3(void)
1014 {
1015         /* make sure pll3 is enabled */
1016         if ((readl(&anatop->usb1_pll_480_ctrl) &
1017                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1018                 /* enable pll's power */
1019                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1020                        &anatop->usb1_pll_480_ctrl_set);
1021                 writel(0x80, &anatop->ana_misc2_clr);
1022                 /* wait for pll lock */
1023                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1024                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1025                         ;
1026                 /* disable bypass */
1027                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1028                        &anatop->usb1_pll_480_ctrl_clr);
1029                 /* enable pll output */
1030                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1031                        &anatop->usb1_pll_480_ctrl_set);
1032         }
1033 }
1034
1035 void enable_thermal_clk(void)
1036 {
1037         enable_pll3();
1038 }
1039
1040 void ipu_clk_enable(void)
1041 {
1042         u32 reg = readl(&imx_ccm->CCGR3);
1043         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1044         writel(reg, &imx_ccm->CCGR3);
1045 }
1046
1047 void ipu_clk_disable(void)
1048 {
1049         u32 reg = readl(&imx_ccm->CCGR3);
1050         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1051         writel(reg, &imx_ccm->CCGR3);
1052 }
1053
1054 void ipu_di_clk_enable(int di)
1055 {
1056         switch (di) {
1057         case 0:
1058                 setbits_le32(&imx_ccm->CCGR3,
1059                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1060                 break;
1061         case 1:
1062                 setbits_le32(&imx_ccm->CCGR3,
1063                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1064                 break;
1065         default:
1066                 printf("%s: Invalid DI index %d\n", __func__, di);
1067         }
1068 }
1069
1070 void ipu_di_clk_disable(int di)
1071 {
1072         switch (di) {
1073         case 0:
1074                 clrbits_le32(&imx_ccm->CCGR3,
1075                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1076                 break;
1077         case 1:
1078                 clrbits_le32(&imx_ccm->CCGR3,
1079                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1080                 break;
1081         default:
1082                 printf("%s: Invalid DI index %d\n", __func__, di);
1083         }
1084 }
1085
1086 void ldb_clk_enable(int ldb)
1087 {
1088         switch (ldb) {
1089         case 0:
1090                 setbits_le32(&imx_ccm->CCGR3,
1091                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1092                 break;
1093         case 1:
1094                 setbits_le32(&imx_ccm->CCGR3,
1095                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1096                 break;
1097         default:
1098                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1099         }
1100 }
1101
1102 void ldb_clk_disable(int ldb)
1103 {
1104         switch (ldb) {
1105         case 0:
1106                 clrbits_le32(&imx_ccm->CCGR3,
1107                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1108                 break;
1109         case 1:
1110                 clrbits_le32(&imx_ccm->CCGR3,
1111                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1112                 break;
1113         default:
1114                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1115         }
1116 }
1117
1118 #ifdef CONFIG_VIDEO_MXS
1119 void lcdif_clk_enable(void)
1120 {
1121         setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1122         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1123 }
1124
1125 void lcdif_clk_disable(void)
1126 {
1127         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1128         clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1129 }
1130
1131 #define CBCMR_LCDIF_MASK        MXC_CCM_CBCMR_LCDIF_PODF_MASK
1132 #define CSCDR2_LCDIF_MASK       (MXC_CCM_CSCDR2_LCDIF_PRED_MASK |       \
1133                                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK)
1134
1135 static u32 get_lcdif_root_clk(u32 cscdr2)
1136 {
1137         int lcdif_pre_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) >>
1138                 MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET;
1139         int lcdif_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK) >>
1140                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET;
1141         u32 root_freq;
1142
1143         switch (lcdif_clk_sel) {
1144         case 0:
1145                 switch (lcdif_pre_clk_sel) {
1146                 case 0:
1147                         root_freq = decode_pll(PLL_528, MXC_HCLK);
1148                         break;
1149                 case 1:
1150                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
1151                         break;
1152                 case 2:
1153                         root_freq = decode_pll(PLL_VIDEO, MXC_HCLK);
1154                         break;
1155                 case 3:
1156                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
1157                         break;
1158                 case 4:
1159                         root_freq = mxc_get_pll_pfd(PLL_528, 1);
1160                         break;
1161                 case 5:
1162                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
1163                         break;
1164                 default:
1165                         return 0;
1166                 }
1167                 break;
1168         case 1:
1169                 root_freq = mxc_get_pll_pfd(PLL_VIDEO, 0);
1170                 break;
1171         case 2:
1172                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1173                 break;
1174         case 3:
1175                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
1176                 break;
1177         default:
1178                 return 0;
1179         }
1180
1181         return root_freq;
1182 }
1183
1184 static int set_lcdif_pll(u32 ref, u32 freq_khz,
1185                         unsigned post_div)
1186 {
1187         int ret;
1188         u64 freq = freq_khz * 1000;
1189         u32 post_div_mask = 1 << (2 - post_div);
1190         int mul = 1;
1191         u32 min_err = ~0;
1192         u32 reg;
1193         int num = 0;
1194         int denom = 1;
1195         const int min_div = 27;
1196         const int max_div = 54;
1197         const int div_mask = 0x7f;
1198         const u32 max_freq = ref * max_div / post_div;
1199         const u32 min_freq = ref * min_div / post_div;
1200
1201         if (freq > max_freq || freq < min_freq) {
1202                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03uMHz\n",
1203                         freq_khz / 1000, freq_khz % 1000,
1204                         min_freq / 1000000, min_freq / 1000 % 1000,
1205                         max_freq / 1000000, max_freq / 1000 % 1000);
1206                 return -EINVAL;
1207         }
1208         {
1209                 int d = post_div;
1210                 int m = lldiv(freq * d + ref - 1, ref);
1211                 u32 err;
1212                 u32 f;
1213
1214                 debug("%s@%d: d=%d m=%d max_div=%u min_div=%u\n", __func__, __LINE__,
1215                         d, m, max_div, min_div);
1216                 if (m > max_div || m < min_div)
1217                         return -EINVAL;
1218
1219                 f = ref * m / d;
1220                 if (f > freq) {
1221                         debug("%s@%d: d=%d m=%d f=%u freq=%llu\n", __func__, __LINE__,
1222                                 d, m, f, freq);
1223                         return -EINVAL;
1224                 }
1225                 err = freq - f;
1226                 debug("%s@%d: d=%d m=%d f=%u freq=%llu err=%d\n", __func__, __LINE__,
1227                         d, m, f, freq, err);
1228                 if (err < min_err) {
1229                         mul = m;
1230                         min_err = err;
1231                 }
1232         }
1233         if (min_err == ~0) {
1234                 printf("Cannot set VIDEO PLL to %u.%03uMHz\n",
1235                         freq_khz / 1000, freq_khz % 1000);
1236                 return -EINVAL;
1237         }
1238
1239         debug("Setting M=%3u D=%u N=%d DE=%u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1240                 mul, post_div, num, denom,
1241                 freq_khz / post_div / 1000, freq_khz / post_div % 1000,
1242                 ref * mul / post_div / 1000000,
1243                 ref * mul / post_div / 1000 % 1000);
1244
1245         reg = readl(&anatop->pll_video);
1246         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1247
1248         reg = (reg & ~(div_mask |
1249                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)) |
1250                 mul | (post_div_mask << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT);
1251         writel(reg, &anatop->pll_video);
1252
1253         ret = wait_pll_lock(&anatop->pll_video);
1254         if (ret) {
1255                 printf("Video PLL failed to lock\n");
1256                 return ret;
1257         }
1258
1259         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1260         return 0;
1261 }
1262
1263 static int set_lcdif_clk(u32 ref, u32 freq_khz)
1264 {
1265         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1266         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1267         u32 cbcmr_val;
1268         u32 cscdr2_val;
1269         u32 freq = freq_khz * 1000;
1270         u32 act_freq;
1271         u32 err;
1272         u32 min_div = 27;
1273         u32 max_div = 54;
1274         u32 min_pll_khz = ref * min_div / 4 / 1000;
1275         u32 max_pll_khz = ref * max_div / 1000;
1276         u32 pll_khz;
1277         u32 post_div = 0;
1278         u32 m;
1279         u32 min_err = ~0;
1280         u32 best_m = 0;
1281         u32 best_pred = 1;
1282         u32 best_podf = 1;
1283         u32 div;
1284         unsigned pd;
1285
1286         if (freq_khz > max_pll_khz)
1287                 return -EINVAL;
1288
1289         for (pd = 1; min_err && pd <= 4; pd <<= 1) {
1290                 for (m = max(min_div, DIV_ROUND_UP(648000 / pd, freq_khz * 64));
1291                      m <= max_div; m++) {
1292                         u32 err;
1293                         int pred = 0;
1294                         int podf = 0;
1295                         u32 root_freq = ref * m / pd;
1296
1297                         div = DIV_ROUND_UP(root_freq, freq);
1298
1299                         while (pred * podf == 0 && div <= 64) {
1300                                 int p1, p2;
1301
1302                                 for (p1 = 1; p1 <= 8; p1++) {
1303                                         for (p2 = 1; p2 <= 8; p2++) {
1304                                                 if (p1 * p2 == div) {
1305                                                         podf = p1;
1306                                                         pred = p2;
1307                                                         break;
1308                                                 }
1309                                         }
1310                                 }
1311                                 if (pred * podf == 0) {
1312                                         div++;
1313                                 }
1314                         }
1315                         if (pred * podf == 0)
1316                                 continue;
1317
1318                         /* relative error in per mille */
1319                         act_freq = root_freq / div;
1320                         err = abs(act_freq - freq) / freq_khz;
1321
1322                         if (err < min_err) {
1323                                 best_m = m;
1324                                 best_pred = pred;
1325                                 best_podf = podf;
1326                                 post_div = pd;
1327                                 min_err = err;
1328                                 if (err <= 10)
1329                                         break;
1330                         }
1331                 }
1332         }
1333         if (min_err > 50)
1334                 return -EINVAL;
1335
1336         pll_khz = ref / 1000 * best_m;
1337         if (pll_khz > max_pll_khz)
1338                 return -EINVAL;
1339
1340         if (pll_khz < min_pll_khz)
1341                 return -EINVAL;
1342
1343         err = set_lcdif_pll(ref, pll_khz / post_div, post_div);
1344         if (err)
1345                 return err;
1346
1347         cbcmr_val = (best_podf - 1) << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET;
1348         cscdr2_val = (best_pred - 1) << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET;
1349
1350         if ((cbcmr & CBCMR_LCDIF_MASK) != cbcmr_val) {
1351                 debug("changing cbcmr from %08x to %08x\n", cbcmr,
1352                         (cbcmr & ~CBCMR_LCDIF_MASK) | cbcmr_val);
1353                 clrsetbits_le32(&imx_ccm->cbcmr,
1354                                 CBCMR_LCDIF_MASK,
1355                                 cbcmr_val);
1356         } else {
1357                 debug("Leaving cbcmr unchanged [%08x]\n", cbcmr);
1358         }
1359         if ((cscdr2 & CSCDR2_LCDIF_MASK) != cscdr2_val) {
1360                 debug("changing cscdr2 from %08x to %08x\n", cscdr2,
1361                         (cscdr2 & ~CSCDR2_LCDIF_MASK) | cscdr2_val);
1362                 clrsetbits_le32(&imx_ccm->cscdr2,
1363                                 CSCDR2_LCDIF_MASK,
1364                                 cscdr2_val);
1365         } else {
1366                 debug("Leaving cscdr2 unchanged [%08x]\n", cscdr2);
1367         }
1368         return 0;
1369 }
1370
1371 void mxs_set_lcdclk(u32 khz)
1372 {
1373         set_lcdif_clk(CONFIG_SYS_MX6_HCLK, khz);
1374 }
1375
1376 static u32 get_lcdif_clk(void)
1377 {
1378         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1379         u32 podf = ((cbcmr & MXC_CCM_CBCMR_LCDIF_PODF_MASK) >>
1380                 MXC_CCM_CBCMR_LCDIF_PODF_OFFSET) + 1;
1381         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1382         u32 pred = ((cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRED_MASK) >>
1383                 MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET) + 1;
1384         u32 root_freq = get_lcdif_root_clk(cscdr2);
1385
1386         return root_freq / pred / podf;
1387 }
1388 #endif
1389
1390 unsigned int mxc_get_clock(enum mxc_clock clk)
1391 {
1392         switch (clk) {
1393         case MXC_ARM_CLK:
1394                 return get_mcu_main_clk();
1395         case MXC_PER_CLK:
1396                 return get_periph_clk();
1397         case MXC_AHB_CLK:
1398                 return get_ahb_clk();
1399         case MXC_IPG_CLK:
1400                 return get_ipg_clk();
1401         case MXC_IPG_PERCLK:
1402         case MXC_I2C_CLK:
1403                 return get_ipg_per_clk();
1404         case MXC_UART_CLK:
1405                 return get_uart_clk();
1406         case MXC_CSPI_CLK:
1407                 return get_cspi_clk();
1408         case MXC_AXI_CLK:
1409                 return get_axi_clk();
1410         case MXC_EMI_SLOW_CLK:
1411                 return get_emi_slow_clk();
1412         case MXC_DDR_CLK:
1413                 return get_mmdc_ch0_clk();
1414         case MXC_ESDHC_CLK:
1415                 return get_usdhc_clk(0);
1416         case MXC_ESDHC2_CLK:
1417                 return get_usdhc_clk(1);
1418         case MXC_ESDHC3_CLK:
1419                 return get_usdhc_clk(2);
1420         case MXC_ESDHC4_CLK:
1421                 return get_usdhc_clk(3);
1422         case MXC_SATA_CLK:
1423                 return get_ahb_clk();
1424         case MXC_NFC_CLK:
1425                 return get_nfc_clk();
1426 #ifdef CONFIG_VIDEO_MXS
1427         case MXC_LCDIF_CLK:
1428                 return get_lcdif_clk();
1429 #endif
1430         default:
1431                 printf("Unsupported MXC CLK: %d\n", clk);
1432         }
1433
1434         return 0;
1435 }
1436
1437 /* Config CPU clock */
1438 static int set_arm_clk(u32 ref, u32 freq_khz)
1439 {
1440         int ret;
1441         int d;
1442         int div = 0;
1443         int mul = 0;
1444         u32 min_err = ~0;
1445         u32 reg;
1446         const int min_div = 54;
1447         const int max_div = 108;
1448         const int div_mask = 0x7f;
1449         const u32 max_freq = ref * max_div / 2;
1450         const u32 min_freq = ref * min_div / 8 / 2;
1451
1452         if (freq_khz > max_freq / 1000 || freq_khz < min_freq / 1000) {
1453                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1454                         freq_khz / 1000, freq_khz % 1000,
1455                         min_freq / 1000000, min_freq / 1000 % 1000,
1456                         max_freq / 1000000, max_freq / 1000 % 1000);
1457                 return -EINVAL;
1458         }
1459
1460         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1461                 int m = freq_khz * 2 * d / (ref / 1000);
1462                 u32 f;
1463                 u32 err;
1464
1465                 if (m > max_div) {
1466                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1467                                 d, m);
1468                         break;
1469                 }
1470
1471                 f = ref * m / d / 2;
1472                 if (f > freq_khz * 1000) {
1473                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1474                                 d, m, f, freq_khz);
1475                         if (--m < min_div)
1476                                 return -EINVAL;
1477                         f = ref * m / d / 2;
1478                 }
1479                 err = freq_khz * 1000 - f;
1480                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1481                         d, m, f, freq_khz, err);
1482                 if (err < min_err) {
1483                         mul = m;
1484                         div = d;
1485                         min_err = err;
1486                         if (err == 0)
1487                                 break;
1488                 }
1489         }
1490         if (min_err == ~0)
1491                 return -EINVAL;
1492         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1493                 mul, div, freq_khz / 1000, freq_khz % 1000,
1494                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1495
1496         reg = readl(&anatop->pll_arm);
1497         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1498
1499         reg = (reg & ~div_mask) | mul;
1500         writel(reg, &anatop->pll_arm);
1501
1502         writel(div - 1, &imx_ccm->cacrr);
1503
1504         ret = wait_pll_lock(&anatop->pll_video);
1505         if (ret) {
1506                 printf("ARM PLL failed to lock\n");
1507                 return ret;
1508         }
1509
1510         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1511
1512         return 0;
1513 }
1514
1515 /*
1516  * This function assumes the expected core clock has to be changed by
1517  * modifying the PLL. This is NOT true always but for most of the times,
1518  * it is. So it assumes the PLL output freq is the same as the expected
1519  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1520  * In the latter case, it will try to increase the presc value until
1521  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1522  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1523  * on the targeted PLL and reference input clock to the PLL. Lastly,
1524  * it sets the register based on these values along with the dividers.
1525  * Note 1) There is no value checking for the passed-in divider values
1526  *         so the caller has to make sure those values are sensible.
1527  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1528  *         exceed NFC_CLK_MAX.
1529  */
1530 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1531 {
1532         int ret;
1533
1534         freq *= 1000;
1535
1536         switch (clk) {
1537         case MXC_ARM_CLK:
1538                 ret = set_arm_clk(ref, freq);
1539                 break;
1540
1541         case MXC_NFC_CLK:
1542                 ret = set_nfc_clk(ref, freq);
1543                 break;
1544
1545         default:
1546                 printf("Warning: Unsupported or invalid clock type: %d\n",
1547                         clk);
1548                 return -EINVAL;
1549         }
1550
1551         return ret;
1552 }
1553
1554 /*
1555  * Dump some core clocks.
1556  */
1557 #define print_pll(pll)  {                               \
1558         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1559         printf("%-12s %4d.%03d MHz\n", #pll,            \
1560                 __pll / 1000000, __pll / 1000 % 1000);  \
1561         }
1562
1563 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1564
1565 #define print_clk(clk)  {                               \
1566         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1567         printf("%-12s %4d.%03d MHz\n", #clk,            \
1568                 __clk / 1000000, __clk / 1000 % 1000);  \
1569         }
1570
1571 #define print_pfd(pll, pfd)     {                                       \
1572         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1573         if (__pfd & (0x80 << 8 * pfd)) {                                \
1574                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1575         } else {                                                        \
1576                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1577                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1578                         pll * 18 / __pfd,                               \
1579                         pll * 18 * 1000 / __pfd % 1000);                \
1580         }                                                               \
1581 }
1582
1583 static void do_mx6_showclocks(void)
1584 {
1585         print_pll(PLL_ARM);
1586         print_pll(PLL_528);
1587         print_pll(PLL_USBOTG);
1588         print_pll(PLL_AUDIO);
1589         print_pll(PLL_VIDEO);
1590         print_pll(PLL_ENET);
1591         print_pll(PLL_USB2);
1592         printf("\n");
1593
1594         print_pfd(480, 0);
1595         print_pfd(480, 1);
1596         print_pfd(480, 2);
1597         print_pfd(480, 3);
1598         print_pfd(528, 0);
1599         print_pfd(528, 1);
1600         print_pfd(528, 2);
1601         printf("\n");
1602
1603         print_clk(IPG);
1604         print_clk(UART);
1605         print_clk(CSPI);
1606         print_clk(AHB);
1607         print_clk(AXI);
1608         print_clk(DDR);
1609         print_clk(ESDHC);
1610         print_clk(ESDHC2);
1611         print_clk(ESDHC3);
1612         print_clk(ESDHC4);
1613         print_clk(EMI_SLOW);
1614         print_clk(NFC);
1615         print_clk(IPG_PER);
1616         print_clk(ARM);
1617 #ifdef CONFIG_VIDEO_MXS
1618         print_clk(LCDIF);
1619 #endif
1620 }
1621
1622 static struct clk_lookup {
1623         const char *name;
1624         unsigned int index;
1625 } mx6_clk_lookup[] = {
1626         { "arm", MXC_ARM_CLK, },
1627         { "nfc", MXC_NFC_CLK, },
1628 };
1629
1630 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1631 {
1632         int i;
1633         unsigned long freq;
1634         unsigned long ref = ~0UL;
1635
1636         if (argc < 2) {
1637                 do_mx6_showclocks();
1638                 return CMD_RET_SUCCESS;
1639         } else if (argc == 2 || argc > 4) {
1640                 return CMD_RET_USAGE;
1641         }
1642
1643         freq = simple_strtoul(argv[2], NULL, 0);
1644         if (freq == 0) {
1645                 printf("Invalid clock frequency %lu\n", freq);
1646                 return CMD_RET_FAILURE;
1647         }
1648         if (argc > 3) {
1649                 ref = simple_strtoul(argv[3], NULL, 0);
1650         }
1651         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1652                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1653                         switch (mx6_clk_lookup[i].index) {
1654                         case MXC_ARM_CLK:
1655                                 if (argc > 3)
1656                                         return CMD_RET_USAGE;
1657                                 ref = MXC_HCLK;
1658                                 break;
1659
1660                         case MXC_NFC_CLK:
1661                                 if (argc > 3 && ref > 3) {
1662                                         printf("Invalid clock selector value: %lu\n", ref);
1663                                         return CMD_RET_FAILURE;
1664                                 }
1665                                 break;
1666                         }
1667                         printf("Setting %s clock to %lu MHz\n",
1668                                 mx6_clk_lookup[i].name, freq);
1669                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1670                                 break;
1671                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1672                         printf("%s clock set to %lu.%03lu MHz\n",
1673                                 mx6_clk_lookup[i].name,
1674                                 freq / 1000000, freq / 1000 % 1000);
1675                         return CMD_RET_SUCCESS;
1676                 }
1677         }
1678         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1679                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1680                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1681                         printf("\t%s\n", mx6_clk_lookup[i].name);
1682                 }
1683         } else {
1684                 printf("Failed to set clock %s to %s MHz\n",
1685                         argv[1], argv[2]);
1686         }
1687         return CMD_RET_FAILURE;
1688 }
1689
1690 #ifndef CONFIG_SOC_MX6SX
1691 void enable_ipu_clock(void)
1692 {
1693         int reg = readl(&imx_ccm->CCGR3);
1694         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1695         writel(reg, &imx_ccm->CCGR3);
1696
1697         if (is_mx6dqp()) {
1698                 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1699                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1700         }
1701 }
1702 #endif
1703 /***************************************************/
1704
1705 U_BOOT_CMD(
1706         clocks, 4, 0, do_clocks,
1707         "display/set clocks",
1708         "                    - display clock settings\n"
1709         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1710 );