arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_ARM,        /* PLL1: ARM PLL */
  18         PLL_528,        /* PLL2: System Bus PLL*/
  19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
  20         PLL_AUDIO,      /* PLL4: Audio PLL */
  21         PLL_VIDEO,      /* PLL5: Video PLL */
  22         PLL_ENET,       /* PLL6: ENET PLL */
  23         PLL_USB2,       /* PLL7: USB2 PLL */
  24         PLL_MLB,        /* PLL8: MLB PLL */
  25 };
  26
  27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
  28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
  29
  30 int clk_enable(struct clk *clk)
  31 {
  32         int ret = 0;
  33
  34         if (!clk)
  35                 return 0;
  36         if (clk->usecount == 0) {
  37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
  38                 ret = clk->enable(clk);
  39                 if (ret)
  40                         return ret;
  41                 clk->usecount++;
  42         }
  43         assert(clk->usecount > 0);
  44         return ret;
  45 }
  46
  47 void clk_disable(struct clk *clk)
  48 {
  49         if (!clk)
  50                 return;
  51
  52         assert(clk->usecount > 0);
  53         if (!(--clk->usecount)) {
  54                 if (clk->disable) {
  55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
  56                         clk->disable(clk);
  57                 }
  58         }
  59 }
  60
  61 int clk_get_usecount(struct clk *clk)
  62 {
  63         if (clk == NULL)
  64                 return 0;
  65
  66         return clk->usecount;
  67 }
  68
  69 u32 clk_get_rate(struct clk *clk)
  70 {
  71         if (!clk)
  72                 return 0;
  73
  74         return clk->rate;
  75 }
  76
  77 struct clk *clk_get_parent(struct clk *clk)
  78 {
  79         if (!clk)
  80                 return 0;
  81
  82         return clk->parent;
  83 }
  84
  85 int clk_set_rate(struct clk *clk, unsigned long rate)
  86 {
  87         if (clk && clk->set_rate)
  88                 clk->set_rate(clk, rate);
  89         return clk->rate;
  90 }
  91
  92 long clk_round_rate(struct clk *clk, unsigned long rate)
  93 {
  94         if (clk == NULL || !clk->round_rate)
  95                 return 0;
  96
  97         return clk->round_rate(clk, rate);
  98 }
  99
 100 int clk_set_parent(struct clk *clk, struct clk *parent)
 101 {
 102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
 103                 clk ? clk->parent : NULL);
 104
 105         if (!clk || clk == parent)
 106                 return 0;
 107
 108         if (clk->set_parent) {
 109                 int ret;
 110
 111                 ret = clk->set_parent(clk, parent);
 112                 if (ret)
 113                         return ret;
 114         }
 115         clk->parent = parent;
 116         return 0;
 117 }
 118
 119 #ifdef CONFIG_MXC_OCOTP
 120 void enable_ocotp_clk(unsigned char enable)
 121 {
 122         u32 reg;
 123
 124         reg = __raw_readl(&imx_ccm->CCGR2);
 125         if (enable)
 126                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 127         else
 128                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 129         __raw_writel(reg, &imx_ccm->CCGR2);
 130 }
 131 #endif
 132
 133 #ifdef CONFIG_NAND_MXS
 134 void setup_gpmi_io_clk(u32 cfg)
 135 {
 136         /* Disable clocks per ERR007177 from MX6 errata */
 137         clrbits_le32(&imx_ccm->CCGR4,
 138                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 139                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 140                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 141                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 142                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 143
 144         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 145
 146         clrsetbits_le32(&imx_ccm->cs2cdr,
 147                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 148                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 149                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 150                         cfg);
 151
 152         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 153         setbits_le32(&imx_ccm->CCGR4,
 154                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 155                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 156                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 158                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 159 }
 160 #endif
 161
 162 void enable_usboh3_clk(unsigned char enable)
 163 {
 164         u32 reg;
 165
 166         reg = __raw_readl(&imx_ccm->CCGR6);
 167         if (enable)
 168                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
 169         else
 170                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
 171         __raw_writel(reg, &imx_ccm->CCGR6);
 172
 173 }
 174
 175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 176 void enable_enet_clk(unsigned char enable)
 177 {
 178         u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
 179
 180         if (enable)
 181                 setbits_le32(&imx_ccm->CCGR1, mask);
 182         else
 183                 clrbits_le32(&imx_ccm->CCGR1, mask);
 184 }
 185 #endif
 186
 187 #ifdef CONFIG_MXC_UART
 188 void enable_uart_clk(unsigned char enable)
 189 {
 190         u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 191
 192         if (enable)
 193                 setbits_le32(&imx_ccm->CCGR5, mask);
 194         else
 195                 clrbits_le32(&imx_ccm->CCGR5, mask);
 196 }
 197 #endif
 198
 199 #ifdef CONFIG_MMC
 200 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 201 {
 202         u32 mask;
 203
 204         if (bus_num > 3)
 205                 return -EINVAL;
 206
 207         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 208         if (enable)
 209                 setbits_le32(&imx_ccm->CCGR6, mask);
 210         else
 211                 clrbits_le32(&imx_ccm->CCGR6, mask);
 212
 213         return 0;
 214 }
 215 #endif
 216
 217 #ifdef CONFIG_SYS_I2C_MXC
 218 /* i2c_num can be from 0 - 3 */
 219 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 220 {
 221         u32 reg;
 222         u32 mask;
 223
 224         if (i2c_num > 3)
 225                 return -EINVAL;
 226         if (i2c_num < 3) {
 227                 mask = MXC_CCM_CCGR_CG_MASK
 228                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 229                         + (i2c_num << 1));
 230                 reg = __raw_readl(&imx_ccm->CCGR2);
 231                 if (enable)
 232                         reg |= mask;
 233                 else
 234                         reg &= ~mask;
 235                 __raw_writel(reg, &imx_ccm->CCGR2);
 236         } else {
 237                 mask = MXC_CCM_CCGR_CG_MASK
 238                         << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
 239                 reg = __raw_readl(&imx_ccm->CCGR1);
 240                 if (enable)
 241                         reg |= mask;
 242                 else
 243                         reg &= ~mask;
 244                 __raw_writel(reg, &imx_ccm->CCGR1);
 245         }
 246         return 0;
 247 }
 248 #endif
 249
 250 /* spi_num can be from 0 - SPI_MAX_NUM */
 251 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 252 {
 253         u32 reg;
 254         u32 mask;
 255
 256         if (spi_num > SPI_MAX_NUM)
 257                 return -EINVAL;
 258
 259         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 260         reg = __raw_readl(&imx_ccm->CCGR1);
 261         if (enable)
 262                 reg |= mask;
 263         else
 264                 reg &= ~mask;
 265         __raw_writel(reg, &imx_ccm->CCGR1);
 266         return 0;
 267 }
 268 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 269 {
 270         u32 div;
 271
 272         switch (pll) {
 273         case PLL_ARM:
 274                 div = __raw_readl(&anatop->pll_arm);
 275                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
 276                         /* Assume the bypass clock is always derived from OSC */
 277                         return infreq;
 278                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
 279
 280                 return infreq * div / 2;
 281         case PLL_528:
 282                 div = __raw_readl(&anatop->pll_528);
 283                 if (div & BM_ANADIG_PLL_528_BYPASS)
 284                         return infreq;
 285                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 286
 287                 return infreq * (20 + div * 2);
 288         case PLL_USBOTG:
 289                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
 290                 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
 291                         return infreq;
 292                 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
 293
 294                 return infreq * (20 + div * 2);
 295         case PLL_AUDIO:
 296                 div = __raw_readl(&anatop->pll_audio);
 297                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 298                         return infreq;
 299                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 300
 301                 return infreq * div;
 302         case PLL_VIDEO:
 303                 div = __raw_readl(&anatop->pll_video);
 304                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 305                         return infreq;
 306                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 307
 308                 return infreq * div;
 309         case PLL_ENET:
 310                 div = __raw_readl(&anatop->pll_enet);
 311                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
 312                         return infreq;
 313                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 314
 315                 return 25000000 * (div + (div >> 1) + 1);
 316         case PLL_USB2:
 317                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
 318                 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
 319                         return infreq;
 320                 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
 321
 322                 return infreq * (20 + div * 2);
 323         case PLL_MLB:
 324                 div = __raw_readl(&anatop->pll_mlb);
 325                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
 326                         return infreq;
 327                 /* unknown external clock provided on MLB_CLK pin */
 328                 return 0;
 329         }
 330         return 0;
 331 }
 332 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 333 {
 334         u32 div;
 335         u64 freq;
 336         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 337
 338         switch (pll) {
 339         case PLL_528:
 340                 if (pfd_num == 3) {
 341                         /* No PFD3 on PLL2 */
 342                         return 0;
 343                 }
 344                 div = __raw_readl(&anatop->pfd_528);
 345                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
 346                 break;
 347         case PLL_USBOTG:
 348                 div = __raw_readl(&anatop->pfd_480);
 349                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 350                 break;
 351         default:
 352                 /* No PFD on other PLL */
 353                 return 0;
 354         }
 355
 356         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 357                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 358 }
 359
 360 static u32 get_mcu_main_clk(void)
 361 {
 362         u32 reg, freq;
 363
 364         reg = __raw_readl(&imx_ccm->cacrr);
 365         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 366         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 367         freq = decode_pll(PLL_ARM, MXC_HCLK);
 368
 369         return freq / (reg + 1);
 370 }
 371
 372 u32 get_periph_clk(void)
 373 {
 374         u32 reg, freq = 0;
 375
 376         reg = __raw_readl(&imx_ccm->cbcdr);
 377         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 378                 reg = __raw_readl(&imx_ccm->cbcmr);
 379                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 380                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 381
 382                 switch (reg) {
 383                 case 0:
 384                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 385                         break;
 386                 case 1:
 387                 case 2:
 388                         freq = MXC_HCLK;
 389                         break;
 390                 }
 391         } else {
 392                 reg = __raw_readl(&imx_ccm->cbcmr);
 393                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 394                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 395
 396                 switch (reg) {
 397                 case 0:
 398                         freq = decode_pll(PLL_528, MXC_HCLK);
 399                         break;
 400                 case 1:
 401                         freq = mxc_get_pll_pfd(PLL_528, 2);
 402                         break;
 403                 case 2:
 404                         freq = mxc_get_pll_pfd(PLL_528, 0);
 405                         break;
 406                 case 3:
 407                         /* static / 2 divider */
 408                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
 409                         break;
 410                 }
 411         }
 412
 413         return freq;
 414 }
 415
 416 static u32 get_ipg_clk(void)
 417 {
 418         u32 reg, ipg_podf;
 419
 420         reg = __raw_readl(&imx_ccm->cbcdr);
 421         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 422         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 423
 424         return get_ahb_clk() / (ipg_podf + 1);
 425 }
 426
 427 static u32 get_ipg_per_clk(void)
 428 {
 429         u32 reg, perclk_podf;
 430
 431         reg = __raw_readl(&imx_ccm->cscmr1);
 432 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 433         if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 434                 return MXC_HCLK; /* OSC 24Mhz */
 435 #endif
 436         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 437
 438         return get_ipg_clk() / (perclk_podf + 1);
 439 }
 440
 441 static u32 get_uart_clk(void)
 442 {
 443         u32 reg, uart_podf;
 444         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 445         reg = __raw_readl(&imx_ccm->cscdr1);
 446 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 447         if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 448                 freq = MXC_HCLK;
 449 #endif
 450         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 451         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 452
 453         return freq / (uart_podf + 1);
 454 }
 455
 456 static u32 get_cspi_clk(void)
 457 {
 458         u32 reg, cspi_podf;
 459
 460         reg = __raw_readl(&imx_ccm->cscdr2);
 461         reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
 462         cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 463
 464         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 465 }
 466
 467 static u32 get_axi_clk(void)
 468 {
 469         u32 root_freq, axi_podf;
 470         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 471
 472         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 473         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 474
 475         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 476                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 477                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 478                 else
 479                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 480         } else
 481                 root_freq = get_periph_clk();
 482
 483         return  root_freq / (axi_podf + 1);
 484 }
 485
 486 static u32 get_emi_slow_clk(void)
 487 {
 488         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 489
 490         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 491         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 492         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 493         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 494         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 495
 496         switch (emi_clk_sel) {
 497         case 0:
 498                 root_freq = get_axi_clk();
 499                 break;
 500         case 1:
 501                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 502                 break;
 503         case 2:
 504                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
 505                 break;
 506         case 3:
 507                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
 508                 break;
 509         }
 510
 511         return root_freq / (emi_slow_podf + 1);
 512 }
 513
 514 static u32 get_nfc_clk(void)
 515 {
 516         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 517         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 518         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 519         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
 520                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 521         u32 root_freq;
 522
 523         switch (nfc_clk_sel) {
 524         case 0:
 525                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 526                 break;
 527         case 1:
 528                 root_freq = decode_pll(PLL_528, MXC_HCLK);
 529                 break;
 530         case 2:
 531                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 532                 break;
 533         case 3:
 534                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 535                 break;
 536         }
 537
 538         return root_freq / (pred + 1) / (podf + 1);
 539 }
 540
 541 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
 542                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
 543                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
 544
 545 static int set_nfc_clk(u32 ref, u32 freq_khz)
 546 {
 547         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 548         u32 podf;
 549         u32 pred;
 550         int nfc_clk_sel;
 551         u32 root_freq;
 552         u32 min_err = ~0;
 553         u32 nfc_val = ~0;
 554         u32 freq = freq_khz * 1000;
 555
 556         for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
 557                 u32 act_freq;
 558                 u32 err;
 559
 560                 if (ref < 4 && ref != nfc_clk_sel)
 561                         continue;
 562
 563                 switch (nfc_clk_sel) {
 564                 case 0:
 565                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
 566                         break;
 567                 case 1:
 568                         root_freq = decode_pll(PLL_528, MXC_HCLK);
 569                         break;
 570                 case 2:
 571                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 572                         break;
 573                 case 3:
 574                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 575                         break;
 576                 }
 577                 if (root_freq < freq)
 578                         continue;
 579
 580                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
 581                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
 582                 act_freq = root_freq / pred / podf;
 583                 err = (freq - act_freq) * 100 / freq;
 584                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
 585                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
 586                 if (act_freq > freq)
 587                         continue;
 588                 if (err < min_err) {
 589                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 590                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 591                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 592                         min_err = err;
 593                         if (err == 0)
 594                                 break;
 595                 }
 596         }
 597
 598         if (nfc_val == ~0 || min_err > 10)
 599                 return -EINVAL;
 600
 601         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
 602                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
 603                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
 604                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
 605                         &imx_ccm->cs2cdr);
 606         } else {
 607                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
 608         }
 609         return 0;
 610 }
 611
 612 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 613 static u32 get_mmdc_ch0_clk(void)
 614 {
 615         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 616         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 617         u32 freq, podf;
 618
 619         podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
 620                         >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 621
 622         switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 623                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 624         case 0:
 625                 freq = decode_pll(PLL_528, MXC_HCLK);
 626                 break;
 627         case 1:
 628                 freq = mxc_get_pll_pfd(PLL_528, 2);
 629                 break;
 630         case 2:
 631                 freq = mxc_get_pll_pfd(PLL_528, 0);
 632                 break;
 633         case 3:
 634                 /* static / 2 divider */
 635                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
 636         }
 637
 638         return freq / (podf + 1);
 639
 640 }
 641 #else
 642 static u32 get_mmdc_ch0_clk(void)
 643 {
 644         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 645         u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 646                                 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 647
 648         return get_periph_clk() / (mmdc_ch0_podf + 1);
 649 }
 650 #endif
 651
 652 #ifdef CONFIG_SOC_MX6SX
 653 /* qspi_num can be from 0 - 1 */
 654 void enable_qspi_clk(int qspi_num)
 655 {
 656         u32 reg = 0;
 657         /* Enable QuadSPI clock */
 658         switch (qspi_num) {
 659         case 0:
 660                 /* disable the clock gate */
 661                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 662
 663                 /* set 50M  : (50 = 396 / 2 / 4) */
 664                 reg = readl(&imx_ccm->cscmr1);
 665                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 666                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 667                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 668                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 669                 writel(reg, &imx_ccm->cscmr1);
 670
 671                 /* enable the clock gate */
 672                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 673                 break;
 674         case 1:
 675                 /*
 676                  * disable the clock gate
 677                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 678                  * disable both of them.
 679                  */
 680                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 681                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 682
 683                 /* set 50M  : (50 = 396 / 2 / 4) */
 684                 reg = readl(&imx_ccm->cs2cdr);
 685                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 686                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 687                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 688                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 689                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 690                 writel(reg, &imx_ccm->cs2cdr);
 691
 692                 /*enable the clock gate*/
 693                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 694                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 695                 break;
 696         default:
 697                 break;
 698         }
 699 }
 700 #endif
 701
 702 #ifdef CONFIG_FEC_MXC
 703 int enable_fec_anatop_clock(enum enet_freq freq)
 704 {
 705         u32 reg = 0;
 706         s32 timeout = 100000;
 707
 708         struct anatop_regs __iomem *anatop =
 709                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 710
 711         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 712                 return -EINVAL;
 713
 714         reg = readl(&anatop->pll_enet);
 715         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 716         reg |= freq;
 717
 718         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 719             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 720                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 721                 writel(reg, &anatop->pll_enet);
 722                 while (timeout--) {
 723                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 724                                 break;
 725                 }
 726                 if (timeout < 0)
 727                         return -ETIMEDOUT;
 728         }
 729
 730         /* Enable FEC clock */
 731         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 732         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 733         writel(reg, &anatop->pll_enet);
 734
 735 #ifdef CONFIG_SOC_MX6SX
 736         /*
 737          * Set enet ahb clock to 200MHz
 738          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 739          */
 740         reg = readl(&imx_ccm->chsccdr);
 741         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 742                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 743                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 744         /* PLL2 PFD2 */
 745         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 746         /* Div = 2*/
 747         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 748         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 749         writel(reg, &imx_ccm->chsccdr);
 750
 751         /* Enable enet system clock */
 752         reg = readl(&imx_ccm->CCGR3);
 753         reg |= MXC_CCM_CCGR3_ENET_MASK;
 754         writel(reg, &imx_ccm->CCGR3);
 755 #endif
 756         return 0;
 757 }
 758 #endif
 759
 760 static u32 get_usdhc_clk(u32 port)
 761 {
 762         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 763         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 764         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 765
 766         switch (port) {
 767         case 0:
 768                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 769                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 770                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 771
 772                 break;
 773         case 1:
 774                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 775                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 776                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 777
 778                 break;
 779         case 2:
 780                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 781                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 782                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 783
 784                 break;
 785         case 3:
 786                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 787                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 788                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 789
 790                 break;
 791         default:
 792                 break;
 793         }
 794
 795         if (clk_sel)
 796                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 797         else
 798                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 799
 800         return root_freq / (usdhc_podf + 1);
 801 }
 802
 803 u32 imx_get_uartclk(void)
 804 {
 805         return get_uart_clk();
 806 }
 807
 808 u32 imx_get_fecclk(void)
 809 {
 810         return mxc_get_clock(MXC_IPG_CLK);
 811 }
 812
 813 static int enable_enet_pll(uint32_t en)
 814 {
 815         u32 reg;
 816         s32 timeout = 100000;
 817
 818         /* Enable PLLs */
 819         reg = readl(&anatop->pll_enet);
 820         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 821         writel(reg, &anatop->pll_enet);
 822         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 823         while (timeout--) {
 824                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 825                         break;
 826         }
 827         if (timeout <= 0)
 828                 return -EIO;
 829         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 830         writel(reg, &anatop->pll_enet);
 831         reg |= en;
 832         writel(reg, &anatop->pll_enet);
 833         return 0;
 834 }
 835
 836 #ifndef CONFIG_SOC_MX6SX
 837 static void ungate_sata_clock(void)
 838 {
 839         struct mxc_ccm_reg *const imx_ccm =
 840                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 841
 842         /* Enable SATA clock. */
 843         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 844 }
 845 #endif
 846
 847 static void ungate_pcie_clock(void)
 848 {
 849         struct mxc_ccm_reg *const imx_ccm =
 850                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 851
 852         /* Enable PCIe clock. */
 853         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 854 }
 855
 856 #ifndef CONFIG_SOC_MX6SX
 857 int enable_sata_clock(void)
 858 {
 859         ungate_sata_clock();
 860         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 861 }
 862
 863 void disable_sata_clock(void)
 864 {
 865         struct mxc_ccm_reg *const imx_ccm =
 866                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 867
 868         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 869 }
 870 #endif
 871
 872 int enable_pcie_clock(void)
 873 {
 874         struct anatop_regs *anatop_regs =
 875                 (struct anatop_regs *)ANATOP_BASE_ADDR;
 876         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 877         u32 lvds1_clk_sel;
 878
 879         /*
 880          * Here be dragons!
 881          *
 882          * The register ANATOP_MISC1 is not documented in the Freescale
 883          * MX6RM. The register that is mapped in the ANATOP space and
 884          * marked as ANATOP_MISC1 is actually documented in the PMU section
 885          * of the datasheet as PMU_MISC1.
 886          *
 887          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 888          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 889          * for PCI express link that is clocked from the i.MX6.
 890          */
 891 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
 892 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
 893 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
 894 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
 895 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
 896
 897         if (is_cpu_type(MXC_CPU_MX6SX))
 898                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 899         else
 900                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
 901
 902         clrsetbits_le32(&anatop_regs->ana_misc1,
 903                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 904                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 905                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 906
 907         /* PCIe reference clock sourced from AXI. */
 908         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 909
 910         /* Party time! Ungate the clock to the PCIe. */
 911 #ifndef CONFIG_SOC_MX6SX
 912         ungate_sata_clock();
 913 #endif
 914         ungate_pcie_clock();
 915
 916         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
 917                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 918 }
 919
 920 #ifdef CONFIG_SECURE_BOOT
 921 void hab_caam_clock_enable(unsigned char enable)
 922 {
 923         u32 reg;
 924
 925         /* CG4 ~ CG6, CAAM clocks */
 926         reg = __raw_readl(&imx_ccm->CCGR0);
 927         if (enable)
 928                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 929                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 930                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 931         else
 932                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 933                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 934                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 935         __raw_writel(reg, &imx_ccm->CCGR0);
 936
 937         /* EMI slow clk */
 938         reg = __raw_readl(&imx_ccm->CCGR6);
 939         if (enable)
 940                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
 941         else
 942                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
 943         __raw_writel(reg, &imx_ccm->CCGR6);
 944 }
 945 #endif
 946
 947 static void enable_pll3(void)
 948 {
 949         struct anatop_regs __iomem *anatop =
 950                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 951
 952         /* make sure pll3 is enabled */
 953         if ((readl(&anatop->usb1_pll_480_ctrl) &
 954                         BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
 955                 /* enable pll's power */
 956                 writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
 957                        &anatop->usb1_pll_480_ctrl_set);
 958                 writel(0x80, &anatop->ana_misc2_clr);
 959                 /* wait for pll lock */
 960                 while ((readl(&anatop->usb1_pll_480_ctrl) &
 961                         BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
 962                         ;
 963                 /* disable bypass */
 964                 writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
 965                        &anatop->usb1_pll_480_ctrl_clr);
 966                 /* enable pll output */
 967                 writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
 968                        &anatop->usb1_pll_480_ctrl_set);
 969         }
 970 }
 971
 972 void enable_thermal_clk(void)
 973 {
 974         enable_pll3();
 975 }
 976
 977 void ipu_clk_enable(void)
 978 {
 979         u32 reg = readl(&imx_ccm->CCGR3);
 980         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 981         writel(reg, &imx_ccm->CCGR3);
 982 }
 983
 984 void ipu_clk_disable(void)
 985 {
 986         u32 reg = readl(&imx_ccm->CCGR3);
 987         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
 988         writel(reg, &imx_ccm->CCGR3);
 989 }
 990
 991 void ipu_di_clk_enable(int di)
 992 {
 993         switch (di) {
 994         case 0:
 995                 setbits_le32(&imx_ccm->CCGR3,
 996                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
 997                 break;
 998         case 1:
 999                 setbits_le32(&imx_ccm->CCGR3,
1000                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1001                 break;
1002         default:
1003                 printf("%s: Invalid DI index %d\n", __func__, di);
1004         }
1005 }
1006
1007 void ipu_di_clk_disable(int di)
1008 {
1009         switch (di) {
1010         case 0:
1011                 clrbits_le32(&imx_ccm->CCGR3,
1012                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1013                 break;
1014         case 1:
1015                 clrbits_le32(&imx_ccm->CCGR3,
1016                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1017                 break;
1018         default:
1019                 printf("%s: Invalid DI index %d\n", __func__, di);
1020         }
1021 }
1022
1023 void ldb_clk_enable(int ldb)
1024 {
1025         switch (ldb) {
1026         case 0:
1027                 setbits_le32(&imx_ccm->CCGR3,
1028                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1029                 break;
1030         case 1:
1031                 setbits_le32(&imx_ccm->CCGR3,
1032                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1033                 break;
1034         default:
1035                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1036         }
1037 }
1038
1039 void ldb_clk_disable(int ldb)
1040 {
1041         switch (ldb) {
1042         case 0:
1043                 clrbits_le32(&imx_ccm->CCGR3,
1044                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1045                 break;
1046         case 1:
1047                 clrbits_le32(&imx_ccm->CCGR3,
1048                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1049                 break;
1050         default:
1051                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1052         }
1053 }
1054
1055 void ocotp_clk_enable(void)
1056 {
1057         u32 reg = readl(&imx_ccm->CCGR2);
1058         reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1059         writel(reg, &imx_ccm->CCGR2);
1060 }
1061
1062 void ocotp_clk_disable(void)
1063 {
1064         u32 reg = readl(&imx_ccm->CCGR2);
1065         reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1066         writel(reg, &imx_ccm->CCGR2);
1067 }
1068
1069 unsigned int mxc_get_clock(enum mxc_clock clk)
1070 {
1071         switch (clk) {
1072         case MXC_ARM_CLK:
1073                 return get_mcu_main_clk();
1074         case MXC_PER_CLK:
1075                 return get_periph_clk();
1076         case MXC_AHB_CLK:
1077                 return get_ahb_clk();
1078         case MXC_IPG_CLK:
1079                 return get_ipg_clk();
1080         case MXC_IPG_PERCLK:
1081         case MXC_I2C_CLK:
1082                 return get_ipg_per_clk();
1083         case MXC_UART_CLK:
1084                 return get_uart_clk();
1085         case MXC_CSPI_CLK:
1086                 return get_cspi_clk();
1087         case MXC_AXI_CLK:
1088                 return get_axi_clk();
1089         case MXC_EMI_SLOW_CLK:
1090                 return get_emi_slow_clk();
1091         case MXC_DDR_CLK:
1092                 return get_mmdc_ch0_clk();
1093         case MXC_ESDHC_CLK:
1094                 return get_usdhc_clk(0);
1095         case MXC_ESDHC2_CLK:
1096                 return get_usdhc_clk(1);
1097         case MXC_ESDHC3_CLK:
1098                 return get_usdhc_clk(2);
1099         case MXC_ESDHC4_CLK:
1100                 return get_usdhc_clk(3);
1101         case MXC_SATA_CLK:
1102                 return get_ahb_clk();
1103         case MXC_NFC_CLK:
1104                 return get_nfc_clk();
1105         default:
1106                 printf("Unsupported MXC CLK: %d\n", clk);
1107         }
1108
1109         return 0;
1110 }
1111
1112 static inline int gcd(int m, int n)
1113 {
1114         int t;
1115         while (m > 0) {
1116                 if (n > m) {
1117                         t = m;
1118                         m = n;
1119                         n = t;
1120                 } /* swap */
1121                 m -= n;
1122         }
1123         return n;
1124 }
1125
1126 /* Config CPU clock */
1127 static int set_arm_clk(u32 ref, u32 freq_khz)
1128 {
1129         int d;
1130         int div = 0;
1131         int mul = 0;
1132         u32 min_err = ~0;
1133         u32 reg;
1134
1135         if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1136                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1137                         freq_khz / 1000, freq_khz % 1000,
1138                         54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1139                         108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1140                 return -EINVAL;
1141         }
1142
1143         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1144                 int m = freq_khz * 2 * d / (ref / 1000);
1145                 u32 f;
1146                 u32 err;
1147
1148                 if (m > 108) {
1149                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1150                                 d, m);
1151                         break;
1152                 }
1153
1154                 f = ref * m / d / 2;
1155                 if (f > freq_khz * 1000) {
1156                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1157                                 d, m, f, freq_khz);
1158                         if (--m < 54)
1159                                 return -EINVAL;
1160                         f = ref * m / d / 2;
1161                 }
1162                 err = freq_khz * 1000 - f;
1163                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1164                         d, m, f, freq_khz, err);
1165                 if (err < min_err) {
1166                         mul = m;
1167                         div = d;
1168                         min_err = err;
1169                         if (err == 0)
1170                                 break;
1171                 }
1172         }
1173         if (min_err == ~0)
1174                 return -EINVAL;
1175         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1176                 mul, div, freq_khz / 1000, freq_khz % 1000,
1177                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1178
1179         reg = readl(&anatop->pll_arm);
1180         debug("anadig_pll_arm=%08x -> %08x\n",
1181                 reg, (reg & ~0x7f) | mul);
1182
1183         reg |= 1 << 16;
1184         writel(reg, &anatop->pll_arm); /* bypass PLL */
1185
1186         reg = (reg & ~0x7f) | mul;
1187         writel(reg, &anatop->pll_arm);
1188
1189         writel(div - 1, &imx_ccm->cacrr);
1190
1191         reg &= ~(1 << 16);
1192         writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1193
1194         return 0;
1195 }
1196
1197 /*
1198  * This function assumes the expected core clock has to be changed by
1199  * modifying the PLL. This is NOT true always but for most of the times,
1200  * it is. So it assumes the PLL output freq is the same as the expected
1201  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1202  * In the latter case, it will try to increase the presc value until
1203  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1204  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1205  * on the targeted PLL and reference input clock to the PLL. Lastly,
1206  * it sets the register based on these values along with the dividers.
1207  * Note 1) There is no value checking for the passed-in divider values
1208  *         so the caller has to make sure those values are sensible.
1209  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1210  *         exceed NFC_CLK_MAX.
1211  *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
1212  *         177MHz for higher voltage, this function fixes the max to 133MHz.
1213  *      4) This function should not have allowed diag_printf() calls since
1214  *         the serial driver has been stoped. But leave then here to allow
1215  *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1216  */
1217 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1218 {
1219         int ret;
1220
1221         freq *= 1000;
1222
1223         switch (clk) {
1224         case MXC_ARM_CLK:
1225                 ret = set_arm_clk(ref, freq);
1226                 break;
1227
1228         case MXC_NFC_CLK:
1229                 ret = set_nfc_clk(ref, freq);
1230                 break;
1231
1232         default:
1233                 printf("Warning: Unsupported or invalid clock type: %d\n",
1234                         clk);
1235                 return -EINVAL;
1236         }
1237
1238         return ret;
1239 }
1240
1241 /*
1242  * Dump some core clocks.
1243  */
1244 #define print_pll(pll)  {                               \
1245         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1246         printf("%-12s %4d.%03d MHz\n", #pll,            \
1247                 __pll / 1000000, __pll / 1000 % 1000);  \
1248         }
1249
1250 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1251
1252 #define print_clk(clk)  {                               \
1253         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1254         printf("%-12s %4d.%03d MHz\n", #clk,            \
1255                 __clk / 1000000, __clk / 1000 % 1000);  \
1256         }
1257
1258 #define print_pfd(pll, pfd)     {                                       \
1259         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1260         if (__pfd & (0x80 << 8 * pfd)) {                                \
1261                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1262         } else {                                                        \
1263                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1264                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1265                         pll * 18 / __pfd,                               \
1266                         pll * 18 * 1000 / __pfd % 1000);                \
1267         }                                                               \
1268 }
1269
1270 static void do_mx6_showclocks(void)
1271 {
1272         print_pll(PLL_ARM);
1273         print_pll(PLL_528);
1274         print_pll(PLL_USBOTG);
1275         print_pll(PLL_AUDIO);
1276         print_pll(PLL_VIDEO);
1277         print_pll(PLL_ENET);
1278         print_pll(PLL_USB2);
1279         printf("\n");
1280
1281         print_pfd(480, 0);
1282         print_pfd(480, 1);
1283         print_pfd(480, 2);
1284         print_pfd(480, 3);
1285         print_pfd(528, 0);
1286         print_pfd(528, 1);
1287         print_pfd(528, 2);
1288         printf("\n");
1289
1290         print_clk(IPG);
1291         print_clk(UART);
1292         print_clk(CSPI);
1293         print_clk(AHB);
1294         print_clk(AXI);
1295         print_clk(DDR);
1296         print_clk(ESDHC);
1297         print_clk(ESDHC2);
1298         print_clk(ESDHC3);
1299         print_clk(ESDHC4);
1300         print_clk(EMI_SLOW);
1301         print_clk(NFC);
1302         print_clk(IPG_PER);
1303         print_clk(ARM);
1304 }
1305
1306 static struct clk_lookup {
1307         const char *name;
1308         unsigned int index;
1309 } mx6_clk_lookup[] = {
1310         { "arm", MXC_ARM_CLK, },
1311         { "nfc", MXC_NFC_CLK, },
1312 };
1313
1314 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1315 {
1316         int i;
1317         unsigned long freq;
1318         unsigned long ref = ~0UL;
1319
1320         if (argc < 2) {
1321                 do_mx6_showclocks();
1322                 return CMD_RET_SUCCESS;
1323         } else if (argc == 2 || argc > 4) {
1324                 return CMD_RET_USAGE;
1325         }
1326
1327         freq = simple_strtoul(argv[2], NULL, 0);
1328         if (freq == 0) {
1329                 printf("Invalid clock frequency %lu\n", freq);
1330                 return CMD_RET_FAILURE;
1331         }
1332         if (argc > 3) {
1333                 ref = simple_strtoul(argv[3], NULL, 0);
1334         }
1335         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1336                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1337                         switch (mx6_clk_lookup[i].index) {
1338                         case MXC_ARM_CLK:
1339                                 if (argc > 3)
1340                                         return CMD_RET_USAGE;
1341                                 ref = MXC_HCLK;
1342                                 break;
1343
1344                         case MXC_NFC_CLK:
1345                                 if (argc > 3 && ref > 3) {
1346                                         printf("Invalid clock selector value: %lu\n", ref);
1347                                         return CMD_RET_FAILURE;
1348                                 }
1349                                 break;
1350                         }
1351                         printf("Setting %s clock to %lu MHz\n",
1352                                 mx6_clk_lookup[i].name, freq);
1353                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1354                                 break;
1355                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1356                         printf("%s clock set to %lu.%03lu MHz\n",
1357                                 mx6_clk_lookup[i].name,
1358                                 freq / 1000000, freq / 1000 % 1000);
1359                         return CMD_RET_SUCCESS;
1360                 }
1361         }
1362         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1363                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1364                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1365                         printf("\t%s\n", mx6_clk_lookup[i].name);
1366                 }
1367         } else {
1368                 printf("Failed to set clock %s to %s MHz\n",
1369                         argv[1], argv[2]);
1370         }
1371         return CMD_RET_FAILURE;
1372 }
1373
1374 #ifndef CONFIG_SOC_MX6SX
1375 void enable_ipu_clock(void)
1376 {
1377         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1378         int reg;
1379         reg = readl(&mxc_ccm->CCGR3);
1380         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1381         writel(reg, &mxc_ccm->CCGR3);
1382 }
1383 #endif
1384 /***************************************************/
1385
1386 U_BOOT_CMD(
1387         clocks, 4, 0, do_clocks,
1388         "display/set clocks",
1389         "                    - display clock settings\n"
1390         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1391 );