imx: mx6: ccm: Change the clock settings for i.MX6QP
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / clock.c
1 /*
2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <div64.h>
9 #include <asm/io.h>
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15
16 enum pll_clocks {
17         PLL_ARM,        /* PLL1: ARM PLL */
18         PLL_528,        /* PLL2: System Bus PLL*/
19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
20         PLL_AUDIO,      /* PLL4: Audio PLL */
21         PLL_VIDEO,      /* PLL5: Video PLL */
22         PLL_ENET,       /* PLL6: ENET PLL */
23         PLL_USB2,       /* PLL7: USB2 PLL */
24         PLL_MLB,        /* PLL8: MLB PLL */
25 };
26
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
29
30 int clk_enable(struct clk *clk)
31 {
32         int ret = 0;
33
34         if (!clk)
35                 return 0;
36         if (clk->usecount == 0) {
37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
38                 ret = clk->enable(clk);
39                 if (ret)
40                         return ret;
41                 clk->usecount++;
42         }
43         assert(clk->usecount > 0);
44         return ret;
45 }
46
47 void clk_disable(struct clk *clk)
48 {
49         if (!clk)
50                 return;
51
52         assert(clk->usecount > 0);
53         if (!(--clk->usecount)) {
54                 if (clk->disable) {
55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
56                         clk->disable(clk);
57                 }
58         }
59 }
60
61 int clk_get_usecount(struct clk *clk)
62 {
63         if (clk == NULL)
64                 return 0;
65
66         return clk->usecount;
67 }
68
69 u32 clk_get_rate(struct clk *clk)
70 {
71         if (!clk)
72                 return 0;
73
74         return clk->rate;
75 }
76
77 struct clk *clk_get_parent(struct clk *clk)
78 {
79         if (!clk)
80                 return 0;
81
82         return clk->parent;
83 }
84
85 int clk_set_rate(struct clk *clk, unsigned long rate)
86 {
87         if (clk && clk->set_rate)
88                 clk->set_rate(clk, rate);
89         return clk->rate;
90 }
91
92 long clk_round_rate(struct clk *clk, unsigned long rate)
93 {
94         if (clk == NULL || !clk->round_rate)
95                 return 0;
96
97         return clk->round_rate(clk, rate);
98 }
99
100 int clk_set_parent(struct clk *clk, struct clk *parent)
101 {
102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103                 clk ? clk->parent : NULL);
104
105         if (!clk || clk == parent)
106                 return 0;
107
108         if (clk->set_parent) {
109                 int ret;
110
111                 ret = clk->set_parent(clk, parent);
112                 if (ret)
113                         return ret;
114         }
115         clk->parent = parent;
116         return 0;
117 }
118
119 #ifdef CONFIG_MXC_OCOTP
120 void enable_ocotp_clk(unsigned char enable)
121 {
122         u32 reg;
123
124         reg = __raw_readl(&imx_ccm->CCGR2);
125         if (enable)
126                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
127         else
128                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
129         __raw_writel(reg, &imx_ccm->CCGR2);
130 }
131 #endif
132
133 #ifdef CONFIG_NAND_MXS
134 void setup_gpmi_io_clk(u32 cfg)
135 {
136         /* Disable clocks per ERR007177 from MX6 errata */
137         clrbits_le32(&imx_ccm->CCGR4,
138                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
139                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
140                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
141                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
142                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
143
144         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
145
146         clrsetbits_le32(&imx_ccm->cs2cdr,
147                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
148                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
149                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
150                         cfg);
151
152         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
153         setbits_le32(&imx_ccm->CCGR4,
154                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
155                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
156                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
158                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
159 }
160 #endif
161
162 void enable_usboh3_clk(unsigned char enable)
163 {
164         u32 reg;
165
166         reg = __raw_readl(&imx_ccm->CCGR6);
167         if (enable)
168                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
169         else
170                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
171         __raw_writel(reg, &imx_ccm->CCGR6);
172
173 }
174
175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
176 void enable_enet_clk(unsigned char enable)
177 {
178         u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
179
180         if (enable)
181                 setbits_le32(&imx_ccm->CCGR1, mask);
182         else
183                 clrbits_le32(&imx_ccm->CCGR1, mask);
184 }
185 #endif
186
187 #ifdef CONFIG_MXC_UART
188 void enable_uart_clk(unsigned char enable)
189 {
190         u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
191
192         if (enable)
193                 setbits_le32(&imx_ccm->CCGR5, mask);
194         else
195                 clrbits_le32(&imx_ccm->CCGR5, mask);
196 }
197 #endif
198
199 #ifdef CONFIG_MMC
200 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
201 {
202         u32 mask;
203
204         if (bus_num > 3)
205                 return -EINVAL;
206
207         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
208         if (enable)
209                 setbits_le32(&imx_ccm->CCGR6, mask);
210         else
211                 clrbits_le32(&imx_ccm->CCGR6, mask);
212
213         return 0;
214 }
215 #endif
216
217 #ifdef CONFIG_SYS_I2C_MXC
218 /* i2c_num can be from 0 - 3 */
219 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
220 {
221         u32 reg;
222         u32 mask;
223         u32 *addr;
224
225         if (i2c_num > 3)
226                 return -EINVAL;
227         if (i2c_num < 3) {
228                 mask = MXC_CCM_CCGR_CG_MASK
229                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
230                         + (i2c_num << 1));
231                 reg = __raw_readl(&imx_ccm->CCGR2);
232                 if (enable)
233                         reg |= mask;
234                 else
235                         reg &= ~mask;
236                 __raw_writel(reg, &imx_ccm->CCGR2);
237         } else {
238                 if (is_cpu_type(MXC_CPU_MX6SX)) {
239                         mask = MXC_CCM_CCGR6_I2C4_MASK;
240                         addr = &imx_ccm->CCGR6;
241                 } else {
242                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
243                         addr = &imx_ccm->CCGR1;
244                 }
245                 reg = __raw_readl(addr);
246                 if (enable)
247                         reg |= mask;
248                 else
249                         reg &= ~mask;
250                 __raw_writel(reg, addr);
251         }
252         return 0;
253 }
254 #endif
255
256 /* spi_num can be from 0 - SPI_MAX_NUM */
257 int enable_spi_clk(unsigned char enable, unsigned spi_num)
258 {
259         u32 reg;
260         u32 mask;
261
262         if (spi_num > SPI_MAX_NUM)
263                 return -EINVAL;
264
265         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
266         reg = __raw_readl(&imx_ccm->CCGR1);
267         if (enable)
268                 reg |= mask;
269         else
270                 reg &= ~mask;
271         __raw_writel(reg, &imx_ccm->CCGR1);
272         return 0;
273 }
274 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
275 {
276         u32 div;
277
278         switch (pll) {
279         case PLL_ARM:
280                 div = __raw_readl(&anatop->pll_arm);
281                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
282                         /* Assume the bypass clock is always derived from OSC */
283                         return infreq;
284                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
285
286                 return infreq * div / 2;
287         case PLL_528:
288                 div = __raw_readl(&anatop->pll_528);
289                 if (div & BM_ANADIG_PLL_528_BYPASS)
290                         return infreq;
291                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
292
293                 return infreq * (20 + div * 2);
294         case PLL_USBOTG:
295                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
296                 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
297                         return infreq;
298                 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
299
300                 return infreq * (20 + div * 2);
301         case PLL_AUDIO:
302                 div = __raw_readl(&anatop->pll_audio);
303                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
304                         return infreq;
305                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
306
307                 return infreq * div;
308         case PLL_VIDEO:
309                 div = __raw_readl(&anatop->pll_video);
310                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
311                         return infreq;
312                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
313
314                 return infreq * div;
315         case PLL_ENET:
316                 div = __raw_readl(&anatop->pll_enet);
317                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
318                         return infreq;
319                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
320
321                 return 25000000 * (div + (div >> 1) + 1);
322         case PLL_USB2:
323                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
324                 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
325                         return infreq;
326                 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
327
328                 return infreq * (20 + div * 2);
329         case PLL_MLB:
330                 div = __raw_readl(&anatop->pll_mlb);
331                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
332                         return infreq;
333                 /* unknown external clock provided on MLB_CLK pin */
334                 return 0;
335         }
336         return 0;
337 }
338 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
339 {
340         u32 div;
341         u64 freq;
342         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
343
344         switch (pll) {
345         case PLL_528:
346                 if (pfd_num == 3) {
347                         /* No PFD3 on PLL2 */
348                         return 0;
349                 }
350                 div = __raw_readl(&anatop->pfd_528);
351                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
352                 break;
353         case PLL_USBOTG:
354                 div = __raw_readl(&anatop->pfd_480);
355                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
356                 break;
357         default:
358                 /* No PFD on other PLL */
359                 return 0;
360         }
361
362         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
363                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
364 }
365
366 static u32 get_mcu_main_clk(void)
367 {
368         u32 reg, freq;
369
370         reg = __raw_readl(&imx_ccm->cacrr);
371         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
372         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
373         freq = decode_pll(PLL_ARM, MXC_HCLK);
374
375         return freq / (reg + 1);
376 }
377
378 u32 get_periph_clk(void)
379 {
380         u32 reg, freq = 0;
381
382         reg = __raw_readl(&imx_ccm->cbcdr);
383         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
384                 reg = __raw_readl(&imx_ccm->cbcmr);
385                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
386                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
387
388                 switch (reg) {
389                 case 0:
390                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
391                         break;
392                 case 1:
393                 case 2:
394                         freq = MXC_HCLK;
395                         break;
396                 }
397         } else {
398                 reg = __raw_readl(&imx_ccm->cbcmr);
399                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
400                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
401
402                 switch (reg) {
403                 case 0:
404                         freq = decode_pll(PLL_528, MXC_HCLK);
405                         break;
406                 case 1:
407                         freq = mxc_get_pll_pfd(PLL_528, 2);
408                         break;
409                 case 2:
410                         freq = mxc_get_pll_pfd(PLL_528, 0);
411                         break;
412                 case 3:
413                         /* static / 2 divider */
414                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
415                         break;
416                 }
417         }
418
419         return freq;
420 }
421
422 static u32 get_ipg_clk(void)
423 {
424         u32 reg, ipg_podf;
425
426         reg = __raw_readl(&imx_ccm->cbcdr);
427         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
428         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
429
430         return get_ahb_clk() / (ipg_podf + 1);
431 }
432
433 static u32 get_ipg_per_clk(void)
434 {
435         u32 reg, perclk_podf;
436
437         reg = __raw_readl(&imx_ccm->cscmr1);
438         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
439             is_mx6dqp()) {
440                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
441                         return MXC_HCLK; /* OSC 24Mhz */
442         }
443
444         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
445
446         return get_ipg_clk() / (perclk_podf + 1);
447 }
448
449 static u32 get_uart_clk(void)
450 {
451         u32 reg, uart_podf;
452         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
453         reg = __raw_readl(&imx_ccm->cscdr1);
454
455         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
456             is_mx6dqp()) {
457                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
458                         freq = MXC_HCLK;
459         }
460
461         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
462         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
463
464         return freq / (uart_podf + 1);
465 }
466
467 static u32 get_cspi_clk(void)
468 {
469         u32 reg, cspi_podf;
470
471         reg = __raw_readl(&imx_ccm->cscdr2);
472         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
473                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
474
475         if (is_mx6dqp()) {
476                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
477                         return MXC_HCLK / (cspi_podf + 1);
478         }
479
480         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
481 }
482
483 static u32 get_axi_clk(void)
484 {
485         u32 root_freq, axi_podf;
486         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
487
488         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
489         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
490
491         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
492                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
493                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
494                 else
495                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
496         } else
497                 root_freq = get_periph_clk();
498
499         return  root_freq / (axi_podf + 1);
500 }
501
502 static u32 get_emi_slow_clk(void)
503 {
504         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
505
506         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
507         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
508         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
509         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
510         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
511
512         switch (emi_clk_sel) {
513         case 0:
514                 root_freq = get_axi_clk();
515                 break;
516         case 1:
517                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
518                 break;
519         case 2:
520                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
521                 break;
522         case 3:
523                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
524                 break;
525         }
526
527         return root_freq / (emi_slow_podf + 1);
528 }
529
530 static u32 get_nfc_clk(void)
531 {
532         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
533         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
534         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
535         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
536                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
537         u32 root_freq;
538
539         switch (nfc_clk_sel) {
540         case 0:
541                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
542                 break;
543         case 1:
544                 root_freq = decode_pll(PLL_528, MXC_HCLK);
545                 break;
546         case 2:
547                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
548                 break;
549         case 3:
550                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
551                 break;
552         }
553
554         return root_freq / (pred + 1) / (podf + 1);
555 }
556
557 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
558                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
559                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
560
561 static int set_nfc_clk(u32 ref, u32 freq_khz)
562 {
563         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
564         u32 podf;
565         u32 pred;
566         int nfc_clk_sel;
567         u32 root_freq;
568         u32 min_err = ~0;
569         u32 nfc_val = ~0;
570         u32 freq = freq_khz * 1000;
571
572         for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
573                 u32 act_freq;
574                 u32 err;
575
576                 if (ref < 4 && ref != nfc_clk_sel)
577                         continue;
578
579                 switch (nfc_clk_sel) {
580                 case 0:
581                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
582                         break;
583                 case 1:
584                         root_freq = decode_pll(PLL_528, MXC_HCLK);
585                         break;
586                 case 2:
587                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
588                         break;
589                 case 3:
590                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
591                         break;
592                 }
593                 if (root_freq < freq)
594                         continue;
595
596                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
597                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
598                 act_freq = root_freq / pred / podf;
599                 err = (freq - act_freq) * 100 / freq;
600                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
601                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
602                 if (act_freq > freq)
603                         continue;
604                 if (err < min_err) {
605                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
606                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
607                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
608                         min_err = err;
609                         if (err == 0)
610                                 break;
611                 }
612         }
613
614         if (nfc_val == ~0 || min_err > 10)
615                 return -EINVAL;
616
617         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
618                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
619                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
620                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
621                         &imx_ccm->cs2cdr);
622         } else {
623                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
624         }
625         return 0;
626 }
627
628 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
629 static u32 get_mmdc_ch0_clk(void)
630 {
631         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
632         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
633         u32 freq, podf;
634
635         podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
636                         >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
637
638         switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
639                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
640         case 0:
641                 freq = decode_pll(PLL_528, MXC_HCLK);
642                 break;
643         case 1:
644                 freq = mxc_get_pll_pfd(PLL_528, 2);
645                 break;
646         case 2:
647                 freq = mxc_get_pll_pfd(PLL_528, 0);
648                 break;
649         case 3:
650                 /* static / 2 divider */
651                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
652         }
653
654         return freq / (podf + 1);
655
656 }
657 #else
658 static u32 get_mmdc_ch0_clk(void)
659 {
660         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
661         u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
662                                 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
663
664         return get_periph_clk() / (mmdc_ch0_podf + 1);
665 }
666 #endif
667
668 #ifdef CONFIG_SOC_MX6SX
669 /* qspi_num can be from 0 - 1 */
670 void enable_qspi_clk(int qspi_num)
671 {
672         u32 reg = 0;
673         /* Enable QuadSPI clock */
674         switch (qspi_num) {
675         case 0:
676                 /* disable the clock gate */
677                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
678
679                 /* set 50M  : (50 = 396 / 2 / 4) */
680                 reg = readl(&imx_ccm->cscmr1);
681                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
682                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
683                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
684                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
685                 writel(reg, &imx_ccm->cscmr1);
686
687                 /* enable the clock gate */
688                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
689                 break;
690         case 1:
691                 /*
692                  * disable the clock gate
693                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
694                  * disable both of them.
695                  */
696                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
697                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
698
699                 /* set 50M  : (50 = 396 / 2 / 4) */
700                 reg = readl(&imx_ccm->cs2cdr);
701                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
702                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
703                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
704                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
705                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
706                 writel(reg, &imx_ccm->cs2cdr);
707
708                 /*enable the clock gate*/
709                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
710                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
711                 break;
712         default:
713                 break;
714         }
715 }
716 #endif
717
718 #ifdef CONFIG_FEC_MXC
719 int enable_fec_anatop_clock(enum enet_freq freq)
720 {
721         u32 reg = 0;
722         s32 timeout = 100000;
723
724         struct anatop_regs __iomem *anatop =
725                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
726
727         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
728                 return -EINVAL;
729
730         reg = readl(&anatop->pll_enet);
731         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
732         reg |= freq;
733
734         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
735             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
736                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
737                 writel(reg, &anatop->pll_enet);
738                 while (timeout--) {
739                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
740                                 break;
741                 }
742                 if (timeout < 0)
743                         return -ETIMEDOUT;
744         }
745
746         /* Enable FEC clock */
747         reg |= BM_ANADIG_PLL_ENET_ENABLE;
748         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
749         writel(reg, &anatop->pll_enet);
750
751 #ifdef CONFIG_SOC_MX6SX
752         /*
753          * Set enet ahb clock to 200MHz
754          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
755          */
756         reg = readl(&imx_ccm->chsccdr);
757         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
758                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
759                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
760         /* PLL2 PFD2 */
761         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
762         /* Div = 2*/
763         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
764         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
765         writel(reg, &imx_ccm->chsccdr);
766
767         /* Enable enet system clock */
768         reg = readl(&imx_ccm->CCGR3);
769         reg |= MXC_CCM_CCGR3_ENET_MASK;
770         writel(reg, &imx_ccm->CCGR3);
771 #endif
772         return 0;
773 }
774 #endif
775
776 static u32 get_usdhc_clk(u32 port)
777 {
778         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
779         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
780         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
781
782         switch (port) {
783         case 0:
784                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
785                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
786                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
787
788                 break;
789         case 1:
790                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
791                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
792                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
793
794                 break;
795         case 2:
796                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
797                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
798                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
799
800                 break;
801         case 3:
802                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
803                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
804                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
805
806                 break;
807         default:
808                 break;
809         }
810
811         if (clk_sel)
812                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
813         else
814                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
815
816         return root_freq / (usdhc_podf + 1);
817 }
818
819 u32 imx_get_uartclk(void)
820 {
821         return get_uart_clk();
822 }
823
824 u32 imx_get_fecclk(void)
825 {
826         return mxc_get_clock(MXC_IPG_CLK);
827 }
828
829 static int enable_enet_pll(uint32_t en)
830 {
831         u32 reg;
832         s32 timeout = 100000;
833
834         /* Enable PLLs */
835         reg = readl(&anatop->pll_enet);
836         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
837         writel(reg, &anatop->pll_enet);
838         reg |= BM_ANADIG_PLL_ENET_ENABLE;
839         while (timeout--) {
840                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
841                         break;
842         }
843         if (timeout <= 0)
844                 return -EIO;
845         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
846         writel(reg, &anatop->pll_enet);
847         reg |= en;
848         writel(reg, &anatop->pll_enet);
849         return 0;
850 }
851
852 #ifndef CONFIG_SOC_MX6SX
853 static void ungate_sata_clock(void)
854 {
855         struct mxc_ccm_reg *const imx_ccm =
856                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
857
858         /* Enable SATA clock. */
859         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
860 }
861 #endif
862
863 static void ungate_pcie_clock(void)
864 {
865         struct mxc_ccm_reg *const imx_ccm =
866                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
867
868         /* Enable PCIe clock. */
869         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
870 }
871
872 #ifndef CONFIG_SOC_MX6SX
873 int enable_sata_clock(void)
874 {
875         ungate_sata_clock();
876         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
877 }
878
879 void disable_sata_clock(void)
880 {
881         struct mxc_ccm_reg *const imx_ccm =
882                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
883
884         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
885 }
886 #endif
887
888 int enable_pcie_clock(void)
889 {
890         struct anatop_regs *anatop_regs =
891                 (struct anatop_regs *)ANATOP_BASE_ADDR;
892         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
893         u32 lvds1_clk_sel;
894
895         /*
896          * Here be dragons!
897          *
898          * The register ANATOP_MISC1 is not documented in the Freescale
899          * MX6RM. The register that is mapped in the ANATOP space and
900          * marked as ANATOP_MISC1 is actually documented in the PMU section
901          * of the datasheet as PMU_MISC1.
902          *
903          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
904          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
905          * for PCI express link that is clocked from the i.MX6.
906          */
907 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
908 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
909 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
910 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
911 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
912
913         if (is_cpu_type(MXC_CPU_MX6SX))
914                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
915         else
916                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
917
918         clrsetbits_le32(&anatop_regs->ana_misc1,
919                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
920                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
921                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
922
923         /* PCIe reference clock sourced from AXI. */
924         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
925
926         /* Party time! Ungate the clock to the PCIe. */
927 #ifndef CONFIG_SOC_MX6SX
928         ungate_sata_clock();
929 #endif
930         ungate_pcie_clock();
931
932         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
933                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
934 }
935
936 #ifdef CONFIG_SECURE_BOOT
937 void hab_caam_clock_enable(unsigned char enable)
938 {
939         u32 reg;
940
941         /* CG4 ~ CG6, CAAM clocks */
942         reg = __raw_readl(&imx_ccm->CCGR0);
943         if (enable)
944                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
945                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
946                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
947         else
948                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
949                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
950                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
951         __raw_writel(reg, &imx_ccm->CCGR0);
952
953         /* EMI slow clk */
954         reg = __raw_readl(&imx_ccm->CCGR6);
955         if (enable)
956                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
957         else
958                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
959         __raw_writel(reg, &imx_ccm->CCGR6);
960 }
961 #endif
962
963 static void enable_pll3(void)
964 {
965         struct anatop_regs __iomem *anatop =
966                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
967
968         /* make sure pll3 is enabled */
969         if ((readl(&anatop->usb1_pll_480_ctrl) &
970                         BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
971                 /* enable pll's power */
972                 writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
973                        &anatop->usb1_pll_480_ctrl_set);
974                 writel(0x80, &anatop->ana_misc2_clr);
975                 /* wait for pll lock */
976                 while ((readl(&anatop->usb1_pll_480_ctrl) &
977                         BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
978                         ;
979                 /* disable bypass */
980                 writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
981                        &anatop->usb1_pll_480_ctrl_clr);
982                 /* enable pll output */
983                 writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
984                        &anatop->usb1_pll_480_ctrl_set);
985         }
986 }
987
988 void enable_thermal_clk(void)
989 {
990         enable_pll3();
991 }
992
993 void ipu_clk_enable(void)
994 {
995         u32 reg = readl(&imx_ccm->CCGR3);
996         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
997         writel(reg, &imx_ccm->CCGR3);
998 }
999
1000 void ipu_clk_disable(void)
1001 {
1002         u32 reg = readl(&imx_ccm->CCGR3);
1003         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1004         writel(reg, &imx_ccm->CCGR3);
1005 }
1006
1007 void ipu_di_clk_enable(int di)
1008 {
1009         switch (di) {
1010         case 0:
1011                 setbits_le32(&imx_ccm->CCGR3,
1012                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1013                 break;
1014         case 1:
1015                 setbits_le32(&imx_ccm->CCGR3,
1016                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1017                 break;
1018         default:
1019                 printf("%s: Invalid DI index %d\n", __func__, di);
1020         }
1021 }
1022
1023 void ipu_di_clk_disable(int di)
1024 {
1025         switch (di) {
1026         case 0:
1027                 clrbits_le32(&imx_ccm->CCGR3,
1028                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1029                 break;
1030         case 1:
1031                 clrbits_le32(&imx_ccm->CCGR3,
1032                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1033                 break;
1034         default:
1035                 printf("%s: Invalid DI index %d\n", __func__, di);
1036         }
1037 }
1038
1039 void ldb_clk_enable(int ldb)
1040 {
1041         switch (ldb) {
1042         case 0:
1043                 setbits_le32(&imx_ccm->CCGR3,
1044                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1045                 break;
1046         case 1:
1047                 setbits_le32(&imx_ccm->CCGR3,
1048                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1049                 break;
1050         default:
1051                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1052         }
1053 }
1054
1055 void ldb_clk_disable(int ldb)
1056 {
1057         switch (ldb) {
1058         case 0:
1059                 clrbits_le32(&imx_ccm->CCGR3,
1060                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1061                 break;
1062         case 1:
1063                 clrbits_le32(&imx_ccm->CCGR3,
1064                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1065                 break;
1066         default:
1067                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1068         }
1069 }
1070
1071 void ocotp_clk_enable(void)
1072 {
1073         u32 reg = readl(&imx_ccm->CCGR2);
1074         reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1075         writel(reg, &imx_ccm->CCGR2);
1076 }
1077
1078 void ocotp_clk_disable(void)
1079 {
1080         u32 reg = readl(&imx_ccm->CCGR2);
1081         reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1082         writel(reg, &imx_ccm->CCGR2);
1083 }
1084
1085 unsigned int mxc_get_clock(enum mxc_clock clk)
1086 {
1087         switch (clk) {
1088         case MXC_ARM_CLK:
1089                 return get_mcu_main_clk();
1090         case MXC_PER_CLK:
1091                 return get_periph_clk();
1092         case MXC_AHB_CLK:
1093                 return get_ahb_clk();
1094         case MXC_IPG_CLK:
1095                 return get_ipg_clk();
1096         case MXC_IPG_PERCLK:
1097         case MXC_I2C_CLK:
1098                 return get_ipg_per_clk();
1099         case MXC_UART_CLK:
1100                 return get_uart_clk();
1101         case MXC_CSPI_CLK:
1102                 return get_cspi_clk();
1103         case MXC_AXI_CLK:
1104                 return get_axi_clk();
1105         case MXC_EMI_SLOW_CLK:
1106                 return get_emi_slow_clk();
1107         case MXC_DDR_CLK:
1108                 return get_mmdc_ch0_clk();
1109         case MXC_ESDHC_CLK:
1110                 return get_usdhc_clk(0);
1111         case MXC_ESDHC2_CLK:
1112                 return get_usdhc_clk(1);
1113         case MXC_ESDHC3_CLK:
1114                 return get_usdhc_clk(2);
1115         case MXC_ESDHC4_CLK:
1116                 return get_usdhc_clk(3);
1117         case MXC_SATA_CLK:
1118                 return get_ahb_clk();
1119         case MXC_NFC_CLK:
1120                 return get_nfc_clk();
1121         default:
1122                 printf("Unsupported MXC CLK: %d\n", clk);
1123         }
1124
1125         return 0;
1126 }
1127
1128 static inline int gcd(int m, int n)
1129 {
1130         int t;
1131         while (m > 0) {
1132                 if (n > m) {
1133                         t = m;
1134                         m = n;
1135                         n = t;
1136                 } /* swap */
1137                 m -= n;
1138         }
1139         return n;
1140 }
1141
1142 /* Config CPU clock */
1143 static int set_arm_clk(u32 ref, u32 freq_khz)
1144 {
1145         int d;
1146         int div = 0;
1147         int mul = 0;
1148         u32 min_err = ~0;
1149         u32 reg;
1150
1151         if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1152                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1153                         freq_khz / 1000, freq_khz % 1000,
1154                         54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1155                         108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1156                 return -EINVAL;
1157         }
1158
1159         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1160                 int m = freq_khz * 2 * d / (ref / 1000);
1161                 u32 f;
1162                 u32 err;
1163
1164                 if (m > 108) {
1165                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1166                                 d, m);
1167                         break;
1168                 }
1169
1170                 f = ref * m / d / 2;
1171                 if (f > freq_khz * 1000) {
1172                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1173                                 d, m, f, freq_khz);
1174                         if (--m < 54)
1175                                 return -EINVAL;
1176                         f = ref * m / d / 2;
1177                 }
1178                 err = freq_khz * 1000 - f;
1179                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1180                         d, m, f, freq_khz, err);
1181                 if (err < min_err) {
1182                         mul = m;
1183                         div = d;
1184                         min_err = err;
1185                         if (err == 0)
1186                                 break;
1187                 }
1188         }
1189         if (min_err == ~0)
1190                 return -EINVAL;
1191         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1192                 mul, div, freq_khz / 1000, freq_khz % 1000,
1193                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1194
1195         reg = readl(&anatop->pll_arm);
1196         debug("anadig_pll_arm=%08x -> %08x\n",
1197                 reg, (reg & ~0x7f) | mul);
1198
1199         reg |= 1 << 16;
1200         writel(reg, &anatop->pll_arm); /* bypass PLL */
1201
1202         reg = (reg & ~0x7f) | mul;
1203         writel(reg, &anatop->pll_arm);
1204
1205         writel(div - 1, &imx_ccm->cacrr);
1206
1207         reg &= ~(1 << 16);
1208         writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1209
1210         return 0;
1211 }
1212
1213 /*
1214  * This function assumes the expected core clock has to be changed by
1215  * modifying the PLL. This is NOT true always but for most of the times,
1216  * it is. So it assumes the PLL output freq is the same as the expected
1217  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1218  * In the latter case, it will try to increase the presc value until
1219  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1220  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1221  * on the targeted PLL and reference input clock to the PLL. Lastly,
1222  * it sets the register based on these values along with the dividers.
1223  * Note 1) There is no value checking for the passed-in divider values
1224  *         so the caller has to make sure those values are sensible.
1225  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1226  *         exceed NFC_CLK_MAX.
1227  *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
1228  *         177MHz for higher voltage, this function fixes the max to 133MHz.
1229  *      4) This function should not have allowed diag_printf() calls since
1230  *         the serial driver has been stoped. But leave then here to allow
1231  *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1232  */
1233 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1234 {
1235         int ret;
1236
1237         freq *= 1000;
1238
1239         switch (clk) {
1240         case MXC_ARM_CLK:
1241                 ret = set_arm_clk(ref, freq);
1242                 break;
1243
1244         case MXC_NFC_CLK:
1245                 ret = set_nfc_clk(ref, freq);
1246                 break;
1247
1248         default:
1249                 printf("Warning: Unsupported or invalid clock type: %d\n",
1250                         clk);
1251                 return -EINVAL;
1252         }
1253
1254         return ret;
1255 }
1256
1257 /*
1258  * Dump some core clocks.
1259  */
1260 #define print_pll(pll)  {                               \
1261         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1262         printf("%-12s %4d.%03d MHz\n", #pll,            \
1263                 __pll / 1000000, __pll / 1000 % 1000);  \
1264         }
1265
1266 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1267
1268 #define print_clk(clk)  {                               \
1269         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1270         printf("%-12s %4d.%03d MHz\n", #clk,            \
1271                 __clk / 1000000, __clk / 1000 % 1000);  \
1272         }
1273
1274 #define print_pfd(pll, pfd)     {                                       \
1275         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1276         if (__pfd & (0x80 << 8 * pfd)) {                                \
1277                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1278         } else {                                                        \
1279                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1280                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1281                         pll * 18 / __pfd,                               \
1282                         pll * 18 * 1000 / __pfd % 1000);                \
1283         }                                                               \
1284 }
1285
1286 static void do_mx6_showclocks(void)
1287 {
1288         print_pll(PLL_ARM);
1289         print_pll(PLL_528);
1290         print_pll(PLL_USBOTG);
1291         print_pll(PLL_AUDIO);
1292         print_pll(PLL_VIDEO);
1293         print_pll(PLL_ENET);
1294         print_pll(PLL_USB2);
1295         printf("\n");
1296
1297         print_pfd(480, 0);
1298         print_pfd(480, 1);
1299         print_pfd(480, 2);
1300         print_pfd(480, 3);
1301         print_pfd(528, 0);
1302         print_pfd(528, 1);
1303         print_pfd(528, 2);
1304         printf("\n");
1305
1306         print_clk(IPG);
1307         print_clk(UART);
1308         print_clk(CSPI);
1309         print_clk(AHB);
1310         print_clk(AXI);
1311         print_clk(DDR);
1312         print_clk(ESDHC);
1313         print_clk(ESDHC2);
1314         print_clk(ESDHC3);
1315         print_clk(ESDHC4);
1316         print_clk(EMI_SLOW);
1317         print_clk(NFC);
1318         print_clk(IPG_PER);
1319         print_clk(ARM);
1320 }
1321
1322 static struct clk_lookup {
1323         const char *name;
1324         unsigned int index;
1325 } mx6_clk_lookup[] = {
1326         { "arm", MXC_ARM_CLK, },
1327         { "nfc", MXC_NFC_CLK, },
1328 };
1329
1330 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1331 {
1332         int i;
1333         unsigned long freq;
1334         unsigned long ref = ~0UL;
1335
1336         if (argc < 2) {
1337                 do_mx6_showclocks();
1338                 return CMD_RET_SUCCESS;
1339         } else if (argc == 2 || argc > 4) {
1340                 return CMD_RET_USAGE;
1341         }
1342
1343         freq = simple_strtoul(argv[2], NULL, 0);
1344         if (freq == 0) {
1345                 printf("Invalid clock frequency %lu\n", freq);
1346                 return CMD_RET_FAILURE;
1347         }
1348         if (argc > 3) {
1349                 ref = simple_strtoul(argv[3], NULL, 0);
1350         }
1351         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1352                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1353                         switch (mx6_clk_lookup[i].index) {
1354                         case MXC_ARM_CLK:
1355                                 if (argc > 3)
1356                                         return CMD_RET_USAGE;
1357                                 ref = MXC_HCLK;
1358                                 break;
1359
1360                         case MXC_NFC_CLK:
1361                                 if (argc > 3 && ref > 3) {
1362                                         printf("Invalid clock selector value: %lu\n", ref);
1363                                         return CMD_RET_FAILURE;
1364                                 }
1365                                 break;
1366                         }
1367                         printf("Setting %s clock to %lu MHz\n",
1368                                 mx6_clk_lookup[i].name, freq);
1369                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1370                                 break;
1371                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1372                         printf("%s clock set to %lu.%03lu MHz\n",
1373                                 mx6_clk_lookup[i].name,
1374                                 freq / 1000000, freq / 1000 % 1000);
1375                         return CMD_RET_SUCCESS;
1376                 }
1377         }
1378         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1379                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1380                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1381                         printf("\t%s\n", mx6_clk_lookup[i].name);
1382                 }
1383         } else {
1384                 printf("Failed to set clock %s to %s MHz\n",
1385                         argv[1], argv[2]);
1386         }
1387         return CMD_RET_FAILURE;
1388 }
1389
1390 #ifndef CONFIG_SOC_MX6SX
1391 void enable_ipu_clock(void)
1392 {
1393         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1394         int reg;
1395         reg = readl(&mxc_ccm->CCGR3);
1396         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1397         writel(reg, &mxc_ccm->CCGR3);
1398 }
1399 #endif
1400 /***************************************************/
1401
1402 U_BOOT_CMD(
1403         clocks, 4, 0, do_clocks,
1404         "display/set clocks",
1405         "                    - display clock settings\n"
1406         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1407 );