980a6eb6dc7bbb076186e9daf8e313f287c3fa0b
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / clock.c
1 /*
2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <div64.h>
9 #include <asm/io.h>
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15
16 enum pll_clocks {
17         PLL_ARM,        /* PLL1: ARM PLL */
18         PLL_528,        /* PLL2: System Bus PLL*/
19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
20         PLL_AUDIO,      /* PLL4: Audio PLL */
21         PLL_VIDEO,      /* PLL5: Video PLL */
22         PLL_ENET,       /* PLL6: ENET PLL */
23         PLL_USB2,       /* PLL7: USB2 PLL */
24         PLL_MLB,        /* PLL8: MLB PLL */
25 };
26
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
29
30 int clk_enable(struct clk *clk)
31 {
32         int ret = 0;
33
34         if (!clk)
35                 return 0;
36         if (clk->usecount == 0) {
37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
38                 ret = clk->enable(clk);
39                 if (ret)
40                         return ret;
41                 clk->usecount++;
42         }
43         assert(clk->usecount > 0);
44         return ret;
45 }
46
47 void clk_disable(struct clk *clk)
48 {
49         if (!clk)
50                 return;
51
52         assert(clk->usecount > 0);
53         if (!(--clk->usecount)) {
54                 if (clk->disable) {
55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
56                         clk->disable(clk);
57                 }
58         }
59 }
60
61 int clk_get_usecount(struct clk *clk)
62 {
63         if (clk == NULL)
64                 return 0;
65
66         return clk->usecount;
67 }
68
69 u32 clk_get_rate(struct clk *clk)
70 {
71         if (!clk)
72                 return 0;
73
74         return clk->rate;
75 }
76
77 struct clk *clk_get_parent(struct clk *clk)
78 {
79         if (!clk)
80                 return 0;
81
82         return clk->parent;
83 }
84
85 int clk_set_rate(struct clk *clk, unsigned long rate)
86 {
87         if (clk && clk->set_rate)
88                 clk->set_rate(clk, rate);
89         return clk->rate;
90 }
91
92 long clk_round_rate(struct clk *clk, unsigned long rate)
93 {
94         if (clk == NULL || !clk->round_rate)
95                 return 0;
96
97         return clk->round_rate(clk, rate);
98 }
99
100 int clk_set_parent(struct clk *clk, struct clk *parent)
101 {
102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103                 clk ? clk->parent : NULL);
104
105         if (!clk || clk == parent)
106                 return 0;
107
108         if (clk->set_parent) {
109                 int ret;
110
111                 ret = clk->set_parent(clk, parent);
112                 if (ret)
113                         return ret;
114         }
115         clk->parent = parent;
116         return 0;
117 }
118
119 #ifdef CONFIG_MXC_OCOTP
120 void enable_ocotp_clk(unsigned char enable)
121 {
122         u32 reg;
123
124         reg = __raw_readl(&imx_ccm->CCGR2);
125         if (enable)
126                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
127         else
128                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
129         __raw_writel(reg, &imx_ccm->CCGR2);
130 }
131 #endif
132
133 #ifdef CONFIG_NAND_MXS
134 void setup_gpmi_io_clk(u32 cfg)
135 {
136         /* Disable clocks per ERR007177 from MX6 errata */
137         clrbits_le32(&imx_ccm->CCGR4,
138                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
139                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
140                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
141                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
142                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
143
144         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
145
146         clrsetbits_le32(&imx_ccm->cs2cdr,
147                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
148                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
149                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
150                         cfg);
151
152         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
153         setbits_le32(&imx_ccm->CCGR4,
154                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
155                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
156                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
158                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
159 }
160 #endif
161
162 void enable_usboh3_clk(unsigned char enable)
163 {
164         u32 reg;
165
166         reg = __raw_readl(&imx_ccm->CCGR6);
167         if (enable)
168                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
169         else
170                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
171         __raw_writel(reg, &imx_ccm->CCGR6);
172
173 }
174
175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
176 void enable_enet_clk(unsigned char enable)
177 {
178         u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
179
180         if (enable)
181                 setbits_le32(&imx_ccm->CCGR1, mask);
182         else
183                 clrbits_le32(&imx_ccm->CCGR1, mask);
184 }
185 #endif
186
187 #ifdef CONFIG_MXC_UART
188 void enable_uart_clk(unsigned char enable)
189 {
190         u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
191
192         if (enable)
193                 setbits_le32(&imx_ccm->CCGR5, mask);
194         else
195                 clrbits_le32(&imx_ccm->CCGR5, mask);
196 }
197 #endif
198
199 #ifdef CONFIG_MMC
200 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
201 {
202         u32 mask;
203
204         if (bus_num > 3)
205                 return -EINVAL;
206
207         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
208         if (enable)
209                 setbits_le32(&imx_ccm->CCGR6, mask);
210         else
211                 clrbits_le32(&imx_ccm->CCGR6, mask);
212
213         return 0;
214 }
215 #endif
216
217 #ifdef CONFIG_SYS_I2C_MXC
218 /* i2c_num can be from 0 - 3 */
219 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
220 {
221         u32 reg;
222         u32 mask;
223         u32 *addr;
224
225         if (i2c_num > 3)
226                 return -EINVAL;
227         if (i2c_num < 3) {
228                 mask = MXC_CCM_CCGR_CG_MASK
229                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
230                         + (i2c_num << 1));
231                 reg = __raw_readl(&imx_ccm->CCGR2);
232                 if (enable)
233                         reg |= mask;
234                 else
235                         reg &= ~mask;
236                 __raw_writel(reg, &imx_ccm->CCGR2);
237         } else {
238                 if (is_cpu_type(MXC_CPU_MX6SX)) {
239                         mask = MXC_CCM_CCGR6_I2C4_MASK;
240                         addr = &imx_ccm->CCGR6;
241                 } else {
242                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
243                         addr = &imx_ccm->CCGR1;
244                 }
245                 reg = __raw_readl(addr);
246                 if (enable)
247                         reg |= mask;
248                 else
249                         reg &= ~mask;
250                 __raw_writel(reg, addr);
251         }
252         return 0;
253 }
254 #endif
255
256 /* spi_num can be from 0 - SPI_MAX_NUM */
257 int enable_spi_clk(unsigned char enable, unsigned spi_num)
258 {
259         u32 reg;
260         u32 mask;
261
262         if (spi_num > SPI_MAX_NUM)
263                 return -EINVAL;
264
265         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
266         reg = __raw_readl(&imx_ccm->CCGR1);
267         if (enable)
268                 reg |= mask;
269         else
270                 reg &= ~mask;
271         __raw_writel(reg, &imx_ccm->CCGR1);
272         return 0;
273 }
274 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
275 {
276         u32 div;
277
278         switch (pll) {
279         case PLL_ARM:
280                 div = __raw_readl(&anatop->pll_arm);
281                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
282                         /* Assume the bypass clock is always derived from OSC */
283                         return infreq;
284                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
285
286                 return infreq * div / 2;
287         case PLL_528:
288                 div = __raw_readl(&anatop->pll_528);
289                 if (div & BM_ANADIG_PLL_528_BYPASS)
290                         return infreq;
291                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
292
293                 return infreq * (20 + div * 2);
294         case PLL_USBOTG:
295                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
296                 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
297                         return infreq;
298                 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
299
300                 return infreq * (20 + div * 2);
301         case PLL_AUDIO:
302                 div = __raw_readl(&anatop->pll_audio);
303                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
304                         return infreq;
305                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
306
307                 return infreq * div;
308         case PLL_VIDEO:
309                 div = __raw_readl(&anatop->pll_video);
310                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
311                         return infreq;
312                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
313
314                 return infreq * div;
315         case PLL_ENET:
316                 div = __raw_readl(&anatop->pll_enet);
317                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
318                         return infreq;
319                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
320
321                 return 25000000 * (div + (div >> 1) + 1);
322         case PLL_USB2:
323                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
324                 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
325                         return infreq;
326                 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
327
328                 return infreq * (20 + div * 2);
329         case PLL_MLB:
330                 div = __raw_readl(&anatop->pll_mlb);
331                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
332                         return infreq;
333                 /* unknown external clock provided on MLB_CLK pin */
334                 return 0;
335         }
336         return 0;
337 }
338 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
339 {
340         u32 div;
341         u64 freq;
342         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
343
344         switch (pll) {
345         case PLL_528:
346                 if (pfd_num == 3) {
347                         /* No PFD3 on PLL2 */
348                         return 0;
349                 }
350                 div = __raw_readl(&anatop->pfd_528);
351                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
352                 break;
353         case PLL_USBOTG:
354                 div = __raw_readl(&anatop->pfd_480);
355                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
356                 break;
357         default:
358                 /* No PFD on other PLL */
359                 return 0;
360         }
361
362         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
363                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
364 }
365
366 static u32 get_mcu_main_clk(void)
367 {
368         u32 reg, freq;
369
370         reg = __raw_readl(&imx_ccm->cacrr);
371         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
372         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
373         freq = decode_pll(PLL_ARM, MXC_HCLK);
374
375         return freq / (reg + 1);
376 }
377
378 u32 get_periph_clk(void)
379 {
380         u32 reg, freq = 0;
381
382         reg = __raw_readl(&imx_ccm->cbcdr);
383         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
384                 reg = __raw_readl(&imx_ccm->cbcmr);
385                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
386                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
387
388                 switch (reg) {
389                 case 0:
390                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
391                         break;
392                 case 1:
393                 case 2:
394                         freq = MXC_HCLK;
395                         break;
396                 }
397         } else {
398                 reg = __raw_readl(&imx_ccm->cbcmr);
399                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
400                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
401
402                 switch (reg) {
403                 case 0:
404                         freq = decode_pll(PLL_528, MXC_HCLK);
405                         break;
406                 case 1:
407                         freq = mxc_get_pll_pfd(PLL_528, 2);
408                         break;
409                 case 2:
410                         freq = mxc_get_pll_pfd(PLL_528, 0);
411                         break;
412                 case 3:
413                         /* static / 2 divider */
414                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
415                         break;
416                 }
417         }
418
419         return freq;
420 }
421
422 static u32 get_ipg_clk(void)
423 {
424         u32 reg, ipg_podf;
425
426         reg = __raw_readl(&imx_ccm->cbcdr);
427         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
428         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
429
430         return get_ahb_clk() / (ipg_podf + 1);
431 }
432
433 static u32 get_ipg_per_clk(void)
434 {
435         u32 reg, perclk_podf;
436
437         reg = __raw_readl(&imx_ccm->cscmr1);
438 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
439         if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
440                 return MXC_HCLK; /* OSC 24Mhz */
441 #endif
442         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
443
444         return get_ipg_clk() / (perclk_podf + 1);
445 }
446
447 static u32 get_uart_clk(void)
448 {
449         u32 reg, uart_podf;
450         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
451         reg = __raw_readl(&imx_ccm->cscdr1);
452 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
453         if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
454                 freq = MXC_HCLK;
455 #endif
456         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
457         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
458
459         return freq / (uart_podf + 1);
460 }
461
462 static u32 get_cspi_clk(void)
463 {
464         u32 reg, cspi_podf;
465
466         reg = __raw_readl(&imx_ccm->cscdr2);
467         reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
468         cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
469
470         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
471 }
472
473 static u32 get_axi_clk(void)
474 {
475         u32 root_freq, axi_podf;
476         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
477
478         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
479         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
480
481         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
482                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
483                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
484                 else
485                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
486         } else
487                 root_freq = get_periph_clk();
488
489         return  root_freq / (axi_podf + 1);
490 }
491
492 static u32 get_emi_slow_clk(void)
493 {
494         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
495
496         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
497         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
498         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
499         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
500         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
501
502         switch (emi_clk_sel) {
503         case 0:
504                 root_freq = get_axi_clk();
505                 break;
506         case 1:
507                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
508                 break;
509         case 2:
510                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
511                 break;
512         case 3:
513                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
514                 break;
515         }
516
517         return root_freq / (emi_slow_podf + 1);
518 }
519
520 static u32 get_nfc_clk(void)
521 {
522         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
523         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
524         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
525         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
526                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
527         u32 root_freq;
528
529         switch (nfc_clk_sel) {
530         case 0:
531                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
532                 break;
533         case 1:
534                 root_freq = decode_pll(PLL_528, MXC_HCLK);
535                 break;
536         case 2:
537                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
538                 break;
539         case 3:
540                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
541                 break;
542         }
543
544         return root_freq / (pred + 1) / (podf + 1);
545 }
546
547 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
548                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
549                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
550
551 static int set_nfc_clk(u32 ref, u32 freq_khz)
552 {
553         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
554         u32 podf;
555         u32 pred;
556         int nfc_clk_sel;
557         u32 root_freq;
558         u32 min_err = ~0;
559         u32 nfc_val = ~0;
560         u32 freq = freq_khz * 1000;
561
562         for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
563                 u32 act_freq;
564                 u32 err;
565
566                 if (ref < 4 && ref != nfc_clk_sel)
567                         continue;
568
569                 switch (nfc_clk_sel) {
570                 case 0:
571                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
572                         break;
573                 case 1:
574                         root_freq = decode_pll(PLL_528, MXC_HCLK);
575                         break;
576                 case 2:
577                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
578                         break;
579                 case 3:
580                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
581                         break;
582                 }
583                 if (root_freq < freq)
584                         continue;
585
586                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
587                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
588                 act_freq = root_freq / pred / podf;
589                 err = (freq - act_freq) * 100 / freq;
590                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
591                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
592                 if (act_freq > freq)
593                         continue;
594                 if (err < min_err) {
595                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
596                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
597                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
598                         min_err = err;
599                         if (err == 0)
600                                 break;
601                 }
602         }
603
604         if (nfc_val == ~0 || min_err > 10)
605                 return -EINVAL;
606
607         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
608                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
609                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
610                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
611                         &imx_ccm->cs2cdr);
612         } else {
613                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
614         }
615         return 0;
616 }
617
618 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
619 static u32 get_mmdc_ch0_clk(void)
620 {
621         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
622         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
623         u32 freq, podf;
624
625         podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
626                         >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
627
628         switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
629                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
630         case 0:
631                 freq = decode_pll(PLL_528, MXC_HCLK);
632                 break;
633         case 1:
634                 freq = mxc_get_pll_pfd(PLL_528, 2);
635                 break;
636         case 2:
637                 freq = mxc_get_pll_pfd(PLL_528, 0);
638                 break;
639         case 3:
640                 /* static / 2 divider */
641                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
642         }
643
644         return freq / (podf + 1);
645
646 }
647 #else
648 static u32 get_mmdc_ch0_clk(void)
649 {
650         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
651         u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
652                                 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
653
654         return get_periph_clk() / (mmdc_ch0_podf + 1);
655 }
656 #endif
657
658 #ifdef CONFIG_SOC_MX6SX
659 /* qspi_num can be from 0 - 1 */
660 void enable_qspi_clk(int qspi_num)
661 {
662         u32 reg = 0;
663         /* Enable QuadSPI clock */
664         switch (qspi_num) {
665         case 0:
666                 /* disable the clock gate */
667                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
668
669                 /* set 50M  : (50 = 396 / 2 / 4) */
670                 reg = readl(&imx_ccm->cscmr1);
671                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
672                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
673                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
674                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
675                 writel(reg, &imx_ccm->cscmr1);
676
677                 /* enable the clock gate */
678                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
679                 break;
680         case 1:
681                 /*
682                  * disable the clock gate
683                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
684                  * disable both of them.
685                  */
686                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
687                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
688
689                 /* set 50M  : (50 = 396 / 2 / 4) */
690                 reg = readl(&imx_ccm->cs2cdr);
691                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
692                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
693                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
694                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
695                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
696                 writel(reg, &imx_ccm->cs2cdr);
697
698                 /*enable the clock gate*/
699                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
700                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
701                 break;
702         default:
703                 break;
704         }
705 }
706 #endif
707
708 #ifdef CONFIG_FEC_MXC
709 int enable_fec_anatop_clock(enum enet_freq freq)
710 {
711         u32 reg = 0;
712         s32 timeout = 100000;
713
714         struct anatop_regs __iomem *anatop =
715                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
716
717         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
718                 return -EINVAL;
719
720         reg = readl(&anatop->pll_enet);
721         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
722         reg |= freq;
723
724         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
725             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
726                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
727                 writel(reg, &anatop->pll_enet);
728                 while (timeout--) {
729                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
730                                 break;
731                 }
732                 if (timeout < 0)
733                         return -ETIMEDOUT;
734         }
735
736         /* Enable FEC clock */
737         reg |= BM_ANADIG_PLL_ENET_ENABLE;
738         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
739         writel(reg, &anatop->pll_enet);
740
741 #ifdef CONFIG_SOC_MX6SX
742         /*
743          * Set enet ahb clock to 200MHz
744          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
745          */
746         reg = readl(&imx_ccm->chsccdr);
747         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
748                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
749                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
750         /* PLL2 PFD2 */
751         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
752         /* Div = 2*/
753         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
754         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
755         writel(reg, &imx_ccm->chsccdr);
756
757         /* Enable enet system clock */
758         reg = readl(&imx_ccm->CCGR3);
759         reg |= MXC_CCM_CCGR3_ENET_MASK;
760         writel(reg, &imx_ccm->CCGR3);
761 #endif
762         return 0;
763 }
764 #endif
765
766 static u32 get_usdhc_clk(u32 port)
767 {
768         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
769         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
770         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
771
772         switch (port) {
773         case 0:
774                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
775                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
776                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
777
778                 break;
779         case 1:
780                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
781                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
782                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
783
784                 break;
785         case 2:
786                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
787                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
788                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
789
790                 break;
791         case 3:
792                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
793                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
794                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
795
796                 break;
797         default:
798                 break;
799         }
800
801         if (clk_sel)
802                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
803         else
804                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
805
806         return root_freq / (usdhc_podf + 1);
807 }
808
809 u32 imx_get_uartclk(void)
810 {
811         return get_uart_clk();
812 }
813
814 u32 imx_get_fecclk(void)
815 {
816         return mxc_get_clock(MXC_IPG_CLK);
817 }
818
819 static int enable_enet_pll(uint32_t en)
820 {
821         u32 reg;
822         s32 timeout = 100000;
823
824         /* Enable PLLs */
825         reg = readl(&anatop->pll_enet);
826         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
827         writel(reg, &anatop->pll_enet);
828         reg |= BM_ANADIG_PLL_ENET_ENABLE;
829         while (timeout--) {
830                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
831                         break;
832         }
833         if (timeout <= 0)
834                 return -EIO;
835         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
836         writel(reg, &anatop->pll_enet);
837         reg |= en;
838         writel(reg, &anatop->pll_enet);
839         return 0;
840 }
841
842 #ifndef CONFIG_SOC_MX6SX
843 static void ungate_sata_clock(void)
844 {
845         struct mxc_ccm_reg *const imx_ccm =
846                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
847
848         /* Enable SATA clock. */
849         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
850 }
851 #endif
852
853 static void ungate_pcie_clock(void)
854 {
855         struct mxc_ccm_reg *const imx_ccm =
856                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
857
858         /* Enable PCIe clock. */
859         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
860 }
861
862 #ifndef CONFIG_SOC_MX6SX
863 int enable_sata_clock(void)
864 {
865         ungate_sata_clock();
866         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
867 }
868
869 void disable_sata_clock(void)
870 {
871         struct mxc_ccm_reg *const imx_ccm =
872                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
873
874         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
875 }
876 #endif
877
878 int enable_pcie_clock(void)
879 {
880         struct anatop_regs *anatop_regs =
881                 (struct anatop_regs *)ANATOP_BASE_ADDR;
882         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
883         u32 lvds1_clk_sel;
884
885         /*
886          * Here be dragons!
887          *
888          * The register ANATOP_MISC1 is not documented in the Freescale
889          * MX6RM. The register that is mapped in the ANATOP space and
890          * marked as ANATOP_MISC1 is actually documented in the PMU section
891          * of the datasheet as PMU_MISC1.
892          *
893          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
894          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
895          * for PCI express link that is clocked from the i.MX6.
896          */
897 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
898 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
899 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
900 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
901 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
902
903         if (is_cpu_type(MXC_CPU_MX6SX))
904                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
905         else
906                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
907
908         clrsetbits_le32(&anatop_regs->ana_misc1,
909                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
910                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
911                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
912
913         /* PCIe reference clock sourced from AXI. */
914         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
915
916         /* Party time! Ungate the clock to the PCIe. */
917 #ifndef CONFIG_SOC_MX6SX
918         ungate_sata_clock();
919 #endif
920         ungate_pcie_clock();
921
922         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
923                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
924 }
925
926 #ifdef CONFIG_SECURE_BOOT
927 void hab_caam_clock_enable(unsigned char enable)
928 {
929         u32 reg;
930
931         /* CG4 ~ CG6, CAAM clocks */
932         reg = __raw_readl(&imx_ccm->CCGR0);
933         if (enable)
934                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
935                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
936                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
937         else
938                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
939                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
940                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
941         __raw_writel(reg, &imx_ccm->CCGR0);
942
943         /* EMI slow clk */
944         reg = __raw_readl(&imx_ccm->CCGR6);
945         if (enable)
946                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
947         else
948                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
949         __raw_writel(reg, &imx_ccm->CCGR6);
950 }
951 #endif
952
953 static void enable_pll3(void)
954 {
955         struct anatop_regs __iomem *anatop =
956                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
957
958         /* make sure pll3 is enabled */
959         if ((readl(&anatop->usb1_pll_480_ctrl) &
960                         BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
961                 /* enable pll's power */
962                 writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
963                        &anatop->usb1_pll_480_ctrl_set);
964                 writel(0x80, &anatop->ana_misc2_clr);
965                 /* wait for pll lock */
966                 while ((readl(&anatop->usb1_pll_480_ctrl) &
967                         BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
968                         ;
969                 /* disable bypass */
970                 writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
971                        &anatop->usb1_pll_480_ctrl_clr);
972                 /* enable pll output */
973                 writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
974                        &anatop->usb1_pll_480_ctrl_set);
975         }
976 }
977
978 void enable_thermal_clk(void)
979 {
980         enable_pll3();
981 }
982
983 void ipu_clk_enable(void)
984 {
985         u32 reg = readl(&imx_ccm->CCGR3);
986         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
987         writel(reg, &imx_ccm->CCGR3);
988 }
989
990 void ipu_clk_disable(void)
991 {
992         u32 reg = readl(&imx_ccm->CCGR3);
993         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
994         writel(reg, &imx_ccm->CCGR3);
995 }
996
997 void ipu_di_clk_enable(int di)
998 {
999         switch (di) {
1000         case 0:
1001                 setbits_le32(&imx_ccm->CCGR3,
1002                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1003                 break;
1004         case 1:
1005                 setbits_le32(&imx_ccm->CCGR3,
1006                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1007                 break;
1008         default:
1009                 printf("%s: Invalid DI index %d\n", __func__, di);
1010         }
1011 }
1012
1013 void ipu_di_clk_disable(int di)
1014 {
1015         switch (di) {
1016         case 0:
1017                 clrbits_le32(&imx_ccm->CCGR3,
1018                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1019                 break;
1020         case 1:
1021                 clrbits_le32(&imx_ccm->CCGR3,
1022                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1023                 break;
1024         default:
1025                 printf("%s: Invalid DI index %d\n", __func__, di);
1026         }
1027 }
1028
1029 void ldb_clk_enable(int ldb)
1030 {
1031         switch (ldb) {
1032         case 0:
1033                 setbits_le32(&imx_ccm->CCGR3,
1034                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1035                 break;
1036         case 1:
1037                 setbits_le32(&imx_ccm->CCGR3,
1038                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1039                 break;
1040         default:
1041                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1042         }
1043 }
1044
1045 void ldb_clk_disable(int ldb)
1046 {
1047         switch (ldb) {
1048         case 0:
1049                 clrbits_le32(&imx_ccm->CCGR3,
1050                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1051                 break;
1052         case 1:
1053                 clrbits_le32(&imx_ccm->CCGR3,
1054                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1055                 break;
1056         default:
1057                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1058         }
1059 }
1060
1061 void ocotp_clk_enable(void)
1062 {
1063         u32 reg = readl(&imx_ccm->CCGR2);
1064         reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1065         writel(reg, &imx_ccm->CCGR2);
1066 }
1067
1068 void ocotp_clk_disable(void)
1069 {
1070         u32 reg = readl(&imx_ccm->CCGR2);
1071         reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1072         writel(reg, &imx_ccm->CCGR2);
1073 }
1074
1075 unsigned int mxc_get_clock(enum mxc_clock clk)
1076 {
1077         switch (clk) {
1078         case MXC_ARM_CLK:
1079                 return get_mcu_main_clk();
1080         case MXC_PER_CLK:
1081                 return get_periph_clk();
1082         case MXC_AHB_CLK:
1083                 return get_ahb_clk();
1084         case MXC_IPG_CLK:
1085                 return get_ipg_clk();
1086         case MXC_IPG_PERCLK:
1087         case MXC_I2C_CLK:
1088                 return get_ipg_per_clk();
1089         case MXC_UART_CLK:
1090                 return get_uart_clk();
1091         case MXC_CSPI_CLK:
1092                 return get_cspi_clk();
1093         case MXC_AXI_CLK:
1094                 return get_axi_clk();
1095         case MXC_EMI_SLOW_CLK:
1096                 return get_emi_slow_clk();
1097         case MXC_DDR_CLK:
1098                 return get_mmdc_ch0_clk();
1099         case MXC_ESDHC_CLK:
1100                 return get_usdhc_clk(0);
1101         case MXC_ESDHC2_CLK:
1102                 return get_usdhc_clk(1);
1103         case MXC_ESDHC3_CLK:
1104                 return get_usdhc_clk(2);
1105         case MXC_ESDHC4_CLK:
1106                 return get_usdhc_clk(3);
1107         case MXC_SATA_CLK:
1108                 return get_ahb_clk();
1109         case MXC_NFC_CLK:
1110                 return get_nfc_clk();
1111         default:
1112                 printf("Unsupported MXC CLK: %d\n", clk);
1113         }
1114
1115         return 0;
1116 }
1117
1118 static inline int gcd(int m, int n)
1119 {
1120         int t;
1121         while (m > 0) {
1122                 if (n > m) {
1123                         t = m;
1124                         m = n;
1125                         n = t;
1126                 } /* swap */
1127                 m -= n;
1128         }
1129         return n;
1130 }
1131
1132 /* Config CPU clock */
1133 static int set_arm_clk(u32 ref, u32 freq_khz)
1134 {
1135         int d;
1136         int div = 0;
1137         int mul = 0;
1138         u32 min_err = ~0;
1139         u32 reg;
1140
1141         if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1142                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1143                         freq_khz / 1000, freq_khz % 1000,
1144                         54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1145                         108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1146                 return -EINVAL;
1147         }
1148
1149         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1150                 int m = freq_khz * 2 * d / (ref / 1000);
1151                 u32 f;
1152                 u32 err;
1153
1154                 if (m > 108) {
1155                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1156                                 d, m);
1157                         break;
1158                 }
1159
1160                 f = ref * m / d / 2;
1161                 if (f > freq_khz * 1000) {
1162                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1163                                 d, m, f, freq_khz);
1164                         if (--m < 54)
1165                                 return -EINVAL;
1166                         f = ref * m / d / 2;
1167                 }
1168                 err = freq_khz * 1000 - f;
1169                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1170                         d, m, f, freq_khz, err);
1171                 if (err < min_err) {
1172                         mul = m;
1173                         div = d;
1174                         min_err = err;
1175                         if (err == 0)
1176                                 break;
1177                 }
1178         }
1179         if (min_err == ~0)
1180                 return -EINVAL;
1181         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1182                 mul, div, freq_khz / 1000, freq_khz % 1000,
1183                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1184
1185         reg = readl(&anatop->pll_arm);
1186         debug("anadig_pll_arm=%08x -> %08x\n",
1187                 reg, (reg & ~0x7f) | mul);
1188
1189         reg |= 1 << 16;
1190         writel(reg, &anatop->pll_arm); /* bypass PLL */
1191
1192         reg = (reg & ~0x7f) | mul;
1193         writel(reg, &anatop->pll_arm);
1194
1195         writel(div - 1, &imx_ccm->cacrr);
1196
1197         reg &= ~(1 << 16);
1198         writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1199
1200         return 0;
1201 }
1202
1203 /*
1204  * This function assumes the expected core clock has to be changed by
1205  * modifying the PLL. This is NOT true always but for most of the times,
1206  * it is. So it assumes the PLL output freq is the same as the expected
1207  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1208  * In the latter case, it will try to increase the presc value until
1209  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1210  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1211  * on the targeted PLL and reference input clock to the PLL. Lastly,
1212  * it sets the register based on these values along with the dividers.
1213  * Note 1) There is no value checking for the passed-in divider values
1214  *         so the caller has to make sure those values are sensible.
1215  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1216  *         exceed NFC_CLK_MAX.
1217  *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
1218  *         177MHz for higher voltage, this function fixes the max to 133MHz.
1219  *      4) This function should not have allowed diag_printf() calls since
1220  *         the serial driver has been stoped. But leave then here to allow
1221  *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1222  */
1223 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1224 {
1225         int ret;
1226
1227         freq *= 1000;
1228
1229         switch (clk) {
1230         case MXC_ARM_CLK:
1231                 ret = set_arm_clk(ref, freq);
1232                 break;
1233
1234         case MXC_NFC_CLK:
1235                 ret = set_nfc_clk(ref, freq);
1236                 break;
1237
1238         default:
1239                 printf("Warning: Unsupported or invalid clock type: %d\n",
1240                         clk);
1241                 return -EINVAL;
1242         }
1243
1244         return ret;
1245 }
1246
1247 /*
1248  * Dump some core clocks.
1249  */
1250 #define print_pll(pll)  {                               \
1251         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1252         printf("%-12s %4d.%03d MHz\n", #pll,            \
1253                 __pll / 1000000, __pll / 1000 % 1000);  \
1254         }
1255
1256 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1257
1258 #define print_clk(clk)  {                               \
1259         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1260         printf("%-12s %4d.%03d MHz\n", #clk,            \
1261                 __clk / 1000000, __clk / 1000 % 1000);  \
1262         }
1263
1264 #define print_pfd(pll, pfd)     {                                       \
1265         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1266         if (__pfd & (0x80 << 8 * pfd)) {                                \
1267                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1268         } else {                                                        \
1269                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1270                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1271                         pll * 18 / __pfd,                               \
1272                         pll * 18 * 1000 / __pfd % 1000);                \
1273         }                                                               \
1274 }
1275
1276 static void do_mx6_showclocks(void)
1277 {
1278         print_pll(PLL_ARM);
1279         print_pll(PLL_528);
1280         print_pll(PLL_USBOTG);
1281         print_pll(PLL_AUDIO);
1282         print_pll(PLL_VIDEO);
1283         print_pll(PLL_ENET);
1284         print_pll(PLL_USB2);
1285         printf("\n");
1286
1287         print_pfd(480, 0);
1288         print_pfd(480, 1);
1289         print_pfd(480, 2);
1290         print_pfd(480, 3);
1291         print_pfd(528, 0);
1292         print_pfd(528, 1);
1293         print_pfd(528, 2);
1294         printf("\n");
1295
1296         print_clk(IPG);
1297         print_clk(UART);
1298         print_clk(CSPI);
1299         print_clk(AHB);
1300         print_clk(AXI);
1301         print_clk(DDR);
1302         print_clk(ESDHC);
1303         print_clk(ESDHC2);
1304         print_clk(ESDHC3);
1305         print_clk(ESDHC4);
1306         print_clk(EMI_SLOW);
1307         print_clk(NFC);
1308         print_clk(IPG_PER);
1309         print_clk(ARM);
1310 }
1311
1312 static struct clk_lookup {
1313         const char *name;
1314         unsigned int index;
1315 } mx6_clk_lookup[] = {
1316         { "arm", MXC_ARM_CLK, },
1317         { "nfc", MXC_NFC_CLK, },
1318 };
1319
1320 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1321 {
1322         int i;
1323         unsigned long freq;
1324         unsigned long ref = ~0UL;
1325
1326         if (argc < 2) {
1327                 do_mx6_showclocks();
1328                 return CMD_RET_SUCCESS;
1329         } else if (argc == 2 || argc > 4) {
1330                 return CMD_RET_USAGE;
1331         }
1332
1333         freq = simple_strtoul(argv[2], NULL, 0);
1334         if (freq == 0) {
1335                 printf("Invalid clock frequency %lu\n", freq);
1336                 return CMD_RET_FAILURE;
1337         }
1338         if (argc > 3) {
1339                 ref = simple_strtoul(argv[3], NULL, 0);
1340         }
1341         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1342                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1343                         switch (mx6_clk_lookup[i].index) {
1344                         case MXC_ARM_CLK:
1345                                 if (argc > 3)
1346                                         return CMD_RET_USAGE;
1347                                 ref = MXC_HCLK;
1348                                 break;
1349
1350                         case MXC_NFC_CLK:
1351                                 if (argc > 3 && ref > 3) {
1352                                         printf("Invalid clock selector value: %lu\n", ref);
1353                                         return CMD_RET_FAILURE;
1354                                 }
1355                                 break;
1356                         }
1357                         printf("Setting %s clock to %lu MHz\n",
1358                                 mx6_clk_lookup[i].name, freq);
1359                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1360                                 break;
1361                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1362                         printf("%s clock set to %lu.%03lu MHz\n",
1363                                 mx6_clk_lookup[i].name,
1364                                 freq / 1000000, freq / 1000 % 1000);
1365                         return CMD_RET_SUCCESS;
1366                 }
1367         }
1368         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1369                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1370                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1371                         printf("\t%s\n", mx6_clk_lookup[i].name);
1372                 }
1373         } else {
1374                 printf("Failed to set clock %s to %s MHz\n",
1375                         argv[1], argv[2]);
1376         }
1377         return CMD_RET_FAILURE;
1378 }
1379
1380 #ifndef CONFIG_SOC_MX6SX
1381 void enable_ipu_clock(void)
1382 {
1383         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1384         int reg;
1385         reg = readl(&mxc_ccm->CCGR3);
1386         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1387         writel(reg, &mxc_ccm->CCGR3);
1388 }
1389 #endif
1390 /***************************************************/
1391
1392 U_BOOT_CMD(
1393         clocks, 4, 0, do_clocks,
1394         "display/set clocks",
1395         "                    - display clock settings\n"
1396         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1397 );