9e76adc8089c2e68a86cb7966dfbf7e14fbc3a19
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / clock.c
1 /*
2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <div64.h>
9 #include <asm/io.h>
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15
16 enum pll_clocks {
17         PLL_ARM,        /* PLL1: ARM PLL */
18         PLL_528,        /* PLL2: System Bus PLL*/
19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
20         PLL_AUDIO,      /* PLL4: Audio PLL */
21         PLL_VIDEO,      /* PLL5: Video PLL */
22         PLL_ENET,       /* PLL6: ENET PLL */
23         PLL_USB2,       /* PLL7: USB2 PLL */
24         PLL_MLB,        /* PLL8: MLB PLL */
25 };
26
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
29
30 int clk_enable(struct clk *clk)
31 {
32         int ret = 0;
33
34         if (!clk)
35                 return 0;
36         if (clk->usecount == 0) {
37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
38                 ret = clk->enable(clk);
39                 if (ret)
40                         return ret;
41                 clk->usecount++;
42         }
43         assert(clk->usecount > 0);
44         return ret;
45 }
46
47 void clk_disable(struct clk *clk)
48 {
49         if (!clk)
50                 return;
51
52         assert(clk->usecount > 0);
53         if (!(--clk->usecount)) {
54                 if (clk->disable) {
55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
56                         clk->disable(clk);
57                 }
58         }
59 }
60
61 int clk_get_usecount(struct clk *clk)
62 {
63         if (clk == NULL)
64                 return 0;
65
66         return clk->usecount;
67 }
68
69 u32 clk_get_rate(struct clk *clk)
70 {
71         if (!clk)
72                 return 0;
73
74         return clk->rate;
75 }
76
77 struct clk *clk_get_parent(struct clk *clk)
78 {
79         if (!clk)
80                 return 0;
81
82         return clk->parent;
83 }
84
85 int clk_set_rate(struct clk *clk, unsigned long rate)
86 {
87         if (clk && clk->set_rate)
88                 clk->set_rate(clk, rate);
89         return clk->rate;
90 }
91
92 long clk_round_rate(struct clk *clk, unsigned long rate)
93 {
94         if (clk == NULL || !clk->round_rate)
95                 return 0;
96
97         return clk->round_rate(clk, rate);
98 }
99
100 int clk_set_parent(struct clk *clk, struct clk *parent)
101 {
102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103                 clk ? clk->parent : NULL);
104
105         if (!clk || clk == parent)
106                 return 0;
107
108         if (clk->set_parent) {
109                 int ret;
110
111                 ret = clk->set_parent(clk, parent);
112                 if (ret)
113                         return ret;
114         }
115         clk->parent = parent;
116         return 0;
117 }
118
119 #define PLL_LOCK_BIT            (1 << 31)
120
121 static inline int wait_pll_lock(u32 *reg)
122 {
123         int loops = 0;
124         u32 val;
125
126         while (!((val = readl(reg)) & PLL_LOCK_BIT)) {
127                 loops++;
128                 if (loops > 1000)
129                         break;
130                 udelay(1);
131         }
132         if (!(val & PLL_LOCK_BIT) && !(readl(reg) & PLL_LOCK_BIT))
133                 return -ETIMEDOUT;
134         return 0;
135 }
136
137 #ifdef CONFIG_MXC_OCOTP
138 void enable_ocotp_clk(unsigned char enable)
139 {
140         u32 reg;
141
142         reg = __raw_readl(&imx_ccm->CCGR2);
143         if (enable)
144                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
145         else
146                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
147         __raw_writel(reg, &imx_ccm->CCGR2);
148 }
149 #endif
150
151 #ifdef CONFIG_NAND_MXS
152 void setup_gpmi_io_clk(u32 cfg)
153 {
154         /* Disable clocks per ERR007177 from MX6 errata */
155         clrbits_le32(&imx_ccm->CCGR4,
156                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
158                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
159                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
160                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
161
162         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
163
164         clrsetbits_le32(&imx_ccm->cs2cdr,
165                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
166                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
167                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
168                         cfg);
169
170         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
171         setbits_le32(&imx_ccm->CCGR4,
172                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
173                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
174                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
175                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
176                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
177 }
178 #endif
179
180 void enable_usboh3_clk(unsigned char enable)
181 {
182         u32 reg;
183
184         reg = __raw_readl(&imx_ccm->CCGR6);
185         if (enable)
186                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
187         else
188                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
189         __raw_writel(reg, &imx_ccm->CCGR6);
190
191 }
192
193 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
194 void enable_enet_clk(unsigned char enable)
195 {
196         u32 mask, *addr;
197
198         if (is_cpu_type(MXC_CPU_MX6UL)) {
199                 mask = MXC_CCM_CCGR3_ENET_MASK;
200                 addr = &imx_ccm->CCGR3;
201         } else {
202                 mask = MXC_CCM_CCGR1_ENET_MASK;
203                 addr = &imx_ccm->CCGR1;
204         }
205
206         if (enable)
207                 setbits_le32(addr, mask);
208         else
209                 clrbits_le32(addr, mask);
210 }
211 #endif
212
213 #ifdef CONFIG_MXC_UART
214 void enable_uart_clk(unsigned char enable)
215 {
216         u32 mask;
217
218         if (is_cpu_type(MXC_CPU_MX6UL))
219                 mask = MXC_CCM_CCGR5_UART_MASK;
220         else
221                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
222
223         if (enable)
224                 setbits_le32(&imx_ccm->CCGR5, mask);
225         else
226                 clrbits_le32(&imx_ccm->CCGR5, mask);
227 }
228 #endif
229
230 #ifdef CONFIG_MMC
231 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
232 {
233         u32 mask;
234
235         if (bus_num > 3)
236                 return -EINVAL;
237
238         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
239         if (enable)
240                 setbits_le32(&imx_ccm->CCGR6, mask);
241         else
242                 clrbits_le32(&imx_ccm->CCGR6, mask);
243
244         return 0;
245 }
246 #endif
247
248 #ifdef CONFIG_SYS_I2C_MXC
249 /* i2c_num can be from 0 - 3 */
250 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
251 {
252         u32 reg;
253         u32 mask;
254         u32 *addr;
255
256         if (i2c_num > 3)
257                 return -EINVAL;
258         if (i2c_num < 3) {
259                 mask = MXC_CCM_CCGR_CG_MASK
260                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
261                         + (i2c_num << 1));
262                 reg = __raw_readl(&imx_ccm->CCGR2);
263                 if (enable)
264                         reg |= mask;
265                 else
266                         reg &= ~mask;
267                 __raw_writel(reg, &imx_ccm->CCGR2);
268         } else {
269                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
270                         mask = MXC_CCM_CCGR6_I2C4_MASK;
271                         addr = &imx_ccm->CCGR6;
272                 } else {
273                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
274                         addr = &imx_ccm->CCGR1;
275                 }
276                 reg = __raw_readl(addr);
277                 if (enable)
278                         reg |= mask;
279                 else
280                         reg &= ~mask;
281                 __raw_writel(reg, addr);
282         }
283         return 0;
284 }
285 #endif
286
287 /* spi_num can be from 0 - SPI_MAX_NUM */
288 int enable_spi_clk(unsigned char enable, unsigned spi_num)
289 {
290         u32 reg;
291         u32 mask;
292
293         if (spi_num > SPI_MAX_NUM)
294                 return -EINVAL;
295
296         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
297         reg = __raw_readl(&imx_ccm->CCGR1);
298         if (enable)
299                 reg |= mask;
300         else
301                 reg &= ~mask;
302         __raw_writel(reg, &imx_ccm->CCGR1);
303         return 0;
304 }
305
306 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
307 {
308         u32 div, post_div;
309         u32 pll_num, pll_denom;
310         u64 freq;
311
312         switch (pll) {
313         case PLL_ARM:
314                 div = __raw_readl(&anatop->pll_arm);
315                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
316                         /* Assume the bypass clock is always derived from OSC */
317                         return infreq;
318                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
319
320                 return infreq * div / 2;
321         case PLL_528:
322                 div = __raw_readl(&anatop->pll_528);
323                 if (div & BM_ANADIG_PLL_528_BYPASS)
324                         return infreq;
325                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
326
327                 return infreq * (20 + div * 2);
328         case PLL_USBOTG:
329                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
330                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
331                         return infreq;
332                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
333
334                 return infreq * (20 + div * 2);
335         case PLL_AUDIO:
336                 div = __raw_readl(&anatop->pll_audio);
337                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
338                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
339                         return infreq;
340
341                 pll_num = __raw_readl(&anatop->pll_audio_num);
342                 pll_denom = __raw_readl(&anatop->pll_audio_denom);
343
344                 post_div = (div & BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT) >>
345                         BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT;
346                 if (post_div == 3) {
347                         printf("Invalid post divider value for PLL_AUDIO\n");
348                         return 0;
349                 }
350                 post_div = 1 << (2 - post_div);
351                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
352
353                 freq = (u64)infreq * pll_num / pll_denom;
354                 freq += infreq * div;
355                 return lldiv(freq, post_div);
356         case PLL_VIDEO:
357                 div = __raw_readl(&anatop->pll_video);
358                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
359                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
360                         return infreq;
361
362                 pll_num = __raw_readl(&anatop->pll_video_num);
363                 pll_denom = __raw_readl(&anatop->pll_video_denom);
364
365                 post_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
366                         BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
367                 if (post_div == 3) {
368                         printf("Invalid post divider value for PLL_VIDEO\n");
369                         return 0;
370                 }
371                 post_div = 1 << (2 - post_div);
372                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
373
374                 freq = (u64)infreq * pll_num / pll_denom;
375                 freq += infreq * div;
376                 return lldiv(freq, post_div);
377         case PLL_ENET:
378                 div = __raw_readl(&anatop->pll_enet);
379                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
380                         return infreq;
381                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
382
383                 return 25000000 * (div + (div >> 1) + 1);
384         case PLL_USB2:
385                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
386                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
387                         return infreq;
388                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
389
390                 return infreq * (20 + div * 2);
391         case PLL_MLB:
392                 div = __raw_readl(&anatop->pll_mlb);
393                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
394                         return infreq;
395                 /* fallthru: unknown external clock provided on MLB_CLK pin */
396         default:
397                 return 0;
398         }
399         /* NOTREACHED */
400 }
401
402 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
403 {
404         u32 div;
405         u64 freq;
406
407         switch (pll) {
408         case PLL_528:
409                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
410                         if (pfd_num == 3) {
411                                 /* No PFD3 on PPL2 */
412                                 return 0;
413                         }
414                 }
415                 div = __raw_readl(&anatop->pfd_528);
416                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
417                 break;
418         case PLL_USBOTG:
419                 div = __raw_readl(&anatop->pfd_480);
420                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
421                 break;
422         default:
423                 /* No PFD on other PLL */
424                 return 0;
425         }
426
427         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
428                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
429 }
430
431 static u32 get_mcu_main_clk(void)
432 {
433         u32 reg, freq;
434
435         reg = __raw_readl(&imx_ccm->cacrr);
436         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
437         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
438         freq = decode_pll(PLL_ARM, MXC_HCLK);
439
440         return freq / (reg + 1);
441 }
442
443 u32 get_periph_clk(void)
444 {
445         u32 reg, div = 0, freq = 0;
446
447         reg = __raw_readl(&imx_ccm->cbcdr);
448         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
449                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
450                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
451                 reg = __raw_readl(&imx_ccm->cbcmr);
452                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
453                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
454
455                 switch (reg) {
456                 case 0:
457                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
458                         break;
459                 case 1:
460                 case 2:
461                         freq = MXC_HCLK;
462                         break;
463                 }
464         } else {
465                 reg = __raw_readl(&imx_ccm->cbcmr);
466                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
467                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
468
469                 switch (reg) {
470                 case 0:
471                         freq = decode_pll(PLL_528, MXC_HCLK);
472                         break;
473                 case 1:
474                         freq = mxc_get_pll_pfd(PLL_528, 2);
475                         break;
476                 case 2:
477                         freq = mxc_get_pll_pfd(PLL_528, 0);
478                         break;
479                 case 3:
480                         /* static / 2 divider */
481                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
482                         break;
483                 }
484         }
485
486         return freq / (div + 1);
487 }
488
489 static u32 get_ipg_clk(void)
490 {
491         u32 reg, ipg_podf;
492
493         reg = __raw_readl(&imx_ccm->cbcdr);
494         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
495         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
496
497         return get_ahb_clk() / (ipg_podf + 1);
498 }
499
500 static u32 get_ipg_per_clk(void)
501 {
502         u32 reg, perclk_podf;
503
504         reg = __raw_readl(&imx_ccm->cscmr1);
505         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
506             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
507                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
508                         return MXC_HCLK; /* OSC 24Mhz */
509         }
510
511         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
512
513         return get_ipg_clk() / (perclk_podf + 1);
514 }
515
516 static u32 get_uart_clk(void)
517 {
518         u32 reg, uart_podf;
519         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
520         reg = __raw_readl(&imx_ccm->cscdr1);
521
522         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
523             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
524                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
525                         freq = MXC_HCLK;
526         }
527
528         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
529         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
530
531         return freq / (uart_podf + 1);
532 }
533
534 static u32 get_cspi_clk(void)
535 {
536         u32 reg, cspi_podf;
537
538         reg = __raw_readl(&imx_ccm->cscdr2);
539         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
540                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
541
542         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
543             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
544                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
545                         return MXC_HCLK / (cspi_podf + 1);
546         }
547
548         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
549 }
550
551 static u32 get_axi_clk(void)
552 {
553         u32 root_freq, axi_podf;
554         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
555
556         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
557         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
558
559         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
560                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
561                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
562                 else
563                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
564         } else {
565                 root_freq = get_periph_clk();
566         }
567         return  root_freq / (axi_podf + 1);
568 }
569
570 static u32 get_emi_slow_clk(void)
571 {
572         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
573
574         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
575         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
576         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
577         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
578         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
579
580         switch (emi_clk_sel) {
581         case 0:
582                 root_freq = get_axi_clk();
583                 break;
584         case 1:
585                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
586                 break;
587         case 2:
588                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
589                 break;
590         case 3:
591                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
592                 break;
593         }
594
595         return root_freq / (emi_slow_podf + 1);
596 }
597
598 static inline unsigned long get_nfc_root_clk(int nfc_clk_sel)
599 {
600         switch (nfc_clk_sel) {
601         case 0:
602                 return mxc_get_pll_pfd(PLL_528, 0);
603                 break;
604         case 1:
605                 return decode_pll(PLL_528, MXC_HCLK);
606                 break;
607         case 2:
608                 return decode_pll(PLL_USBOTG, MXC_HCLK);
609                 break;
610         case 3:
611                 return mxc_get_pll_pfd(PLL_528, 2);
612                 break;
613         case 4:
614                 return mxc_get_pll_pfd(PLL_USBOTG, 3);
615         default:
616                 return 0;
617         }
618 }
619
620 static u32 get_nfc_clk(void)
621 {
622         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
623         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
624                 MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
625         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
626                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
627         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
628                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
629         u32 root_freq = get_nfc_root_clk(nfc_clk_sel);
630
631         return root_freq / (pred + 1) / (podf + 1);
632 }
633
634 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
635                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
636                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
637
638 static int set_nfc_clk(u32 ref, u32 freq_khz)
639 {
640         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
641         u32 podf;
642         u32 pred;
643         int nfc_clk_sel;
644         u32 root_freq;
645         u32 min_err = ~0;
646         u32 nfc_val = ~0;
647         u32 freq = freq_khz * 1000;
648         int num_sel = is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) ? 5 : 4;
649
650         for (nfc_clk_sel = 0; nfc_clk_sel < num_sel; nfc_clk_sel++) {
651                 u32 act_freq;
652                 u32 err;
653
654                 if (ref < num_sel && ref != nfc_clk_sel)
655                         continue;
656
657                 switch (nfc_clk_sel) {
658                 case 0:
659                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
660                         break;
661                 case 1:
662                         root_freq = decode_pll(PLL_528, MXC_HCLK);
663                         break;
664                 case 2:
665                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
666                         break;
667                 case 3:
668                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
669                         break;
670                 case 4:
671                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
672                         break;
673                 }
674                 if (root_freq < freq)
675                         continue;
676
677                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
678                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
679                 act_freq = root_freq / pred / podf;
680                 err = (freq - act_freq) / (freq / 1000);
681                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
682                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
683                 if (act_freq > freq)
684                         continue;
685                 if (err < min_err) {
686                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
687                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
688                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
689                         min_err = err;
690                         if (err == 0)
691                                 break;
692                 }
693         }
694
695         if (nfc_val == ~0 || min_err > 100)
696                 return -EINVAL;
697
698         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
699                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
700                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
701                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
702                         &imx_ccm->cs2cdr);
703         } else {
704                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
705         }
706         return 0;
707 }
708
709 static u32 get_mmdc_ch0_clk(void)
710 {
711         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
712         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
713
714         u32 freq, podf, per2_clk2_podf;
715
716         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
717             is_cpu_type(MXC_CPU_MX6SL)) {
718                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
719                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
720                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
721                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
722                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
723                         if (is_cpu_type(MXC_CPU_MX6SL)) {
724                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
725                                         freq = MXC_HCLK;
726                                 else
727                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
728                         } else {
729                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
730                                         freq = decode_pll(PLL_528, MXC_HCLK);
731                                 else
732                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
733                         }
734                 } else {
735                         per2_clk2_podf = 0;
736                         switch ((cbcmr &
737                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
738                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
739                         case 0:
740                                 freq = decode_pll(PLL_528, MXC_HCLK);
741                                 break;
742                         case 1:
743                                 freq = mxc_get_pll_pfd(PLL_528, 2);
744                                 break;
745                         case 2:
746                                 freq = mxc_get_pll_pfd(PLL_528, 0);
747                                 break;
748                         case 3:
749                                 /* static / 2 divider */
750                                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
751                                 break;
752                         }
753                 }
754                 return freq / (podf + 1) / (per2_clk2_podf + 1);
755         } else {
756                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
757                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
758                 return get_periph_clk() / (podf + 1);
759         }
760 }
761
762 #ifdef CONFIG_FSL_QSPI
763 /* qspi_num can be from 0 - 1 */
764 void enable_qspi_clk(int qspi_num)
765 {
766         u32 reg = 0;
767         /* Enable QuadSPI clock */
768         switch (qspi_num) {
769         case 0:
770                 /* disable the clock gate */
771                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
772
773                 /* set 50M  : (50 = 396 / 2 / 4) */
774                 reg = readl(&imx_ccm->cscmr1);
775                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
776                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
777                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
778                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
779                 writel(reg, &imx_ccm->cscmr1);
780
781                 /* enable the clock gate */
782                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
783                 break;
784         case 1:
785                 /*
786                  * disable the clock gate
787                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
788                  * disable both of them.
789                  */
790                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
791                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
792
793                 /* set 50M  : (50 = 396 / 2 / 4) */
794                 reg = readl(&imx_ccm->cs2cdr);
795                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
796                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
797                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
798                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
799                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
800                 writel(reg, &imx_ccm->cs2cdr);
801
802                 /*enable the clock gate*/
803                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
804                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
805                 break;
806         default:
807                 break;
808         }
809 }
810 #endif
811
812 #ifdef CONFIG_FEC_MXC
813 int enable_fec_anatop_clock(enum enet_freq freq)
814 {
815         u32 reg = 0;
816         s32 timeout = 100000;
817
818         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
819                 return -EINVAL;
820
821         reg = readl(&anatop->pll_enet);
822         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
823         reg |= freq;
824
825         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
826             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
827                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
828                 writel(reg, &anatop->pll_enet);
829                 while (timeout--) {
830                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
831                                 break;
832                 }
833                 if (timeout < 0)
834                         return -ETIMEDOUT;
835         }
836
837         /* Enable FEC clock */
838         reg |= BM_ANADIG_PLL_ENET_ENABLE;
839         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
840         writel(reg, &anatop->pll_enet);
841
842 #ifdef CONFIG_SOC_MX6SX
843         /*
844          * Set enet ahb clock to 200MHz
845          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
846          */
847         reg = readl(&imx_ccm->chsccdr);
848         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
849                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
850                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
851         /* PLL2 PFD2 */
852         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
853         /* Div = 2*/
854         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
855         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
856         writel(reg, &imx_ccm->chsccdr);
857
858         /* Enable enet system clock */
859         reg = readl(&imx_ccm->CCGR3);
860         reg |= MXC_CCM_CCGR3_ENET_MASK;
861         writel(reg, &imx_ccm->CCGR3);
862 #endif
863         return 0;
864 }
865 #endif
866
867 static u32 get_usdhc_clk(u32 port)
868 {
869         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
870         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
871         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
872
873         switch (port) {
874         case 0:
875                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
876                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
877                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
878
879                 break;
880         case 1:
881                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
882                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
883                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
884
885                 break;
886         case 2:
887                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
888                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
889                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
890
891                 break;
892         case 3:
893                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
894                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
895                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
896
897                 break;
898         default:
899                 break;
900         }
901
902         if (clk_sel)
903                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
904         else
905                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
906
907         return root_freq / (usdhc_podf + 1);
908 }
909
910 u32 imx_get_uartclk(void)
911 {
912         return get_uart_clk();
913 }
914
915 u32 imx_get_fecclk(void)
916 {
917         return mxc_get_clock(MXC_IPG_CLK);
918 }
919
920 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
921 static int enable_enet_pll(uint32_t en)
922 {
923         u32 reg;
924         s32 timeout = 100000;
925
926         /* Enable PLLs */
927         reg = readl(&anatop->pll_enet);
928         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
929         writel(reg, &anatop->pll_enet);
930         reg |= BM_ANADIG_PLL_ENET_ENABLE;
931         while (timeout--) {
932                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
933                         break;
934         }
935         if (timeout <= 0)
936                 return -EIO;
937         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
938         writel(reg, &anatop->pll_enet);
939         reg |= en;
940         writel(reg, &anatop->pll_enet);
941         return 0;
942 }
943 #endif
944
945 #ifdef CONFIG_CMD_SATA
946 static void ungate_sata_clock(void)
947 {
948         /* Enable SATA clock. */
949         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
950 }
951
952 int enable_sata_clock(void)
953 {
954         ungate_sata_clock();
955         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
956 }
957
958 void disable_sata_clock(void)
959 {
960         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
961 }
962 #endif
963
964 #ifdef CONFIG_PCIE_IMX
965 static void ungate_pcie_clock(void)
966 {
967         /* Enable PCIe clock. */
968         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
969 }
970
971 int enable_pcie_clock(void)
972 {
973         u32 lvds1_clk_sel;
974
975         /*
976          * Here be dragons!
977          *
978          * The register ANATOP_MISC1 is not documented in the Freescale
979          * MX6RM. The register that is mapped in the ANATOP space and
980          * marked as ANATOP_MISC1 is actually documented in the PMU section
981          * of the datasheet as PMU_MISC1.
982          *
983          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
984          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
985          * for PCI express link that is clocked from the i.MX6.
986          */
987 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
988 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
989 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
990 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
991 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
992
993         if (is_cpu_type(MXC_CPU_MX6SX))
994                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
995         else
996                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
997
998         clrsetbits_le32(&anatop_regs->ana_misc1,
999                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1000                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1001                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1002
1003         /* PCIe reference clock sourced from AXI. */
1004         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1005
1006         /* Party time! Ungate the clock to the PCIe. */
1007 #ifdef CONFIG_CMD_SATA
1008         ungate_sata_clock();
1009 #endif
1010         ungate_pcie_clock();
1011
1012         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1013                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1014 }
1015 #endif
1016
1017 #ifdef CONFIG_SECURE_BOOT
1018 void hab_caam_clock_enable(unsigned char enable)
1019 {
1020         u32 reg;
1021
1022         /* CG4 ~ CG6, CAAM clocks */
1023         reg = __raw_readl(&imx_ccm->CCGR0);
1024         if (enable)
1025                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1026                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1027                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1028         else
1029                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1030                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1031                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1032         __raw_writel(reg, &imx_ccm->CCGR0);
1033
1034         /* EMI slow clk */
1035         reg = __raw_readl(&imx_ccm->CCGR6);
1036         if (enable)
1037                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1038         else
1039                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1040         __raw_writel(reg, &imx_ccm->CCGR6);
1041 }
1042 #endif
1043
1044 static void enable_pll3(void)
1045 {
1046         /* make sure pll3 is enabled */
1047         if ((readl(&anatop->usb1_pll_480_ctrl) &
1048                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1049                 /* enable pll's power */
1050                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1051                        &anatop->usb1_pll_480_ctrl_set);
1052                 writel(0x80, &anatop->ana_misc2_clr);
1053                 /* wait for pll lock */
1054                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1055                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1056                         ;
1057                 /* disable bypass */
1058                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1059                        &anatop->usb1_pll_480_ctrl_clr);
1060                 /* enable pll output */
1061                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1062                        &anatop->usb1_pll_480_ctrl_set);
1063         }
1064 }
1065
1066 void enable_thermal_clk(void)
1067 {
1068         enable_pll3();
1069 }
1070
1071 void ipu_clk_enable(void)
1072 {
1073         u32 reg = readl(&imx_ccm->CCGR3);
1074         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1075         writel(reg, &imx_ccm->CCGR3);
1076 }
1077
1078 void ipu_clk_disable(void)
1079 {
1080         u32 reg = readl(&imx_ccm->CCGR3);
1081         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1082         writel(reg, &imx_ccm->CCGR3);
1083 }
1084
1085 void ipu_di_clk_enable(int di)
1086 {
1087         switch (di) {
1088         case 0:
1089                 setbits_le32(&imx_ccm->CCGR3,
1090                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1091                 break;
1092         case 1:
1093                 setbits_le32(&imx_ccm->CCGR3,
1094                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1095                 break;
1096         default:
1097                 printf("%s: Invalid DI index %d\n", __func__, di);
1098         }
1099 }
1100
1101 void ipu_di_clk_disable(int di)
1102 {
1103         switch (di) {
1104         case 0:
1105                 clrbits_le32(&imx_ccm->CCGR3,
1106                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1107                 break;
1108         case 1:
1109                 clrbits_le32(&imx_ccm->CCGR3,
1110                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1111                 break;
1112         default:
1113                 printf("%s: Invalid DI index %d\n", __func__, di);
1114         }
1115 }
1116
1117 void ldb_clk_enable(int ldb)
1118 {
1119         switch (ldb) {
1120         case 0:
1121                 setbits_le32(&imx_ccm->CCGR3,
1122                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1123                 break;
1124         case 1:
1125                 setbits_le32(&imx_ccm->CCGR3,
1126                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1127                 break;
1128         default:
1129                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1130         }
1131 }
1132
1133 void ldb_clk_disable(int ldb)
1134 {
1135         switch (ldb) {
1136         case 0:
1137                 clrbits_le32(&imx_ccm->CCGR3,
1138                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1139                 break;
1140         case 1:
1141                 clrbits_le32(&imx_ccm->CCGR3,
1142                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1143                 break;
1144         default:
1145                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1146         }
1147 }
1148
1149 #ifdef CONFIG_VIDEO_MXS
1150 void lcdif_clk_enable(void)
1151 {
1152         setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1153         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1154 }
1155
1156 void lcdif_clk_disable(void)
1157 {
1158         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1159         clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1160 }
1161
1162 #define CBCMR_LCDIF_MASK        MXC_CCM_CBCMR_LCDIF_PODF_MASK
1163 #define CSCDR2_LCDIF_MASK       (MXC_CCM_CSCDR2_LCDIF_PRED_MASK |       \
1164                                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK)
1165
1166 static u32 get_lcdif_root_clk(u32 cscdr2)
1167 {
1168         int lcdif_pre_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) >>
1169                 MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET;
1170         int lcdif_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK) >>
1171                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET;
1172         u32 root_freq;
1173
1174         switch (lcdif_clk_sel) {
1175         case 0:
1176                 switch (lcdif_pre_clk_sel) {
1177                 case 0:
1178                         root_freq = decode_pll(PLL_528, MXC_HCLK);
1179                         break;
1180                 case 1:
1181                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
1182                         break;
1183                 case 2:
1184                         root_freq = decode_pll(PLL_VIDEO, MXC_HCLK);
1185                         break;
1186                 case 3:
1187                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
1188                         break;
1189                 case 4:
1190                         root_freq = mxc_get_pll_pfd(PLL_528, 1);
1191                         break;
1192                 case 5:
1193                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
1194                         break;
1195                 default:
1196                         return 0;
1197                 }
1198                 break;
1199         case 1:
1200                 root_freq = mxc_get_pll_pfd(PLL_VIDEO, 0);
1201                 break;
1202         case 2:
1203                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1204                 break;
1205         case 3:
1206                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
1207                 break;
1208         default:
1209                 return 0;
1210         }
1211
1212         return root_freq;
1213 }
1214
1215 static int set_lcdif_pll(u32 ref, u32 freq_khz,
1216                         unsigned post_div)
1217 {
1218         int ret;
1219         u64 freq = freq_khz * 1000;
1220         u32 post_div_mask = 1 << (2 - post_div);
1221         int mul = 1;
1222         u32 min_err = ~0;
1223         u32 reg;
1224         int num = 0;
1225         int denom = 1;
1226         const int min_div = 27;
1227         const int max_div = 54;
1228         const int div_mask = 0x7f;
1229         const u32 max_freq = ref * max_div / post_div;
1230         const u32 min_freq = ref * min_div / post_div;
1231
1232         if (freq > max_freq || freq < min_freq) {
1233                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03uMHz\n",
1234                         freq_khz / 1000, freq_khz % 1000,
1235                         min_freq / 1000000, min_freq / 1000 % 1000,
1236                         max_freq / 1000000, max_freq / 1000 % 1000);
1237                 return -EINVAL;
1238         }
1239         {
1240                 int d = post_div;
1241                 int m = lldiv(freq * d + ref - 1, ref);
1242                 u32 err;
1243                 u32 f;
1244
1245                 debug("%s@%d: d=%d m=%d max_div=%u min_div=%u\n", __func__, __LINE__,
1246                         d, m, max_div, min_div);
1247                 if (m > max_div || m < min_div)
1248                         return -EINVAL;
1249
1250                 f = ref * m / d;
1251                 if (f > freq) {
1252                         debug("%s@%d: d=%d m=%d f=%u freq=%llu\n", __func__, __LINE__,
1253                                 d, m, f, freq);
1254                         return -EINVAL;
1255                 }
1256                 err = freq - f;
1257                 debug("%s@%d: d=%d m=%d f=%u freq=%llu err=%d\n", __func__, __LINE__,
1258                         d, m, f, freq, err);
1259                 if (err < min_err) {
1260                         mul = m;
1261                         min_err = err;
1262                 }
1263         }
1264         if (min_err == ~0) {
1265                 printf("Cannot set VIDEO PLL to %u.%03uMHz\n",
1266                         freq_khz / 1000, freq_khz % 1000);
1267                 return -EINVAL;
1268         }
1269
1270         debug("Setting M=%3u D=%u N=%d DE=%u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1271                 mul, post_div, num, denom,
1272                 freq_khz / post_div / 1000, freq_khz / post_div % 1000,
1273                 ref * mul / post_div / 1000000,
1274                 ref * mul / post_div / 1000 % 1000);
1275
1276         reg = readl(&anatop->pll_video);
1277         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1278
1279         reg = (reg & ~(div_mask |
1280                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)) |
1281                 mul | (post_div_mask << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT);
1282         writel(reg, &anatop->pll_video);
1283
1284         ret = wait_pll_lock(&anatop->pll_video);
1285         if (ret) {
1286                 printf("Video PLL failed to lock\n");
1287                 return ret;
1288         }
1289
1290         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1291         return 0;
1292 }
1293
1294 static int set_lcdif_clk(u32 ref, u32 freq_khz)
1295 {
1296         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1297         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1298         u32 cbcmr_val;
1299         u32 cscdr2_val;
1300         u32 freq = freq_khz * 1000;
1301         u32 act_freq;
1302         u32 err;
1303         u32 min_div = 27;
1304         u32 max_div = 54;
1305         u32 min_pll_khz = ref * min_div / 4 / 1000;
1306         u32 max_pll_khz = ref * max_div / 1000;
1307         u32 pll_khz;
1308         u32 post_div = 0;
1309         u32 m;
1310         u32 min_err = ~0;
1311         u32 best_m = 0;
1312         u32 best_pred = 1;
1313         u32 best_podf = 1;
1314         u32 div;
1315         unsigned pd;
1316
1317         if (freq_khz > max_pll_khz)
1318                 return -EINVAL;
1319
1320         for (pd = 1; min_err && pd <= 4; pd <<= 1) {
1321                 for (m = max(min_div, DIV_ROUND_UP(648000 / pd, freq_khz * 64));
1322                      m <= max_div; m++) {
1323                         u32 err;
1324                         int pred = 0;
1325                         int podf = 0;
1326                         u32 root_freq = ref * m / pd;
1327
1328                         div = DIV_ROUND_UP(root_freq, freq);
1329
1330                         while (pred * podf == 0 && div <= 64) {
1331                                 int p1, p2;
1332
1333                                 for (p1 = 1; p1 <= 8; p1++) {
1334                                         for (p2 = 1; p2 <= 8; p2++) {
1335                                                 if (p1 * p2 == div) {
1336                                                         podf = p1;
1337                                                         pred = p2;
1338                                                         break;
1339                                                 }
1340                                         }
1341                                 }
1342                                 if (pred * podf == 0) {
1343                                         div++;
1344                                 }
1345                         }
1346                         if (pred * podf == 0)
1347                                 continue;
1348
1349                         /* relative error in per mille */
1350                         act_freq = root_freq / div;
1351                         err = abs(act_freq - freq) / freq_khz;
1352
1353                         if (err < min_err) {
1354                                 best_m = m;
1355                                 best_pred = pred;
1356                                 best_podf = podf;
1357                                 post_div = pd;
1358                                 min_err = err;
1359                                 if (err <= 10)
1360                                         break;
1361                         }
1362                 }
1363         }
1364         if (min_err > 50)
1365                 return -EINVAL;
1366
1367         pll_khz = ref / 1000 * best_m;
1368         if (pll_khz > max_pll_khz)
1369                 return -EINVAL;
1370
1371         if (pll_khz < min_pll_khz)
1372                 return -EINVAL;
1373
1374         err = set_lcdif_pll(ref, pll_khz / post_div, post_div);
1375         if (err)
1376                 return err;
1377
1378         cbcmr_val = (best_podf - 1) << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET;
1379         cscdr2_val = (best_pred - 1) << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET;
1380
1381         if ((cbcmr & CBCMR_LCDIF_MASK) != cbcmr_val) {
1382                 debug("changing cbcmr from %08x to %08x\n", cbcmr,
1383                         (cbcmr & ~CBCMR_LCDIF_MASK) | cbcmr_val);
1384                 clrsetbits_le32(&imx_ccm->cbcmr,
1385                                 CBCMR_LCDIF_MASK,
1386                                 cbcmr_val);
1387         } else {
1388                 debug("Leaving cbcmr unchanged [%08x]\n", cbcmr);
1389         }
1390         if ((cscdr2 & CSCDR2_LCDIF_MASK) != cscdr2_val) {
1391                 debug("changing cscdr2 from %08x to %08x\n", cscdr2,
1392                         (cscdr2 & ~CSCDR2_LCDIF_MASK) | cscdr2_val);
1393                 clrsetbits_le32(&imx_ccm->cscdr2,
1394                                 CSCDR2_LCDIF_MASK,
1395                                 cscdr2_val);
1396         } else {
1397                 debug("Leaving cscdr2 unchanged [%08x]\n", cscdr2);
1398         }
1399         return 0;
1400 }
1401
1402 void mxs_set_lcdclk(u32 khz)
1403 {
1404         set_lcdif_clk(CONFIG_SYS_MX6_HCLK, khz);
1405 }
1406
1407 static u32 get_lcdif_clk(void)
1408 {
1409         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1410         u32 podf = ((cbcmr & MXC_CCM_CBCMR_LCDIF_PODF_MASK) >>
1411                 MXC_CCM_CBCMR_LCDIF_PODF_OFFSET) + 1;
1412         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1413         u32 pred = ((cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRED_MASK) >>
1414                 MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET) + 1;
1415         u32 root_freq = get_lcdif_root_clk(cscdr2);
1416
1417         return root_freq / pred / podf;
1418 }
1419 #endif
1420
1421 unsigned int mxc_get_clock(enum mxc_clock clk)
1422 {
1423         switch (clk) {
1424         case MXC_ARM_CLK:
1425                 return get_mcu_main_clk();
1426         case MXC_PER_CLK:
1427                 return get_periph_clk();
1428         case MXC_AHB_CLK:
1429                 return get_ahb_clk();
1430         case MXC_IPG_CLK:
1431                 return get_ipg_clk();
1432         case MXC_IPG_PERCLK:
1433         case MXC_I2C_CLK:
1434                 return get_ipg_per_clk();
1435         case MXC_UART_CLK:
1436                 return get_uart_clk();
1437         case MXC_CSPI_CLK:
1438                 return get_cspi_clk();
1439         case MXC_AXI_CLK:
1440                 return get_axi_clk();
1441         case MXC_EMI_SLOW_CLK:
1442                 return get_emi_slow_clk();
1443         case MXC_DDR_CLK:
1444                 return get_mmdc_ch0_clk();
1445         case MXC_ESDHC_CLK:
1446                 return get_usdhc_clk(0);
1447         case MXC_ESDHC2_CLK:
1448                 return get_usdhc_clk(1);
1449         case MXC_ESDHC3_CLK:
1450                 return get_usdhc_clk(2);
1451         case MXC_ESDHC4_CLK:
1452                 return get_usdhc_clk(3);
1453         case MXC_SATA_CLK:
1454                 return get_ahb_clk();
1455         case MXC_NFC_CLK:
1456                 return get_nfc_clk();
1457 #ifdef CONFIG_VIDEO_MXS
1458         case MXC_LCDIF_CLK:
1459                 return get_lcdif_clk();
1460 #endif
1461         default:
1462                 printf("Unsupported MXC CLK: %d\n", clk);
1463         }
1464
1465         return 0;
1466 }
1467
1468 /* Config CPU clock */
1469 static int set_arm_clk(u32 ref, u32 freq_khz)
1470 {
1471         int ret;
1472         int d;
1473         int div = 0;
1474         int mul = 0;
1475         u32 min_err = ~0;
1476         u32 reg;
1477         const int min_div = 54;
1478         const int max_div = 108;
1479         const int div_mask = 0x7f;
1480         const u32 max_freq = ref * max_div / 2;
1481         const u32 min_freq = ref * min_div / 8 / 2;
1482
1483         if (freq_khz > max_freq / 1000 || freq_khz < min_freq / 1000) {
1484                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1485                         freq_khz / 1000, freq_khz % 1000,
1486                         min_freq / 1000000, min_freq / 1000 % 1000,
1487                         max_freq / 1000000, max_freq / 1000 % 1000);
1488                 return -EINVAL;
1489         }
1490
1491         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1492                 int m = freq_khz * 2 * d / (ref / 1000);
1493                 u32 f;
1494                 u32 err;
1495
1496                 if (m > max_div) {
1497                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1498                                 d, m);
1499                         break;
1500                 }
1501
1502                 f = ref * m / d / 2;
1503                 if (f > freq_khz * 1000) {
1504                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1505                                 d, m, f, freq_khz);
1506                         if (--m < min_div)
1507                                 return -EINVAL;
1508                         f = ref * m / d / 2;
1509                 }
1510                 err = freq_khz * 1000 - f;
1511                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1512                         d, m, f, freq_khz, err);
1513                 if (err < min_err) {
1514                         mul = m;
1515                         div = d;
1516                         min_err = err;
1517                         if (err == 0)
1518                                 break;
1519                 }
1520         }
1521         if (min_err == ~0)
1522                 return -EINVAL;
1523         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1524                 mul, div, freq_khz / 1000, freq_khz % 1000,
1525                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1526
1527         reg = readl(&anatop->pll_arm);
1528         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1529
1530         reg = (reg & ~div_mask) | mul;
1531         writel(reg, &anatop->pll_arm);
1532
1533         writel(div - 1, &imx_ccm->cacrr);
1534
1535         ret = wait_pll_lock(&anatop->pll_video);
1536         if (ret) {
1537                 printf("ARM PLL failed to lock\n");
1538                 return ret;
1539         }
1540
1541         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1542
1543         return 0;
1544 }
1545
1546 /*
1547  * This function assumes the expected core clock has to be changed by
1548  * modifying the PLL. This is NOT true always but for most of the times,
1549  * it is. So it assumes the PLL output freq is the same as the expected
1550  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1551  * In the latter case, it will try to increase the presc value until
1552  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1553  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1554  * on the targeted PLL and reference input clock to the PLL. Lastly,
1555  * it sets the register based on these values along with the dividers.
1556  * Note 1) There is no value checking for the passed-in divider values
1557  *         so the caller has to make sure those values are sensible.
1558  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1559  *         exceed NFC_CLK_MAX.
1560  */
1561 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1562 {
1563         int ret;
1564
1565         freq *= 1000;
1566
1567         switch (clk) {
1568         case MXC_ARM_CLK:
1569                 ret = set_arm_clk(ref, freq);
1570                 break;
1571
1572         case MXC_NFC_CLK:
1573                 ret = set_nfc_clk(ref, freq);
1574                 break;
1575
1576         default:
1577                 printf("Warning: Unsupported or invalid clock type: %d\n",
1578                         clk);
1579                 return -EINVAL;
1580         }
1581
1582         return ret;
1583 }
1584
1585 /*
1586  * Dump some core clocks.
1587  */
1588 #define print_pll(pll)  {                               \
1589         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1590         printf("%-12s %4d.%03d MHz\n", #pll,            \
1591                 __pll / 1000000, __pll / 1000 % 1000);  \
1592         }
1593
1594 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1595
1596 #define print_clk(clk)  {                               \
1597         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1598         printf("%-12s %4d.%03d MHz\n", #clk,            \
1599                 __clk / 1000000, __clk / 1000 % 1000);  \
1600         }
1601
1602 #define print_pfd(pll, pfd)     {                                       \
1603         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1604         if (__pfd & (0x80 << 8 * pfd)) {                                \
1605                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1606         } else {                                                        \
1607                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1608                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1609                         pll * 18 / __pfd,                               \
1610                         pll * 18 * 1000 / __pfd % 1000);                \
1611         }                                                               \
1612 }
1613
1614 static void do_mx6_showclocks(void)
1615 {
1616         print_pll(PLL_ARM);
1617         print_pll(PLL_528);
1618         print_pll(PLL_USBOTG);
1619         print_pll(PLL_AUDIO);
1620         print_pll(PLL_VIDEO);
1621         print_pll(PLL_ENET);
1622         print_pll(PLL_USB2);
1623         printf("\n");
1624
1625         print_pfd(480, 0);
1626         print_pfd(480, 1);
1627         print_pfd(480, 2);
1628         print_pfd(480, 3);
1629         print_pfd(528, 0);
1630         print_pfd(528, 1);
1631         print_pfd(528, 2);
1632         printf("\n");
1633
1634         print_clk(IPG);
1635         print_clk(UART);
1636         print_clk(CSPI);
1637         print_clk(AHB);
1638         print_clk(AXI);
1639         print_clk(DDR);
1640         print_clk(ESDHC);
1641         print_clk(ESDHC2);
1642         print_clk(ESDHC3);
1643         print_clk(ESDHC4);
1644         print_clk(EMI_SLOW);
1645         print_clk(NFC);
1646         print_clk(IPG_PER);
1647         print_clk(ARM);
1648 #ifdef CONFIG_VIDEO_MXS
1649         print_clk(LCDIF);
1650 #endif
1651 }
1652
1653 static struct clk_lookup {
1654         const char *name;
1655         unsigned int index;
1656 } mx6_clk_lookup[] = {
1657         { "arm", MXC_ARM_CLK, },
1658         { "nfc", MXC_NFC_CLK, },
1659 };
1660
1661 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1662 {
1663         int i;
1664         unsigned long freq;
1665         unsigned long ref = ~0UL;
1666
1667         if (argc < 2) {
1668                 do_mx6_showclocks();
1669                 return CMD_RET_SUCCESS;
1670         } else if (argc == 2 || argc > 4) {
1671                 return CMD_RET_USAGE;
1672         }
1673
1674         freq = simple_strtoul(argv[2], NULL, 0);
1675         if (freq == 0) {
1676                 printf("Invalid clock frequency %lu\n", freq);
1677                 return CMD_RET_FAILURE;
1678         }
1679         if (argc > 3) {
1680                 ref = simple_strtoul(argv[3], NULL, 0);
1681         }
1682         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1683                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1684                         switch (mx6_clk_lookup[i].index) {
1685                         case MXC_ARM_CLK:
1686                                 if (argc > 3)
1687                                         return CMD_RET_USAGE;
1688                                 ref = MXC_HCLK;
1689                                 break;
1690
1691                         case MXC_NFC_CLK:
1692                                 if (argc > 3 && ref > 3) {
1693                                         printf("Invalid clock selector value: %lu\n", ref);
1694                                         return CMD_RET_FAILURE;
1695                                 }
1696                                 break;
1697                         }
1698                         printf("Setting %s clock to %lu MHz\n",
1699                                 mx6_clk_lookup[i].name, freq);
1700                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1701                                 break;
1702                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1703                         printf("%s clock set to %lu.%03lu MHz\n",
1704                                 mx6_clk_lookup[i].name,
1705                                 freq / 1000000, freq / 1000 % 1000);
1706                         return CMD_RET_SUCCESS;
1707                 }
1708         }
1709         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1710                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1711                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1712                         printf("\t%s\n", mx6_clk_lookup[i].name);
1713                 }
1714         } else {
1715                 printf("Failed to set clock %s to %s MHz\n",
1716                         argv[1], argv[2]);
1717         }
1718         return CMD_RET_FAILURE;
1719 }
1720
1721 #ifndef CONFIG_SOC_MX6SX
1722 void enable_ipu_clock(void)
1723 {
1724         int reg = readl(&imx_ccm->CCGR3);
1725         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1726         writel(reg, &imx_ccm->CCGR3);
1727
1728         if (is_mx6dqp()) {
1729                 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1730                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1731         }
1732 }
1733 #endif
1734 /***************************************************/
1735
1736 U_BOOT_CMD(
1737         clocks, 4, 0, do_clocks,
1738         "display/set clocks",
1739         "                    - display clock settings\n"
1740         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1741 );