arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_ARM,        /* PLL1: ARM PLL */
  18         PLL_528,        /* PLL2: System Bus PLL*/
  19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
  20         PLL_AUDIO,      /* PLL4: Audio PLL */
  21         PLL_VIDEO,      /* PLL5: Video PLL */
  22         PLL_ENET,       /* PLL6: ENET PLL */
  23         PLL_USB2,       /* PLL7: USB2 PLL */
  24         PLL_MLB,        /* PLL8: MLB PLL */
  25 };
  26
  27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
  28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
  29
  30 int clk_enable(struct clk *clk)
  31 {
  32         int ret = 0;
  33
  34         if (!clk)
  35                 return 0;
  36         if (clk->usecount == 0) {
  37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
  38                 ret = clk->enable(clk);
  39                 if (ret)
  40                         return ret;
  41                 clk->usecount++;
  42         }
  43         assert(clk->usecount > 0);
  44         return ret;
  45 }
  46
  47 void clk_disable(struct clk *clk)
  48 {
  49         if (!clk)
  50                 return;
  51
  52         assert(clk->usecount > 0);
  53         if (!(--clk->usecount)) {
  54                 if (clk->disable) {
  55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
  56                         clk->disable(clk);
  57                 }
  58         }
  59 }
  60
  61 int clk_get_usecount(struct clk *clk)
  62 {
  63         if (clk == NULL)
  64                 return 0;
  65
  66         return clk->usecount;
  67 }
  68
  69 u32 clk_get_rate(struct clk *clk)
  70 {
  71         if (!clk)
  72                 return 0;
  73
  74         return clk->rate;
  75 }
  76
  77 struct clk *clk_get_parent(struct clk *clk)
  78 {
  79         if (!clk)
  80                 return 0;
  81
  82         return clk->parent;
  83 }
  84
  85 int clk_set_rate(struct clk *clk, unsigned long rate)
  86 {
  87         if (clk && clk->set_rate)
  88                 clk->set_rate(clk, rate);
  89         return clk->rate;
  90 }
  91
  92 long clk_round_rate(struct clk *clk, unsigned long rate)
  93 {
  94         if (clk == NULL || !clk->round_rate)
  95                 return 0;
  96
  97         return clk->round_rate(clk, rate);
  98 }
  99
 100 int clk_set_parent(struct clk *clk, struct clk *parent)
 101 {
 102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
 103                 clk ? clk->parent : NULL);
 104
 105         if (!clk || clk == parent)
 106                 return 0;
 107
 108         if (clk->set_parent) {
 109                 int ret;
 110
 111                 ret = clk->set_parent(clk, parent);
 112                 if (ret)
 113                         return ret;
 114         }
 115         clk->parent = parent;
 116         return 0;
 117 }
 118
 119 #define PLL_LOCK_BIT            (1 << 31)
 120
 121 static inline int wait_pll_lock(u32 *reg)
 122 {
 123         int loops = 0;
 124         u32 val;
 125
 126         while (!((val = readl(reg)) & PLL_LOCK_BIT)) {
 127                 loops++;
 128                 if (loops > 1000)
 129                         break;
 130                 udelay(1);
 131         }
 132         if (!(val & PLL_LOCK_BIT) && !(readl(reg) & PLL_LOCK_BIT))
 133                 return -ETIMEDOUT;
 134         return 0;
 135 }
 136
 137 #ifdef CONFIG_MXC_OCOTP
 138 void enable_ocotp_clk(unsigned char enable)
 139 {
 140         u32 reg;
 141
 142         reg = __raw_readl(&imx_ccm->CCGR2);
 143         if (enable)
 144                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 145         else
 146                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 147         __raw_writel(reg, &imx_ccm->CCGR2);
 148 }
 149 #endif
 150
 151 #ifdef CONFIG_NAND_MXS
 152 void setup_gpmi_io_clk(u32 cfg)
 153 {
 154         /* Disable clocks per ERR007177 from MX6 errata */
 155         clrbits_le32(&imx_ccm->CCGR4,
 156                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 158                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 159                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 160                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 161
 162         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 163
 164         clrsetbits_le32(&imx_ccm->cs2cdr,
 165                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 166                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 167                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 168                         cfg);
 169
 170         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 171         setbits_le32(&imx_ccm->CCGR4,
 172                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 173                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 174                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 175                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 176                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 177 }
 178 #endif
 179
 180 void enable_usboh3_clk(unsigned char enable)
 181 {
 182         u32 reg;
 183
 184         reg = __raw_readl(&imx_ccm->CCGR6);
 185         if (enable)
 186                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
 187         else
 188                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
 189         __raw_writel(reg, &imx_ccm->CCGR6);
 190
 191 }
 192
 193 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 194 void enable_enet_clk(unsigned char enable)
 195 {
 196         u32 mask, *addr;
 197
 198         if (is_cpu_type(MXC_CPU_MX6UL)) {
 199                 mask = MXC_CCM_CCGR3_ENET_MASK;
 200                 addr = &imx_ccm->CCGR3;
 201         } else {
 202                 mask = MXC_CCM_CCGR1_ENET_MASK;
 203                 addr = &imx_ccm->CCGR1;
 204         }
 205
 206         if (enable)
 207                 setbits_le32(addr, mask);
 208         else
 209                 clrbits_le32(addr, mask);
 210 }
 211 #endif
 212
 213 #ifdef CONFIG_MXC_UART
 214 void enable_uart_clk(unsigned char enable)
 215 {
 216         u32 mask;
 217
 218         if (is_cpu_type(MXC_CPU_MX6UL))
 219                 mask = MXC_CCM_CCGR5_UART_MASK;
 220         else
 221                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 222
 223         if (enable)
 224                 setbits_le32(&imx_ccm->CCGR5, mask);
 225         else
 226                 clrbits_le32(&imx_ccm->CCGR5, mask);
 227 }
 228 #endif
 229
 230 #ifdef CONFIG_MMC
 231 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 232 {
 233         u32 mask;
 234
 235         if (bus_num > 3)
 236                 return -EINVAL;
 237
 238         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 239         if (enable)
 240                 setbits_le32(&imx_ccm->CCGR6, mask);
 241         else
 242                 clrbits_le32(&imx_ccm->CCGR6, mask);
 243
 244         return 0;
 245 }
 246 #endif
 247
 248 #ifdef CONFIG_SYS_I2C_MXC
 249 /* i2c_num can be from 0 - 3 */
 250 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 251 {
 252         u32 reg;
 253         u32 mask;
 254         u32 *addr;
 255
 256         if (i2c_num > 3)
 257                 return -EINVAL;
 258         if (i2c_num < 3) {
 259                 mask = MXC_CCM_CCGR_CG_MASK
 260                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 261                         + (i2c_num << 1));
 262                 reg = __raw_readl(&imx_ccm->CCGR2);
 263                 if (enable)
 264                         reg |= mask;
 265                 else
 266                         reg &= ~mask;
 267                 __raw_writel(reg, &imx_ccm->CCGR2);
 268         } else {
 269                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 270                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 271                         addr = &imx_ccm->CCGR6;
 272                 } else {
 273                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 274                         addr = &imx_ccm->CCGR1;
 275                 }
 276                 reg = __raw_readl(addr);
 277                 if (enable)
 278                         reg |= mask;
 279                 else
 280                         reg &= ~mask;
 281                 __raw_writel(reg, addr);
 282         }
 283         return 0;
 284 }
 285 #endif
 286
 287 /* spi_num can be from 0 - SPI_MAX_NUM */
 288 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 289 {
 290         u32 reg;
 291         u32 mask;
 292
 293         if (spi_num > SPI_MAX_NUM)
 294                 return -EINVAL;
 295
 296         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 297         reg = __raw_readl(&imx_ccm->CCGR1);
 298         if (enable)
 299                 reg |= mask;
 300         else
 301                 reg &= ~mask;
 302         __raw_writel(reg, &imx_ccm->CCGR1);
 303         return 0;
 304 }
 305
 306 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 307 {
 308         u32 div, post_div;
 309         u32 pll_num, pll_denom;
 310         u64 freq;
 311
 312         switch (pll) {
 313         case PLL_ARM:
 314                 div = __raw_readl(&anatop->pll_arm);
 315                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
 316                         /* Assume the bypass clock is always derived from OSC */
 317                         return infreq;
 318                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
 319
 320                 return infreq * div / 2;
 321         case PLL_528:
 322                 div = __raw_readl(&anatop->pll_528);
 323                 if (div & BM_ANADIG_PLL_528_BYPASS)
 324                         return infreq;
 325                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 326
 327                 return infreq * (20 + div * 2);
 328         case PLL_USBOTG:
 329                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
 330                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 331                         return infreq;
 332                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 333
 334                 return infreq * (20 + div * 2);
 335         case PLL_AUDIO:
 336                 div = __raw_readl(&anatop->pll_audio);
 337                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 338                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 339                         return infreq;
 340
 341                 pll_num = __raw_readl(&anatop->pll_audio_num);
 342                 pll_denom = __raw_readl(&anatop->pll_audio_denom);
 343
 344                 post_div = (div & BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT) >>
 345                         BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT;
 346                 if (post_div == 3) {
 347                         printf("Invalid post divider value for PLL_AUDIO\n");
 348                         return 0;
 349                 }
 350                 post_div = 1 << (2 - post_div);
 351                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 352
 353                 freq = (u64)infreq * pll_num / pll_denom;
 354                 freq += infreq * div;
 355                 return lldiv(freq, post_div);
 356         case PLL_VIDEO:
 357                 div = __raw_readl(&anatop->pll_video);
 358                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 359                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 360                         return infreq;
 361
 362                 pll_num = __raw_readl(&anatop->pll_video_num);
 363                 pll_denom = __raw_readl(&anatop->pll_video_denom);
 364
 365                 post_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
 366                         BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 367                 if (post_div == 3) {
 368                         printf("Invalid post divider value for PLL_VIDEO\n");
 369                         return 0;
 370                 }
 371                 post_div = 1 << (2 - post_div);
 372                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 373
 374                 freq = (u64)infreq * pll_num / pll_denom;
 375                 freq += infreq * div;
 376                 return lldiv(freq, post_div);
 377         case PLL_ENET:
 378                 div = __raw_readl(&anatop->pll_enet);
 379                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
 380                         return infreq;
 381                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 382
 383                 return 25000000 * (div + (div >> 1) + 1);
 384         case PLL_USB2:
 385                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
 386                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 387                         return infreq;
 388                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 389
 390                 return infreq * (20 + div * 2);
 391         case PLL_MLB:
 392                 div = __raw_readl(&anatop->pll_mlb);
 393                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
 394                         return infreq;
 395                 /* fallthru: unknown external clock provided on MLB_CLK pin */
 396         default:
 397                 return 0;
 398         }
 399         /* NOTREACHED */
 400 }
 401
 402 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 403 {
 404         u32 div;
 405         u64 freq;
 406
 407         switch (pll) {
 408         case PLL_528:
 409                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
 410                         if (pfd_num == 3) {
 411                                 /* No PFD3 on PPL2 */
 412                                 return 0;
 413                         }
 414                 }
 415                 div = __raw_readl(&anatop->pfd_528);
 416                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
 417                 break;
 418         case PLL_USBOTG:
 419                 div = __raw_readl(&anatop->pfd_480);
 420                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 421                 break;
 422         default:
 423                 /* No PFD on other PLL */
 424                 return 0;
 425         }
 426
 427         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 428                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 429 }
 430
 431 static u32 get_mcu_main_clk(void)
 432 {
 433         u32 reg, freq;
 434
 435         reg = __raw_readl(&imx_ccm->cacrr);
 436         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 437         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 438         freq = decode_pll(PLL_ARM, MXC_HCLK);
 439
 440         return freq / (reg + 1);
 441 }
 442
 443 u32 get_periph_clk(void)
 444 {
 445         u32 reg, div = 0, freq = 0;
 446
 447         reg = __raw_readl(&imx_ccm->cbcdr);
 448         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 449                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 450                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 451                 reg = __raw_readl(&imx_ccm->cbcmr);
 452                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 453                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 454
 455                 switch (reg) {
 456                 case 0:
 457                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 458                         break;
 459                 case 1:
 460                 case 2:
 461                         freq = MXC_HCLK;
 462                         break;
 463                 }
 464         } else {
 465                 reg = __raw_readl(&imx_ccm->cbcmr);
 466                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 467                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 468
 469                 switch (reg) {
 470                 case 0:
 471                         freq = decode_pll(PLL_528, MXC_HCLK);
 472                         break;
 473                 case 1:
 474                         freq = mxc_get_pll_pfd(PLL_528, 2);
 475                         break;
 476                 case 2:
 477                         freq = mxc_get_pll_pfd(PLL_528, 0);
 478                         break;
 479                 case 3:
 480                         /* static / 2 divider */
 481                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
 482                         break;
 483                 }
 484         }
 485
 486         return freq / (div + 1);
 487 }
 488
 489 static u32 get_ipg_clk(void)
 490 {
 491         u32 reg, ipg_podf;
 492
 493         reg = __raw_readl(&imx_ccm->cbcdr);
 494         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 495         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 496
 497         return get_ahb_clk() / (ipg_podf + 1);
 498 }
 499
 500 static u32 get_ipg_per_clk(void)
 501 {
 502         u32 reg, perclk_podf;
 503
 504         reg = __raw_readl(&imx_ccm->cscmr1);
 505         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 506             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 507                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 508                         return MXC_HCLK; /* OSC 24Mhz */
 509         }
 510
 511         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 512
 513         return get_ipg_clk() / (perclk_podf + 1);
 514 }
 515
 516 static u32 get_uart_clk(void)
 517 {
 518         u32 reg, uart_podf;
 519         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 520         reg = __raw_readl(&imx_ccm->cscdr1);
 521
 522         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 523             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 524                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 525                         freq = MXC_HCLK;
 526         }
 527
 528         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 529         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 530
 531         return freq / (uart_podf + 1);
 532 }
 533
 534 static u32 get_cspi_clk(void)
 535 {
 536         u32 reg, cspi_podf;
 537
 538         reg = __raw_readl(&imx_ccm->cscdr2);
 539         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 540                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 541
 542         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
 543             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 544                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 545                         return MXC_HCLK / (cspi_podf + 1);
 546         }
 547
 548         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 549 }
 550
 551 static u32 get_axi_clk(void)
 552 {
 553         u32 root_freq, axi_podf;
 554         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 555
 556         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 557         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 558
 559         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 560                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 561                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 562                 else
 563                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 564         } else {
 565                 root_freq = get_periph_clk();
 566         }
 567         return  root_freq / (axi_podf + 1);
 568 }
 569
 570 static u32 get_emi_slow_clk(void)
 571 {
 572         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 573
 574         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 575         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 576         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 577         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 578         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 579
 580         switch (emi_clk_sel) {
 581         case 0:
 582                 root_freq = get_axi_clk();
 583                 break;
 584         case 1:
 585                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 586                 break;
 587         case 2:
 588                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
 589                 break;
 590         case 3:
 591                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
 592                 break;
 593         }
 594
 595         return root_freq / (emi_slow_podf + 1);
 596 }
 597
 598 static inline unsigned long get_nfc_root_clk(int nfc_clk_sel)
 599 {
 600         switch (nfc_clk_sel) {
 601         case 0:
 602                 return mxc_get_pll_pfd(PLL_528, 0);
 603                 break;
 604         case 1:
 605                 return decode_pll(PLL_528, MXC_HCLK);
 606                 break;
 607         case 2:
 608                 return decode_pll(PLL_USBOTG, MXC_HCLK);
 609                 break;
 610         case 3:
 611                 return mxc_get_pll_pfd(PLL_528, 2);
 612                 break;
 613         case 4:
 614                 return mxc_get_pll_pfd(PLL_USBOTG, 3);
 615         default:
 616                 return 0;
 617         }
 618 }
 619
 620 static u32 get_nfc_clk(void)
 621 {
 622         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 623         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
 624                 MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 625         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
 626                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 627         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
 628                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 629         u32 root_freq = get_nfc_root_clk(nfc_clk_sel);
 630
 631         return root_freq / (pred + 1) / (podf + 1);
 632 }
 633
 634 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
 635                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
 636                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
 637
 638 static int set_nfc_clk(u32 ref, u32 freq_khz)
 639 {
 640         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 641         u32 podf;
 642         u32 pred;
 643         int nfc_clk_sel;
 644         u32 root_freq;
 645         u32 min_err = ~0;
 646         u32 nfc_val = ~0;
 647         u32 freq = freq_khz * 1000;
 648         int num_sel = is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) ? 5 : 4;
 649
 650         for (nfc_clk_sel = 0; nfc_clk_sel < num_sel; nfc_clk_sel++) {
 651                 u32 act_freq;
 652                 u32 err;
 653
 654                 if (ref < num_sel && ref != nfc_clk_sel)
 655                         continue;
 656
 657                 switch (nfc_clk_sel) {
 658                 case 0:
 659                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
 660                         break;
 661                 case 1:
 662                         root_freq = decode_pll(PLL_528, MXC_HCLK);
 663                         break;
 664                 case 2:
 665                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 666                         break;
 667                 case 3:
 668                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 669                         break;
 670                 case 4:
 671                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
 672                         break;
 673                 }
 674                 if (root_freq < freq)
 675                         continue;
 676
 677                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
 678                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
 679                 act_freq = root_freq / pred / podf;
 680                 err = (freq - act_freq) / (freq / 1000);
 681                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
 682                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
 683                 if (act_freq > freq)
 684                         continue;
 685                 if (err < min_err) {
 686                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 687                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 688                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 689                         min_err = err;
 690                         if (err == 0)
 691                                 break;
 692                 }
 693         }
 694
 695         if (nfc_val == ~0 || min_err > 100)
 696                 return -EINVAL;
 697
 698         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
 699                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
 700                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
 701 #ifdef CONFIG_NAND_MXS
 702                 setup_gpmi_io_clk(nfc_val);
 703 #else
 704                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
 705                         &imx_ccm->cs2cdr);
 706 #endif
 707         } else {
 708                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
 709         }
 710         return 0;
 711 }
 712
 713 static u32 get_mmdc_ch0_clk(void)
 714 {
 715         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 716         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 717
 718         u32 freq, podf, per2_clk2_podf;
 719
 720         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
 721             is_cpu_type(MXC_CPU_MX6SL)) {
 722                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 723                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 724                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 725                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 726                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 727                         if (is_cpu_type(MXC_CPU_MX6SL)) {
 728                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 729                                         freq = MXC_HCLK;
 730                                 else
 731                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 732                         } else {
 733                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 734                                         freq = decode_pll(PLL_528, MXC_HCLK);
 735                                 else
 736                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 737                         }
 738                 } else {
 739                         per2_clk2_podf = 0;
 740                         switch ((cbcmr &
 741                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 742                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 743                         case 0:
 744                                 freq = decode_pll(PLL_528, MXC_HCLK);
 745                                 break;
 746                         case 1:
 747                                 freq = mxc_get_pll_pfd(PLL_528, 2);
 748                                 break;
 749                         case 2:
 750                                 freq = mxc_get_pll_pfd(PLL_528, 0);
 751                                 break;
 752                         case 3:
 753                                 /* static / 2 divider */
 754                                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
 755                                 break;
 756                         }
 757                 }
 758                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 759         } else {
 760                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 761                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 762                 return get_periph_clk() / (podf + 1);
 763         }
 764 }
 765
 766 #ifdef CONFIG_FSL_QSPI
 767 /* qspi_num can be from 0 - 1 */
 768 void enable_qspi_clk(int qspi_num)
 769 {
 770         u32 reg = 0;
 771         /* Enable QuadSPI clock */
 772         switch (qspi_num) {
 773         case 0:
 774                 /* disable the clock gate */
 775                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 776
 777                 /* set 50M  : (50 = 396 / 2 / 4) */
 778                 reg = readl(&imx_ccm->cscmr1);
 779                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 780                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 781                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 782                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 783                 writel(reg, &imx_ccm->cscmr1);
 784
 785                 /* enable the clock gate */
 786                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 787                 break;
 788         case 1:
 789                 /*
 790                  * disable the clock gate
 791                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 792                  * disable both of them.
 793                  */
 794                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 795                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 796
 797                 /* set 50M  : (50 = 396 / 2 / 4) */
 798                 reg = readl(&imx_ccm->cs2cdr);
 799                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 800                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 801                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 802                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 803                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 804                 writel(reg, &imx_ccm->cs2cdr);
 805
 806                 /*enable the clock gate*/
 807                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 808                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 809                 break;
 810         default:
 811                 break;
 812         }
 813 }
 814 #endif
 815
 816 #ifdef CONFIG_FEC_MXC
 817 int enable_fec_anatop_clock(enum enet_freq freq)
 818 {
 819         u32 reg = 0;
 820         s32 timeout = 100000;
 821
 822         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 823                 return -EINVAL;
 824
 825         reg = readl(&anatop->pll_enet);
 826         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 827         reg |= freq;
 828
 829         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 830             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 831                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 832                 writel(reg, &anatop->pll_enet);
 833                 while (timeout--) {
 834                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 835                                 break;
 836                 }
 837                 if (timeout < 0)
 838                         return -ETIMEDOUT;
 839         }
 840
 841         /* Enable FEC clock */
 842         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 843         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 844         writel(reg, &anatop->pll_enet);
 845
 846 #ifdef CONFIG_SOC_MX6SX
 847         /*
 848          * Set enet ahb clock to 200MHz
 849          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 850          */
 851         reg = readl(&imx_ccm->chsccdr);
 852         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 853                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 854                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 855         /* PLL2 PFD2 */
 856         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 857         /* Div = 2*/
 858         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 859         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 860         writel(reg, &imx_ccm->chsccdr);
 861
 862         /* Enable enet system clock */
 863         reg = readl(&imx_ccm->CCGR3);
 864         reg |= MXC_CCM_CCGR3_ENET_MASK;
 865         writel(reg, &imx_ccm->CCGR3);
 866 #endif
 867         return 0;
 868 }
 869 #endif
 870
 871 static u32 get_usdhc_clk(u32 port)
 872 {
 873         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 874         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 875         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 876
 877         switch (port) {
 878         case 0:
 879                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 880                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 881                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 882
 883                 break;
 884         case 1:
 885                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 886                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 887                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 888
 889                 break;
 890         case 2:
 891                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 892                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 893                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 894
 895                 break;
 896         case 3:
 897                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 898                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 899                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 900
 901                 break;
 902         default:
 903                 break;
 904         }
 905
 906         if (clk_sel)
 907                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 908         else
 909                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 910
 911         return root_freq / (usdhc_podf + 1);
 912 }
 913
 914 u32 imx_get_uartclk(void)
 915 {
 916         return get_uart_clk();
 917 }
 918
 919 u32 imx_get_fecclk(void)
 920 {
 921         return mxc_get_clock(MXC_IPG_CLK);
 922 }
 923
 924 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 925 static int enable_enet_pll(uint32_t en)
 926 {
 927         u32 reg;
 928         s32 timeout = 100000;
 929
 930         /* Enable PLLs */
 931         reg = readl(&anatop->pll_enet);
 932         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 933         writel(reg, &anatop->pll_enet);
 934         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 935         while (timeout--) {
 936                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 937                         break;
 938         }
 939         if (timeout <= 0)
 940                 return -EIO;
 941         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 942         writel(reg, &anatop->pll_enet);
 943         reg |= en;
 944         writel(reg, &anatop->pll_enet);
 945         return 0;
 946 }
 947 #endif
 948
 949 #ifdef CONFIG_CMD_SATA
 950 static void ungate_sata_clock(void)
 951 {
 952         /* Enable SATA clock. */
 953         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 954 }
 955
 956 int enable_sata_clock(void)
 957 {
 958         ungate_sata_clock();
 959         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 960 }
 961
 962 void disable_sata_clock(void)
 963 {
 964         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 965 }
 966 #endif
 967
 968 #ifdef CONFIG_PCIE_IMX
 969 static void ungate_pcie_clock(void)
 970 {
 971         /* Enable PCIe clock. */
 972         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 973 }
 974
 975 int enable_pcie_clock(void)
 976 {
 977         u32 lvds1_clk_sel;
 978
 979         /*
 980          * Here be dragons!
 981          *
 982          * The register ANATOP_MISC1 is not documented in the Freescale
 983          * MX6RM. The register that is mapped in the ANATOP space and
 984          * marked as ANATOP_MISC1 is actually documented in the PMU section
 985          * of the datasheet as PMU_MISC1.
 986          *
 987          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 988          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 989          * for PCI express link that is clocked from the i.MX6.
 990          */
 991 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
 992 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
 993 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
 994 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
 995 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
 996
 997         if (is_cpu_type(MXC_CPU_MX6SX))
 998                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 999         else
1000                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1001
1002         clrsetbits_le32(&anatop_regs->ana_misc1,
1003                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1004                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1005                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1006
1007         /* PCIe reference clock sourced from AXI. */
1008         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1009
1010         /* Party time! Ungate the clock to the PCIe. */
1011 #ifdef CONFIG_CMD_SATA
1012         ungate_sata_clock();
1013 #endif
1014         ungate_pcie_clock();
1015
1016         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1017                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1018 }
1019 #endif
1020
1021 #ifdef CONFIG_SECURE_BOOT
1022 void hab_caam_clock_enable(unsigned char enable)
1023 {
1024         u32 reg;
1025
1026         /* CG4 ~ CG6, CAAM clocks */
1027         reg = __raw_readl(&imx_ccm->CCGR0);
1028         if (enable)
1029                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1030                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1031                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1032         else
1033                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1034                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1035                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1036         __raw_writel(reg, &imx_ccm->CCGR0);
1037
1038         /* EMI slow clk */
1039         reg = __raw_readl(&imx_ccm->CCGR6);
1040         if (enable)
1041                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1042         else
1043                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1044         __raw_writel(reg, &imx_ccm->CCGR6);
1045 }
1046 #endif
1047
1048 static void enable_pll3(void)
1049 {
1050         /* make sure pll3 is enabled */
1051         if ((readl(&anatop->usb1_pll_480_ctrl) &
1052                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1053                 /* enable pll's power */
1054                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1055                        &anatop->usb1_pll_480_ctrl_set);
1056                 writel(0x80, &anatop->ana_misc2_clr);
1057                 /* wait for pll lock */
1058                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1059                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1060                         ;
1061                 /* disable bypass */
1062                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1063                        &anatop->usb1_pll_480_ctrl_clr);
1064                 /* enable pll output */
1065                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1066                        &anatop->usb1_pll_480_ctrl_set);
1067         }
1068 }
1069
1070 void enable_thermal_clk(void)
1071 {
1072         enable_pll3();
1073 }
1074
1075 void ipu_clk_enable(void)
1076 {
1077         u32 reg = readl(&imx_ccm->CCGR3);
1078         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1079         writel(reg, &imx_ccm->CCGR3);
1080 }
1081
1082 void ipu_clk_disable(void)
1083 {
1084         u32 reg = readl(&imx_ccm->CCGR3);
1085         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1086         writel(reg, &imx_ccm->CCGR3);
1087 }
1088
1089 void ipu_di_clk_enable(int di)
1090 {
1091         switch (di) {
1092         case 0:
1093                 setbits_le32(&imx_ccm->CCGR3,
1094                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1095                 break;
1096         case 1:
1097                 setbits_le32(&imx_ccm->CCGR3,
1098                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1099                 break;
1100         default:
1101                 printf("%s: Invalid DI index %d\n", __func__, di);
1102         }
1103 }
1104
1105 void ipu_di_clk_disable(int di)
1106 {
1107         switch (di) {
1108         case 0:
1109                 clrbits_le32(&imx_ccm->CCGR3,
1110                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1111                 break;
1112         case 1:
1113                 clrbits_le32(&imx_ccm->CCGR3,
1114                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1115                 break;
1116         default:
1117                 printf("%s: Invalid DI index %d\n", __func__, di);
1118         }
1119 }
1120
1121 void ldb_clk_enable(int ldb)
1122 {
1123         switch (ldb) {
1124         case 0:
1125                 setbits_le32(&imx_ccm->CCGR3,
1126                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1127                 break;
1128         case 1:
1129                 setbits_le32(&imx_ccm->CCGR3,
1130                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1131                 break;
1132         default:
1133                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1134         }
1135 }
1136
1137 void ldb_clk_disable(int ldb)
1138 {
1139         switch (ldb) {
1140         case 0:
1141                 clrbits_le32(&imx_ccm->CCGR3,
1142                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1143                 break;
1144         case 1:
1145                 clrbits_le32(&imx_ccm->CCGR3,
1146                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1147                 break;
1148         default:
1149                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1150         }
1151 }
1152
1153 #ifdef CONFIG_VIDEO_MXS
1154 void lcdif_clk_enable(void)
1155 {
1156         setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1157         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1158 }
1159
1160 void lcdif_clk_disable(void)
1161 {
1162         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1163         clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1164 }
1165
1166 #define CBCMR_LCDIF_MASK        MXC_CCM_CBCMR_LCDIF_PODF_MASK
1167 #define CSCDR2_LCDIF_MASK       (MXC_CCM_CSCDR2_LCDIF_PRED_MASK |       \
1168                                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK)
1169
1170 static u32 get_lcdif_root_clk(u32 cscdr2)
1171 {
1172         int lcdif_pre_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) >>
1173                 MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET;
1174         int lcdif_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK) >>
1175                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET;
1176         u32 root_freq;
1177
1178         switch (lcdif_clk_sel) {
1179         case 0:
1180                 switch (lcdif_pre_clk_sel) {
1181                 case 0:
1182                         root_freq = decode_pll(PLL_528, MXC_HCLK);
1183                         break;
1184                 case 1:
1185                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
1186                         break;
1187                 case 2:
1188                         root_freq = decode_pll(PLL_VIDEO, MXC_HCLK);
1189                         break;
1190                 case 3:
1191                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
1192                         break;
1193                 case 4:
1194                         root_freq = mxc_get_pll_pfd(PLL_528, 1);
1195                         break;
1196                 case 5:
1197                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
1198                         break;
1199                 default:
1200                         return 0;
1201                 }
1202                 break;
1203         case 1:
1204                 root_freq = mxc_get_pll_pfd(PLL_VIDEO, 0);
1205                 break;
1206         case 2:
1207                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1208                 break;
1209         case 3:
1210                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
1211                 break;
1212         default:
1213                 return 0;
1214         }
1215
1216         return root_freq;
1217 }
1218
1219 static int set_lcdif_pll(u32 ref, u32 freq_khz,
1220                         unsigned post_div)
1221 {
1222         int ret;
1223         u64 freq = freq_khz * 1000;
1224         u32 post_div_mask = 1 << (2 - post_div);
1225         int mul = 1;
1226         u32 min_err = ~0;
1227         u32 reg;
1228         int num = 0;
1229         int denom = 1;
1230         const int min_div = 27;
1231         const int max_div = 54;
1232         const int div_mask = 0x7f;
1233         const u32 max_freq = ref * max_div / post_div;
1234         const u32 min_freq = ref * min_div / post_div;
1235
1236         if (freq > max_freq || freq < min_freq) {
1237                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03uMHz\n",
1238                         freq_khz / 1000, freq_khz % 1000,
1239                         min_freq / 1000000, min_freq / 1000 % 1000,
1240                         max_freq / 1000000, max_freq / 1000 % 1000);
1241                 return -EINVAL;
1242         }
1243         {
1244                 int d = post_div;
1245                 int m = lldiv(freq * d + ref - 1, ref);
1246                 u32 err;
1247                 u32 f;
1248
1249                 debug("%s@%d: d=%d m=%d max_div=%u min_div=%u\n", __func__, __LINE__,
1250                         d, m, max_div, min_div);
1251                 if (m > max_div || m < min_div)
1252                         return -EINVAL;
1253
1254                 f = ref * m / d;
1255                 if (f > freq) {
1256                         debug("%s@%d: d=%d m=%d f=%u freq=%llu\n", __func__, __LINE__,
1257                                 d, m, f, freq);
1258                         return -EINVAL;
1259                 }
1260                 err = freq - f;
1261                 debug("%s@%d: d=%d m=%d f=%u freq=%llu err=%d\n", __func__, __LINE__,
1262                         d, m, f, freq, err);
1263                 if (err < min_err) {
1264                         mul = m;
1265                         min_err = err;
1266                 }
1267         }
1268         if (min_err == ~0) {
1269                 printf("Cannot set VIDEO PLL to %u.%03uMHz\n",
1270                         freq_khz / 1000, freq_khz % 1000);
1271                 return -EINVAL;
1272         }
1273
1274         debug("Setting M=%3u D=%u N=%d DE=%u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1275                 mul, post_div, num, denom,
1276                 freq_khz / post_div / 1000, freq_khz / post_div % 1000,
1277                 ref * mul / post_div / 1000000,
1278                 ref * mul / post_div / 1000 % 1000);
1279
1280         reg = readl(&anatop->pll_video);
1281         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1282
1283         reg = (reg & ~(div_mask |
1284                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)) |
1285                 mul | (post_div_mask << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT);
1286         writel(reg, &anatop->pll_video);
1287
1288         ret = wait_pll_lock(&anatop->pll_video);
1289         if (ret) {
1290                 printf("Video PLL failed to lock\n");
1291                 return ret;
1292         }
1293
1294         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1295         return 0;
1296 }
1297
1298 static int set_lcdif_clk(u32 ref, u32 freq_khz)
1299 {
1300         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1301         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1302         u32 cbcmr_val;
1303         u32 cscdr2_val;
1304         u32 freq = freq_khz * 1000;
1305         u32 act_freq;
1306         u32 err;
1307         u32 min_div = 27;
1308         u32 max_div = 54;
1309         u32 min_pll_khz = ref * min_div / 4 / 1000;
1310         u32 max_pll_khz = ref * max_div / 1000;
1311         u32 pll_khz;
1312         u32 post_div = 0;
1313         u32 m;
1314         u32 min_err = ~0;
1315         u32 best_m = 0;
1316         u32 best_pred = 1;
1317         u32 best_podf = 1;
1318         u32 div;
1319         unsigned pd;
1320
1321         if (freq_khz > max_pll_khz)
1322                 return -EINVAL;
1323
1324         for (pd = 1; min_err && pd <= 4; pd <<= 1) {
1325                 for (m = max(min_div, DIV_ROUND_UP(648000 / pd, freq_khz * 64));
1326                      m <= max_div; m++) {
1327                         u32 err;
1328                         int pred = 0;
1329                         int podf = 0;
1330                         u32 root_freq = ref * m / pd;
1331
1332                         div = DIV_ROUND_UP(root_freq, freq);
1333
1334                         while (pred * podf == 0 && div <= 64) {
1335                                 int p1, p2;
1336
1337                                 for (p1 = 1; p1 <= 8; p1++) {
1338                                         for (p2 = 1; p2 <= 8; p2++) {
1339                                                 if (p1 * p2 == div) {
1340                                                         podf = p1;
1341                                                         pred = p2;
1342                                                         break;
1343                                                 }
1344                                         }
1345                                 }
1346                                 if (pred * podf == 0) {
1347                                         div++;
1348                                 }
1349                         }
1350                         if (pred * podf == 0)
1351                                 continue;
1352
1353                         /* relative error in per mille */
1354                         act_freq = root_freq / div;
1355                         err = abs(act_freq - freq) / freq_khz;
1356
1357                         if (err < min_err) {
1358                                 best_m = m;
1359                                 best_pred = pred;
1360                                 best_podf = podf;
1361                                 post_div = pd;
1362                                 min_err = err;
1363                                 if (err <= 10)
1364                                         break;
1365                         }
1366                 }
1367         }
1368         if (min_err > 50)
1369                 return -EINVAL;
1370
1371         pll_khz = ref / 1000 * best_m;
1372         if (pll_khz > max_pll_khz)
1373                 return -EINVAL;
1374
1375         if (pll_khz < min_pll_khz)
1376                 return -EINVAL;
1377
1378         err = set_lcdif_pll(ref, pll_khz / post_div, post_div);
1379         if (err)
1380                 return err;
1381
1382         cbcmr_val = (best_podf - 1) << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET;
1383         cscdr2_val = (best_pred - 1) << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET;
1384
1385         if ((cbcmr & CBCMR_LCDIF_MASK) != cbcmr_val) {
1386                 debug("changing cbcmr from %08x to %08x\n", cbcmr,
1387                         (cbcmr & ~CBCMR_LCDIF_MASK) | cbcmr_val);
1388                 clrsetbits_le32(&imx_ccm->cbcmr,
1389                                 CBCMR_LCDIF_MASK,
1390                                 cbcmr_val);
1391         } else {
1392                 debug("Leaving cbcmr unchanged [%08x]\n", cbcmr);
1393         }
1394         if ((cscdr2 & CSCDR2_LCDIF_MASK) != cscdr2_val) {
1395                 debug("changing cscdr2 from %08x to %08x\n", cscdr2,
1396                         (cscdr2 & ~CSCDR2_LCDIF_MASK) | cscdr2_val);
1397                 clrsetbits_le32(&imx_ccm->cscdr2,
1398                                 CSCDR2_LCDIF_MASK,
1399                                 cscdr2_val);
1400         } else {
1401                 debug("Leaving cscdr2 unchanged [%08x]\n", cscdr2);
1402         }
1403         return 0;
1404 }
1405
1406 void mxs_set_lcdclk(u32 khz)
1407 {
1408         set_lcdif_clk(CONFIG_SYS_MX6_HCLK, khz);
1409 }
1410
1411 static u32 get_lcdif_clk(void)
1412 {
1413         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1414         u32 podf = ((cbcmr & MXC_CCM_CBCMR_LCDIF_PODF_MASK) >>
1415                 MXC_CCM_CBCMR_LCDIF_PODF_OFFSET) + 1;
1416         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1417         u32 pred = ((cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRED_MASK) >>
1418                 MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET) + 1;
1419         u32 root_freq = get_lcdif_root_clk(cscdr2);
1420
1421         return root_freq / pred / podf;
1422 }
1423 #endif
1424
1425 unsigned int mxc_get_clock(enum mxc_clock clk)
1426 {
1427         switch (clk) {
1428         case MXC_ARM_CLK:
1429                 return get_mcu_main_clk();
1430         case MXC_PER_CLK:
1431                 return get_periph_clk();
1432         case MXC_AHB_CLK:
1433                 return get_ahb_clk();
1434         case MXC_IPG_CLK:
1435                 return get_ipg_clk();
1436         case MXC_IPG_PERCLK:
1437         case MXC_I2C_CLK:
1438                 return get_ipg_per_clk();
1439         case MXC_UART_CLK:
1440                 return get_uart_clk();
1441         case MXC_CSPI_CLK:
1442                 return get_cspi_clk();
1443         case MXC_AXI_CLK:
1444                 return get_axi_clk();
1445         case MXC_EMI_SLOW_CLK:
1446                 return get_emi_slow_clk();
1447         case MXC_DDR_CLK:
1448                 return get_mmdc_ch0_clk();
1449         case MXC_ESDHC_CLK:
1450                 return get_usdhc_clk(0);
1451         case MXC_ESDHC2_CLK:
1452                 return get_usdhc_clk(1);
1453         case MXC_ESDHC3_CLK:
1454                 return get_usdhc_clk(2);
1455         case MXC_ESDHC4_CLK:
1456                 return get_usdhc_clk(3);
1457         case MXC_SATA_CLK:
1458                 return get_ahb_clk();
1459         case MXC_NFC_CLK:
1460                 return get_nfc_clk();
1461 #ifdef CONFIG_VIDEO_MXS
1462         case MXC_LCDIF_CLK:
1463                 return get_lcdif_clk();
1464 #endif
1465         default:
1466                 printf("Unsupported MXC CLK: %d\n", clk);
1467         }
1468
1469         return 0;
1470 }
1471
1472 /* Config CPU clock */
1473 static int set_arm_clk(u32 ref, u32 freq_khz)
1474 {
1475         int ret;
1476         int d;
1477         int div = 0;
1478         int mul = 0;
1479         u32 min_err = ~0;
1480         u32 reg;
1481         const int min_div = 54;
1482         const int max_div = 108;
1483         const int div_mask = 0x7f;
1484         const u32 max_freq = ref * max_div / 2;
1485         const u32 min_freq = ref * min_div / 8 / 2;
1486
1487         if (freq_khz > max_freq / 1000 || freq_khz < min_freq / 1000) {
1488                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1489                         freq_khz / 1000, freq_khz % 1000,
1490                         min_freq / 1000000, min_freq / 1000 % 1000,
1491                         max_freq / 1000000, max_freq / 1000 % 1000);
1492                 return -EINVAL;
1493         }
1494
1495         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1496                 int m = freq_khz * 2 * d / (ref / 1000);
1497                 u32 f;
1498                 u32 err;
1499
1500                 if (m > max_div) {
1501                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1502                                 d, m);
1503                         break;
1504                 }
1505
1506                 f = ref * m / d / 2;
1507                 if (f > freq_khz * 1000) {
1508                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1509                                 d, m, f, freq_khz);
1510                         if (--m < min_div)
1511                                 return -EINVAL;
1512                         f = ref * m / d / 2;
1513                 }
1514                 err = freq_khz * 1000 - f;
1515                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1516                         d, m, f, freq_khz, err);
1517                 if (err < min_err) {
1518                         mul = m;
1519                         div = d;
1520                         min_err = err;
1521                         if (err == 0)
1522                                 break;
1523                 }
1524         }
1525         if (min_err == ~0)
1526                 return -EINVAL;
1527         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1528                 mul, div, freq_khz / 1000, freq_khz % 1000,
1529                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1530
1531         reg = readl(&anatop->pll_arm);
1532         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1533
1534         reg = (reg & ~div_mask) | mul;
1535         writel(reg, &anatop->pll_arm);
1536
1537         writel(div - 1, &imx_ccm->cacrr);
1538
1539         ret = wait_pll_lock(&anatop->pll_video);
1540         if (ret) {
1541                 printf("ARM PLL failed to lock\n");
1542                 return ret;
1543         }
1544
1545         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1546
1547         return 0;
1548 }
1549
1550 /*
1551  * This function assumes the expected core clock has to be changed by
1552  * modifying the PLL. This is NOT true always but for most of the times,
1553  * it is. So it assumes the PLL output freq is the same as the expected
1554  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1555  * In the latter case, it will try to increase the presc value until
1556  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1557  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1558  * on the targeted PLL and reference input clock to the PLL. Lastly,
1559  * it sets the register based on these values along with the dividers.
1560  * Note 1) There is no value checking for the passed-in divider values
1561  *         so the caller has to make sure those values are sensible.
1562  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1563  *         exceed NFC_CLK_MAX.
1564  */
1565 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1566 {
1567         int ret;
1568
1569         freq *= 1000;
1570
1571         switch (clk) {
1572         case MXC_ARM_CLK:
1573                 ret = set_arm_clk(ref, freq);
1574                 break;
1575
1576         case MXC_NFC_CLK:
1577                 ret = set_nfc_clk(ref, freq);
1578                 break;
1579
1580         default:
1581                 printf("Warning: Unsupported or invalid clock type: %d\n",
1582                         clk);
1583                 return -EINVAL;
1584         }
1585
1586         return ret;
1587 }
1588
1589 /*
1590  * Dump some core clocks.
1591  */
1592 #define print_pll(pll)  {                               \
1593         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1594         printf("%-12s %4d.%03d MHz\n", #pll,            \
1595                 __pll / 1000000, __pll / 1000 % 1000);  \
1596         }
1597
1598 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1599
1600 #define print_clk(clk)  {                               \
1601         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1602         printf("%-12s %4d.%03d MHz\n", #clk,            \
1603                 __clk / 1000000, __clk / 1000 % 1000);  \
1604         }
1605
1606 #define print_pfd(pll, pfd)     {                                       \
1607         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1608         if (__pfd & (0x80 << 8 * pfd)) {                                \
1609                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1610         } else {                                                        \
1611                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1612                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1613                         pll * 18 / __pfd,                               \
1614                         pll * 18 * 1000 / __pfd % 1000);                \
1615         }                                                               \
1616 }
1617
1618 static void do_mx6_showclocks(void)
1619 {
1620         print_pll(PLL_ARM);
1621         print_pll(PLL_528);
1622         print_pll(PLL_USBOTG);
1623         print_pll(PLL_AUDIO);
1624         print_pll(PLL_VIDEO);
1625         print_pll(PLL_ENET);
1626         print_pll(PLL_USB2);
1627         printf("\n");
1628
1629         print_pfd(480, 0);
1630         print_pfd(480, 1);
1631         print_pfd(480, 2);
1632         print_pfd(480, 3);
1633         print_pfd(528, 0);
1634         print_pfd(528, 1);
1635         print_pfd(528, 2);
1636         printf("\n");
1637
1638         print_clk(IPG);
1639         print_clk(UART);
1640         print_clk(CSPI);
1641         print_clk(AHB);
1642         print_clk(AXI);
1643         print_clk(DDR);
1644         print_clk(ESDHC);
1645         print_clk(ESDHC2);
1646         print_clk(ESDHC3);
1647         print_clk(ESDHC4);
1648         print_clk(EMI_SLOW);
1649         print_clk(NFC);
1650         print_clk(IPG_PER);
1651         print_clk(ARM);
1652 #ifdef CONFIG_VIDEO_MXS
1653         print_clk(LCDIF);
1654 #endif
1655 }
1656
1657 static struct clk_lookup {
1658         const char *name;
1659         unsigned int index;
1660 } mx6_clk_lookup[] = {
1661         { "arm", MXC_ARM_CLK, },
1662         { "nfc", MXC_NFC_CLK, },
1663 };
1664
1665 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1666 {
1667         int i;
1668         unsigned long freq;
1669         unsigned long ref = ~0UL;
1670
1671         if (argc < 2) {
1672                 do_mx6_showclocks();
1673                 return CMD_RET_SUCCESS;
1674         } else if (argc == 2 || argc > 4) {
1675                 return CMD_RET_USAGE;
1676         }
1677
1678         freq = simple_strtoul(argv[2], NULL, 0);
1679         if (freq == 0) {
1680                 printf("Invalid clock frequency %lu\n", freq);
1681                 return CMD_RET_FAILURE;
1682         }
1683         if (argc > 3) {
1684                 ref = simple_strtoul(argv[3], NULL, 0);
1685         }
1686         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1687                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1688                         switch (mx6_clk_lookup[i].index) {
1689                         case MXC_ARM_CLK:
1690                                 if (argc > 3)
1691                                         return CMD_RET_USAGE;
1692                                 ref = MXC_HCLK;
1693                                 break;
1694
1695                         case MXC_NFC_CLK:
1696                                 if (argc > 3 && ref > 3) {
1697                                         printf("Invalid clock selector value: %lu\n", ref);
1698                                         return CMD_RET_FAILURE;
1699                                 }
1700                                 break;
1701                         }
1702                         printf("Setting %s clock to %lu MHz\n",
1703                                 mx6_clk_lookup[i].name, freq);
1704                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1705                                 break;
1706                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1707                         printf("%s clock set to %lu.%03lu MHz\n",
1708                                 mx6_clk_lookup[i].name,
1709                                 freq / 1000000, freq / 1000 % 1000);
1710                         return CMD_RET_SUCCESS;
1711                 }
1712         }
1713         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1714                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1715                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1716                         printf("\t%s\n", mx6_clk_lookup[i].name);
1717                 }
1718         } else {
1719                 printf("Failed to set clock %s to %s MHz\n",
1720                         argv[1], argv[2]);
1721         }
1722         return CMD_RET_FAILURE;
1723 }
1724
1725 #ifndef CONFIG_SOC_MX6SX
1726 void enable_ipu_clock(void)
1727 {
1728         int reg = readl(&imx_ccm->CCGR3);
1729         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1730         writel(reg, &imx_ccm->CCGR3);
1731
1732         if (is_mx6dqp()) {
1733                 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1734                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1735         }
1736 }
1737 #endif
1738 /***************************************************/
1739
1740 U_BOOT_CMD(
1741         clocks, 4, 0, do_clocks,
1742         "display/set clocks",
1743         "                    - display clock settings\n"
1744         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1745 );