2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_ARM, /* PLL1: ARM PLL */
18 PLL_528, /* PLL2: System Bus PLL*/
19 PLL_USBOTG, /* PLL3: OTG USB PLL */
20 PLL_AUDIO, /* PLL4: Audio PLL */
21 PLL_VIDEO, /* PLL5: Video PLL */
22 PLL_ENET, /* PLL6: ENET PLL */
23 PLL_USB2, /* PLL7: USB2 PLL */
24 PLL_MLB, /* PLL8: MLB PLL */
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
30 int clk_enable(struct clk *clk)
36 if (clk->usecount == 0) {
37 debug("%s: Enabling %s clock\n", __func__, clk->name);
38 ret = clk->enable(clk);
43 assert(clk->usecount > 0);
47 void clk_disable(struct clk *clk)
52 assert(clk->usecount > 0);
53 if (!(--clk->usecount)) {
55 debug("%s: Disabling %s clock\n", __func__, clk->name);
61 int clk_get_usecount(struct clk *clk)
69 u32 clk_get_rate(struct clk *clk)
77 struct clk *clk_get_parent(struct clk *clk)
85 int clk_set_rate(struct clk *clk, unsigned long rate)
87 if (clk && clk->set_rate)
88 clk->set_rate(clk, rate);
92 long clk_round_rate(struct clk *clk, unsigned long rate)
94 if (clk == NULL || !clk->round_rate)
97 return clk->round_rate(clk, rate);
100 int clk_set_parent(struct clk *clk, struct clk *parent)
102 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103 clk ? clk->parent : NULL);
105 if (!clk || clk == parent)
108 if (clk->set_parent) {
111 ret = clk->set_parent(clk, parent);
115 clk->parent = parent;
119 #ifdef CONFIG_MXC_OCOTP
120 void enable_ocotp_clk(unsigned char enable)
124 reg = __raw_readl(&imx_ccm->CCGR2);
126 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
128 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
129 __raw_writel(reg, &imx_ccm->CCGR2);
133 #ifdef CONFIG_NAND_MXS
134 void setup_gpmi_io_clk(u32 cfg)
136 /* Disable clocks per ERR007177 from MX6 errata */
137 clrbits_le32(&imx_ccm->CCGR4,
138 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
139 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
140 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
141 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
142 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
144 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
146 clrsetbits_le32(&imx_ccm->cs2cdr,
147 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
148 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
149 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
152 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
153 setbits_le32(&imx_ccm->CCGR4,
154 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
155 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
156 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
157 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
158 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
162 void enable_usboh3_clk(unsigned char enable)
166 reg = __raw_readl(&imx_ccm->CCGR6);
168 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
170 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
171 __raw_writel(reg, &imx_ccm->CCGR6);
175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
176 void enable_enet_clk(unsigned char enable)
180 if (is_cpu_type(MXC_CPU_MX6UL)) {
181 mask = MXC_CCM_CCGR3_ENET_MASK;
182 addr = &imx_ccm->CCGR3;
184 mask = MXC_CCM_CCGR1_ENET_MASK;
185 addr = &imx_ccm->CCGR1;
189 setbits_le32(addr, mask);
191 clrbits_le32(addr, mask);
195 #ifdef CONFIG_MXC_UART
196 void enable_uart_clk(unsigned char enable)
200 if (is_cpu_type(MXC_CPU_MX6UL))
201 mask = MXC_CCM_CCGR5_UART_MASK;
203 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
206 setbits_le32(&imx_ccm->CCGR5, mask);
208 clrbits_le32(&imx_ccm->CCGR5, mask);
213 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
220 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
222 setbits_le32(&imx_ccm->CCGR6, mask);
224 clrbits_le32(&imx_ccm->CCGR6, mask);
230 #ifdef CONFIG_SYS_I2C_MXC
231 /* i2c_num can be from 0 - 3 */
232 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
241 mask = MXC_CCM_CCGR_CG_MASK
242 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
244 reg = __raw_readl(&imx_ccm->CCGR2);
249 __raw_writel(reg, &imx_ccm->CCGR2);
251 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
252 mask = MXC_CCM_CCGR6_I2C4_MASK;
253 addr = &imx_ccm->CCGR6;
255 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
256 addr = &imx_ccm->CCGR1;
258 reg = __raw_readl(addr);
263 __raw_writel(reg, addr);
269 /* spi_num can be from 0 - SPI_MAX_NUM */
270 int enable_spi_clk(unsigned char enable, unsigned spi_num)
275 if (spi_num > SPI_MAX_NUM)
278 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
279 reg = __raw_readl(&imx_ccm->CCGR1);
284 __raw_writel(reg, &imx_ccm->CCGR1);
287 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
293 div = __raw_readl(&anatop->pll_arm);
294 if (div & BM_ANADIG_PLL_ARM_BYPASS)
295 /* Assume the bypass clock is always derived from OSC */
297 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
299 return infreq * div / 2;
301 div = __raw_readl(&anatop->pll_528);
302 if (div & BM_ANADIG_PLL_528_BYPASS)
304 div &= BM_ANADIG_PLL_528_DIV_SELECT;
306 return infreq * (20 + div * 2);
308 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
309 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
311 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
313 return infreq * (20 + div * 2);
315 div = __raw_readl(&anatop->pll_audio);
316 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
318 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
322 div = __raw_readl(&anatop->pll_video);
323 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
325 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
329 div = __raw_readl(&anatop->pll_enet);
330 if (div & BM_ANADIG_PLL_ENET_BYPASS)
332 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
334 return 25000000 * (div + (div >> 1) + 1);
336 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
337 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
339 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
341 return infreq * (20 + div * 2);
343 div = __raw_readl(&anatop->pll_mlb);
344 if (div & BM_ANADIG_PLL_MLB_BYPASS)
346 /* unknown external clock provided on MLB_CLK pin */
351 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
355 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
359 if (!is_cpu_type(MXC_CPU_MX6UL)) {
361 /* No PFD3 on PPL2 */
365 div = __raw_readl(&anatop->pfd_528);
366 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
369 div = __raw_readl(&anatop->pfd_480);
370 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
373 /* No PFD on other PLL */
377 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
378 ANATOP_PFD_FRAC_SHIFT(pfd_num));
381 static u32 get_mcu_main_clk(void)
385 reg = __raw_readl(&imx_ccm->cacrr);
386 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
387 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
388 freq = decode_pll(PLL_ARM, MXC_HCLK);
390 return freq / (reg + 1);
393 u32 get_periph_clk(void)
395 u32 reg, div = 0, freq = 0;
397 reg = __raw_readl(&imx_ccm->cbcdr);
398 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
399 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
400 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
401 reg = __raw_readl(&imx_ccm->cbcmr);
402 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
403 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
407 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
415 reg = __raw_readl(&imx_ccm->cbcmr);
416 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
417 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
421 freq = decode_pll(PLL_528, MXC_HCLK);
424 freq = mxc_get_pll_pfd(PLL_528, 2);
427 freq = mxc_get_pll_pfd(PLL_528, 0);
430 /* static / 2 divider */
431 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
436 return freq / (div + 1);
439 static u32 get_ipg_clk(void)
443 reg = __raw_readl(&imx_ccm->cbcdr);
444 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
445 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
447 return get_ahb_clk() / (ipg_podf + 1);
450 static u32 get_ipg_per_clk(void)
452 u32 reg, perclk_podf;
454 reg = __raw_readl(&imx_ccm->cscmr1);
455 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
456 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
457 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
458 return MXC_HCLK; /* OSC 24Mhz */
461 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
463 return get_ipg_clk() / (perclk_podf + 1);
466 static u32 get_uart_clk(void)
469 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
470 reg = __raw_readl(&imx_ccm->cscdr1);
472 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
473 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
474 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
478 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
479 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
481 return freq / (uart_podf + 1);
484 static u32 get_cspi_clk(void)
488 reg = __raw_readl(&imx_ccm->cscdr2);
489 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
490 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
492 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
493 is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
494 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
495 return MXC_HCLK / (cspi_podf + 1);
498 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
501 static u32 get_axi_clk(void)
503 u32 root_freq, axi_podf;
504 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
506 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
507 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
509 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
510 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
511 root_freq = mxc_get_pll_pfd(PLL_528, 2);
513 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
515 root_freq = get_periph_clk();
517 return root_freq / (axi_podf + 1);
520 static u32 get_emi_slow_clk(void)
522 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
524 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
525 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
526 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
527 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
528 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
530 switch (emi_clk_sel) {
532 root_freq = get_axi_clk();
535 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
538 root_freq = mxc_get_pll_pfd(PLL_528, 2);
541 root_freq = mxc_get_pll_pfd(PLL_528, 0);
545 return root_freq / (emi_slow_podf + 1);
548 static u32 get_nfc_clk(void)
550 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
551 u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
552 u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
553 int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
554 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
557 switch (nfc_clk_sel) {
559 root_freq = mxc_get_pll_pfd(PLL_528, 0);
562 root_freq = decode_pll(PLL_528, MXC_HCLK);
565 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
568 root_freq = mxc_get_pll_pfd(PLL_528, 2);
574 return root_freq / (pred + 1) / (podf + 1);
577 #define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \
578 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \
579 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
581 static int set_nfc_clk(u32 ref, u32 freq_khz)
583 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
590 u32 freq = freq_khz * 1000;
592 for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
596 if (ref < 4 && ref != nfc_clk_sel)
599 switch (nfc_clk_sel) {
601 root_freq = mxc_get_pll_pfd(PLL_528, 0);
604 root_freq = decode_pll(PLL_528, MXC_HCLK);
607 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
610 root_freq = mxc_get_pll_pfd(PLL_528, 2);
613 if (root_freq < freq)
616 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
617 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
618 act_freq = root_freq / pred / podf;
619 err = (freq - act_freq) * 100 / freq;
620 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
621 nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
625 nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
626 nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
627 nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
634 if (nfc_val == ~0 || min_err > 10)
637 if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
638 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
639 (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
640 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
643 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
648 static u32 get_mmdc_ch0_clk(void)
650 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
651 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
653 u32 freq, podf, per2_clk2_podf;
655 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
656 is_cpu_type(MXC_CPU_MX6SL)) {
657 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
658 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
659 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
660 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
661 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
662 if (is_cpu_type(MXC_CPU_MX6SL)) {
663 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
666 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
668 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
669 freq = decode_pll(PLL_528, MXC_HCLK);
671 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
676 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
677 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
679 freq = decode_pll(PLL_528, MXC_HCLK);
682 freq = mxc_get_pll_pfd(PLL_528, 2);
685 freq = mxc_get_pll_pfd(PLL_528, 0);
688 /* static / 2 divider */
689 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
693 return freq / (podf + 1) / (per2_clk2_podf + 1);
695 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
696 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
697 return get_periph_clk() / (podf + 1);
701 #ifdef CONFIG_FSL_QSPI
702 /* qspi_num can be from 0 - 1 */
703 void enable_qspi_clk(int qspi_num)
706 /* Enable QuadSPI clock */
709 /* disable the clock gate */
710 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
712 /* set 50M : (50 = 396 / 2 / 4) */
713 reg = readl(&imx_ccm->cscmr1);
714 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
715 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
716 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
717 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
718 writel(reg, &imx_ccm->cscmr1);
720 /* enable the clock gate */
721 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
725 * disable the clock gate
726 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
727 * disable both of them.
729 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
730 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
732 /* set 50M : (50 = 396 / 2 / 4) */
733 reg = readl(&imx_ccm->cs2cdr);
734 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
735 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
736 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
737 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
738 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
739 writel(reg, &imx_ccm->cs2cdr);
741 /*enable the clock gate*/
742 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
743 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
751 #ifdef CONFIG_FEC_MXC
752 int enable_fec_anatop_clock(enum enet_freq freq)
755 s32 timeout = 100000;
757 struct anatop_regs __iomem *anatop =
758 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
760 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
763 reg = readl(&anatop->pll_enet);
764 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
767 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
768 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
769 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
770 writel(reg, &anatop->pll_enet);
772 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
779 /* Enable FEC clock */
780 reg |= BM_ANADIG_PLL_ENET_ENABLE;
781 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
782 writel(reg, &anatop->pll_enet);
784 #ifdef CONFIG_SOC_MX6SX
786 * Set enet ahb clock to 200MHz
787 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
789 reg = readl(&imx_ccm->chsccdr);
790 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
791 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
792 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
794 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
796 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
797 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
798 writel(reg, &imx_ccm->chsccdr);
800 /* Enable enet system clock */
801 reg = readl(&imx_ccm->CCGR3);
802 reg |= MXC_CCM_CCGR3_ENET_MASK;
803 writel(reg, &imx_ccm->CCGR3);
809 static u32 get_usdhc_clk(u32 port)
811 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
812 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
813 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
817 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
818 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
819 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
823 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
824 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
825 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
829 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
830 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
831 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
835 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
836 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
837 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
845 root_freq = mxc_get_pll_pfd(PLL_528, 0);
847 root_freq = mxc_get_pll_pfd(PLL_528, 2);
849 return root_freq / (usdhc_podf + 1);
852 u32 imx_get_uartclk(void)
854 return get_uart_clk();
857 u32 imx_get_fecclk(void)
859 return mxc_get_clock(MXC_IPG_CLK);
862 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
863 static int enable_enet_pll(uint32_t en)
866 s32 timeout = 100000;
869 reg = readl(&anatop->pll_enet);
870 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
871 writel(reg, &anatop->pll_enet);
872 reg |= BM_ANADIG_PLL_ENET_ENABLE;
874 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
879 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
880 writel(reg, &anatop->pll_enet);
882 writel(reg, &anatop->pll_enet);
887 #ifdef CONFIG_CMD_SATA
888 static void ungate_sata_clock(void)
890 struct mxc_ccm_reg *const imx_ccm =
891 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
893 /* Enable SATA clock. */
894 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
897 int enable_sata_clock(void)
900 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
903 void disable_sata_clock(void)
905 struct mxc_ccm_reg *const imx_ccm =
906 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
908 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
912 #ifdef CONFIG_PCIE_IMX
913 static void ungate_pcie_clock(void)
915 struct mxc_ccm_reg *const imx_ccm =
916 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
918 /* Enable PCIe clock. */
919 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
922 int enable_pcie_clock(void)
924 struct anatop_regs *anatop_regs =
925 (struct anatop_regs *)ANATOP_BASE_ADDR;
926 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
932 * The register ANATOP_MISC1 is not documented in the Freescale
933 * MX6RM. The register that is mapped in the ANATOP space and
934 * marked as ANATOP_MISC1 is actually documented in the PMU section
935 * of the datasheet as PMU_MISC1.
937 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
938 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
939 * for PCI express link that is clocked from the i.MX6.
941 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
942 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
943 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
944 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
945 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
947 if (is_cpu_type(MXC_CPU_MX6SX))
948 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
950 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
952 clrsetbits_le32(&anatop_regs->ana_misc1,
953 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
954 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
955 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
957 /* PCIe reference clock sourced from AXI. */
958 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
960 /* Party time! Ungate the clock to the PCIe. */
961 #ifdef CONFIG_CMD_SATA
966 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
967 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
971 #ifdef CONFIG_SECURE_BOOT
972 void hab_caam_clock_enable(unsigned char enable)
976 /* CG4 ~ CG6, CAAM clocks */
977 reg = __raw_readl(&imx_ccm->CCGR0);
979 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
980 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
981 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
983 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
984 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
985 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
986 __raw_writel(reg, &imx_ccm->CCGR0);
989 reg = __raw_readl(&imx_ccm->CCGR6);
991 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
993 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
994 __raw_writel(reg, &imx_ccm->CCGR6);
998 static void enable_pll3(void)
1000 struct anatop_regs __iomem *anatop =
1001 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1003 /* make sure pll3 is enabled */
1004 if ((readl(&anatop->usb1_pll_480_ctrl) &
1005 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1006 /* enable pll's power */
1007 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1008 &anatop->usb1_pll_480_ctrl_set);
1009 writel(0x80, &anatop->ana_misc2_clr);
1010 /* wait for pll lock */
1011 while ((readl(&anatop->usb1_pll_480_ctrl) &
1012 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1014 /* disable bypass */
1015 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1016 &anatop->usb1_pll_480_ctrl_clr);
1017 /* enable pll output */
1018 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1019 &anatop->usb1_pll_480_ctrl_set);
1023 void enable_thermal_clk(void)
1028 void ipu_clk_enable(void)
1030 u32 reg = readl(&imx_ccm->CCGR3);
1031 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1032 writel(reg, &imx_ccm->CCGR3);
1035 void ipu_clk_disable(void)
1037 u32 reg = readl(&imx_ccm->CCGR3);
1038 reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1039 writel(reg, &imx_ccm->CCGR3);
1042 void ipu_di_clk_enable(int di)
1046 setbits_le32(&imx_ccm->CCGR3,
1047 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1050 setbits_le32(&imx_ccm->CCGR3,
1051 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1054 printf("%s: Invalid DI index %d\n", __func__, di);
1058 void ipu_di_clk_disable(int di)
1062 clrbits_le32(&imx_ccm->CCGR3,
1063 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1066 clrbits_le32(&imx_ccm->CCGR3,
1067 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1070 printf("%s: Invalid DI index %d\n", __func__, di);
1074 void ldb_clk_enable(int ldb)
1078 setbits_le32(&imx_ccm->CCGR3,
1079 MXC_CCM_CCGR3_LDB_DI0_MASK);
1082 setbits_le32(&imx_ccm->CCGR3,
1083 MXC_CCM_CCGR3_LDB_DI1_MASK);
1086 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1090 void ldb_clk_disable(int ldb)
1094 clrbits_le32(&imx_ccm->CCGR3,
1095 MXC_CCM_CCGR3_LDB_DI0_MASK);
1098 clrbits_le32(&imx_ccm->CCGR3,
1099 MXC_CCM_CCGR3_LDB_DI1_MASK);
1102 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1106 void ocotp_clk_enable(void)
1108 u32 reg = readl(&imx_ccm->CCGR2);
1109 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1110 writel(reg, &imx_ccm->CCGR2);
1113 void ocotp_clk_disable(void)
1115 u32 reg = readl(&imx_ccm->CCGR2);
1116 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1117 writel(reg, &imx_ccm->CCGR2);
1120 unsigned int mxc_get_clock(enum mxc_clock clk)
1124 return get_mcu_main_clk();
1126 return get_periph_clk();
1128 return get_ahb_clk();
1130 return get_ipg_clk();
1131 case MXC_IPG_PERCLK:
1133 return get_ipg_per_clk();
1135 return get_uart_clk();
1137 return get_cspi_clk();
1139 return get_axi_clk();
1140 case MXC_EMI_SLOW_CLK:
1141 return get_emi_slow_clk();
1143 return get_mmdc_ch0_clk();
1145 return get_usdhc_clk(0);
1146 case MXC_ESDHC2_CLK:
1147 return get_usdhc_clk(1);
1148 case MXC_ESDHC3_CLK:
1149 return get_usdhc_clk(2);
1150 case MXC_ESDHC4_CLK:
1151 return get_usdhc_clk(3);
1153 return get_ahb_clk();
1155 return get_nfc_clk();
1157 printf("Unsupported MXC CLK: %d\n", clk);
1163 static inline int gcd(int m, int n)
1177 /* Config CPU clock */
1178 static int set_arm_clk(u32 ref, u32 freq_khz)
1186 if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1187 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1188 freq_khz / 1000, freq_khz % 1000,
1189 54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1190 108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1194 for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1195 int m = freq_khz * 2 * d / (ref / 1000);
1200 debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1205 f = ref * m / d / 2;
1206 if (f > freq_khz * 1000) {
1207 debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1211 f = ref * m / d / 2;
1213 err = freq_khz * 1000 - f;
1214 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1215 d, m, f, freq_khz, err);
1216 if (err < min_err) {
1226 debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1227 mul, div, freq_khz / 1000, freq_khz % 1000,
1228 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1230 reg = readl(&anatop->pll_arm);
1231 debug("anadig_pll_arm=%08x -> %08x\n",
1232 reg, (reg & ~0x7f) | mul);
1235 writel(reg, &anatop->pll_arm); /* bypass PLL */
1237 reg = (reg & ~0x7f) | mul;
1238 writel(reg, &anatop->pll_arm);
1240 writel(div - 1, &imx_ccm->cacrr);
1243 writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1249 * This function assumes the expected core clock has to be changed by
1250 * modifying the PLL. This is NOT true always but for most of the times,
1251 * it is. So it assumes the PLL output freq is the same as the expected
1252 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1253 * In the latter case, it will try to increase the presc value until
1254 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1255 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1256 * on the targeted PLL and reference input clock to the PLL. Lastly,
1257 * it sets the register based on these values along with the dividers.
1258 * Note 1) There is no value checking for the passed-in divider values
1259 * so the caller has to make sure those values are sensible.
1260 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1261 * exceed NFC_CLK_MAX.
1262 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
1263 * 177MHz for higher voltage, this function fixes the max to 133MHz.
1264 * 4) This function should not have allowed diag_printf() calls since
1265 * the serial driver has been stoped. But leave then here to allow
1266 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1268 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1276 ret = set_arm_clk(ref, freq);
1280 ret = set_nfc_clk(ref, freq);
1284 printf("Warning: Unsupported or invalid clock type: %d\n",
1293 * Dump some core clocks.
1295 #define print_pll(pll) { \
1296 u32 __pll = decode_pll(pll, MXC_HCLK); \
1297 printf("%-12s %4d.%03d MHz\n", #pll, \
1298 __pll / 1000000, __pll / 1000 % 1000); \
1301 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1303 #define print_clk(clk) { \
1304 u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \
1305 printf("%-12s %4d.%03d MHz\n", #clk, \
1306 __clk / 1000000, __clk / 1000 % 1000); \
1309 #define print_pfd(pll, pfd) { \
1310 u32 __pfd = readl(&anatop->pfd_##pll); \
1311 if (__pfd & (0x80 << 8 * pfd)) { \
1312 printf("PFD_%s[%d] OFF\n", #pll, pfd); \
1314 __pfd = (__pfd >> 8 * pfd) & 0x3f; \
1315 printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \
1317 pll * 18 * 1000 / __pfd % 1000); \
1321 static void do_mx6_showclocks(void)
1325 print_pll(PLL_USBOTG);
1326 print_pll(PLL_AUDIO);
1327 print_pll(PLL_VIDEO);
1328 print_pll(PLL_ENET);
1329 print_pll(PLL_USB2);
1351 print_clk(EMI_SLOW);
1357 static struct clk_lookup {
1360 } mx6_clk_lookup[] = {
1361 { "arm", MXC_ARM_CLK, },
1362 { "nfc", MXC_NFC_CLK, },
1365 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1369 unsigned long ref = ~0UL;
1372 do_mx6_showclocks();
1373 return CMD_RET_SUCCESS;
1374 } else if (argc == 2 || argc > 4) {
1375 return CMD_RET_USAGE;
1378 freq = simple_strtoul(argv[2], NULL, 0);
1380 printf("Invalid clock frequency %lu\n", freq);
1381 return CMD_RET_FAILURE;
1384 ref = simple_strtoul(argv[3], NULL, 0);
1386 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1387 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1388 switch (mx6_clk_lookup[i].index) {
1391 return CMD_RET_USAGE;
1396 if (argc > 3 && ref > 3) {
1397 printf("Invalid clock selector value: %lu\n", ref);
1398 return CMD_RET_FAILURE;
1402 printf("Setting %s clock to %lu MHz\n",
1403 mx6_clk_lookup[i].name, freq);
1404 if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1406 freq = mxc_get_clock(mx6_clk_lookup[i].index);
1407 printf("%s clock set to %lu.%03lu MHz\n",
1408 mx6_clk_lookup[i].name,
1409 freq / 1000000, freq / 1000 % 1000);
1410 return CMD_RET_SUCCESS;
1413 if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1414 printf("clock %s not found; supported clocks are:\n", argv[1]);
1415 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1416 printf("\t%s\n", mx6_clk_lookup[i].name);
1419 printf("Failed to set clock %s to %s MHz\n",
1422 return CMD_RET_FAILURE;
1425 #ifndef CONFIG_SOC_MX6SX
1426 void enable_ipu_clock(void)
1428 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1430 reg = readl(&mxc_ccm->CCGR3);
1431 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1432 writel(reg, &mxc_ccm->CCGR3);
1435 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1436 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1440 /***************************************************/
1443 clocks, 4, 0, do_clocks,
1444 "display/set clocks",
1445 " - display clock settings\n"
1446 "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"