arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_ARM,        /* PLL1: ARM PLL */
  18         PLL_528,        /* PLL2: System Bus PLL*/
  19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
  20         PLL_AUDIO,      /* PLL4: Audio PLL */
  21         PLL_VIDEO,      /* PLL5: Video PLL */
  22         PLL_ENET,       /* PLL6: ENET PLL */
  23         PLL_USB2,       /* PLL7: USB2 PLL */
  24         PLL_MLB,        /* PLL8: MLB PLL */
  25 };
  26
  27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
  28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
  29
  30 int clk_enable(struct clk *clk)
  31 {
  32         int ret = 0;
  33
  34         if (!clk)
  35                 return 0;
  36         if (clk->usecount == 0) {
  37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
  38                 ret = clk->enable(clk);
  39                 if (ret)
  40                         return ret;
  41                 clk->usecount++;
  42         }
  43         assert(clk->usecount > 0);
  44         return ret;
  45 }
  46
  47 void clk_disable(struct clk *clk)
  48 {
  49         if (!clk)
  50                 return;
  51
  52         assert(clk->usecount > 0);
  53         if (!(--clk->usecount)) {
  54                 if (clk->disable) {
  55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
  56                         clk->disable(clk);
  57                 }
  58         }
  59 }
  60
  61 int clk_get_usecount(struct clk *clk)
  62 {
  63         if (clk == NULL)
  64                 return 0;
  65
  66         return clk->usecount;
  67 }
  68
  69 u32 clk_get_rate(struct clk *clk)
  70 {
  71         if (!clk)
  72                 return 0;
  73
  74         return clk->rate;
  75 }
  76
  77 struct clk *clk_get_parent(struct clk *clk)
  78 {
  79         if (!clk)
  80                 return 0;
  81
  82         return clk->parent;
  83 }
  84
  85 int clk_set_rate(struct clk *clk, unsigned long rate)
  86 {
  87         if (clk && clk->set_rate)
  88                 clk->set_rate(clk, rate);
  89         return clk->rate;
  90 }
  91
  92 long clk_round_rate(struct clk *clk, unsigned long rate)
  93 {
  94         if (clk == NULL || !clk->round_rate)
  95                 return 0;
  96
  97         return clk->round_rate(clk, rate);
  98 }
  99
 100 int clk_set_parent(struct clk *clk, struct clk *parent)
 101 {
 102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
 103                 clk ? clk->parent : NULL);
 104
 105         if (!clk || clk == parent)
 106                 return 0;
 107
 108         if (clk->set_parent) {
 109                 int ret;
 110
 111                 ret = clk->set_parent(clk, parent);
 112                 if (ret)
 113                         return ret;
 114         }
 115         clk->parent = parent;
 116         return 0;
 117 }
 118
 119 #define PLL_LOCK_BIT            (1 << 31)
 120
 121 static inline int wait_pll_lock(u32 *reg)
 122 {
 123         int loops = 0;
 124         u32 val;
 125
 126         while (!((val = readl(reg)) & PLL_LOCK_BIT)) {
 127                 loops++;
 128                 if (loops > 1000)
 129                         break;
 130                 udelay(1);
 131         }
 132         if (!(val & PLL_LOCK_BIT) && !(readl(reg) & PLL_LOCK_BIT))
 133                 return -ETIMEDOUT;
 134         return 0;
 135 }
 136
 137 #ifdef CONFIG_MXC_OCOTP
 138 void enable_ocotp_clk(unsigned char enable)
 139 {
 140         u32 reg;
 141
 142         reg = __raw_readl(&imx_ccm->CCGR2);
 143         if (enable)
 144                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 145         else
 146                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 147         __raw_writel(reg, &imx_ccm->CCGR2);
 148 }
 149 #endif
 150
 151 #ifdef CONFIG_NAND_MXS
 152 void setup_gpmi_io_clk(u32 cfg)
 153 {
 154         /* Disable clocks per ERR007177 from MX6 errata */
 155         clrbits_le32(&imx_ccm->CCGR4,
 156                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 158                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 159                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 160                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 161
 162         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 163
 164         clrsetbits_le32(&imx_ccm->cs2cdr,
 165                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 166                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 167                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 168                         cfg);
 169
 170         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 171         setbits_le32(&imx_ccm->CCGR4,
 172                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 173                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 174                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 175                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 176                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 177 }
 178 #endif
 179
 180 void enable_usboh3_clk(unsigned char enable)
 181 {
 182         u32 reg;
 183
 184         reg = __raw_readl(&imx_ccm->CCGR6);
 185         if (enable)
 186                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
 187         else
 188                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
 189         __raw_writel(reg, &imx_ccm->CCGR6);
 190
 191 }
 192
 193 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 194 void enable_enet_clk(unsigned char enable)
 195 {
 196         u32 mask, *addr;
 197
 198         if (is_cpu_type(MXC_CPU_MX6UL)) {
 199                 mask = MXC_CCM_CCGR3_ENET_MASK;
 200                 addr = &imx_ccm->CCGR3;
 201         } else {
 202                 mask = MXC_CCM_CCGR1_ENET_MASK;
 203                 addr = &imx_ccm->CCGR1;
 204         }
 205
 206         if (enable)
 207                 setbits_le32(addr, mask);
 208         else
 209                 clrbits_le32(addr, mask);
 210 }
 211 #endif
 212
 213 #ifdef CONFIG_MXC_UART
 214 void enable_uart_clk(unsigned char enable)
 215 {
 216         u32 mask;
 217
 218         if (is_cpu_type(MXC_CPU_MX6UL))
 219                 mask = MXC_CCM_CCGR5_UART_MASK;
 220         else
 221                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 222
 223         if (enable)
 224                 setbits_le32(&imx_ccm->CCGR5, mask);
 225         else
 226                 clrbits_le32(&imx_ccm->CCGR5, mask);
 227 }
 228 #endif
 229
 230 #ifdef CONFIG_MMC
 231 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 232 {
 233         u32 mask;
 234
 235         if (bus_num > 3)
 236                 return -EINVAL;
 237
 238         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 239         if (enable)
 240                 setbits_le32(&imx_ccm->CCGR6, mask);
 241         else
 242                 clrbits_le32(&imx_ccm->CCGR6, mask);
 243
 244         return 0;
 245 }
 246 #endif
 247
 248 #ifdef CONFIG_SYS_I2C_MXC
 249 /* i2c_num can be from 0 - 3 */
 250 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 251 {
 252         u32 reg;
 253         u32 mask;
 254         u32 *addr;
 255
 256         if (i2c_num > 3)
 257                 return -EINVAL;
 258         if (i2c_num < 3) {
 259                 mask = MXC_CCM_CCGR_CG_MASK
 260                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 261                         + (i2c_num << 1));
 262                 reg = __raw_readl(&imx_ccm->CCGR2);
 263                 if (enable)
 264                         reg |= mask;
 265                 else
 266                         reg &= ~mask;
 267                 __raw_writel(reg, &imx_ccm->CCGR2);
 268         } else {
 269                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 270                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 271                         addr = &imx_ccm->CCGR6;
 272                 } else {
 273                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 274                         addr = &imx_ccm->CCGR1;
 275                 }
 276                 reg = __raw_readl(addr);
 277                 if (enable)
 278                         reg |= mask;
 279                 else
 280                         reg &= ~mask;
 281                 __raw_writel(reg, addr);
 282         }
 283         return 0;
 284 }
 285 #endif
 286
 287 /* spi_num can be from 0 - SPI_MAX_NUM */
 288 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 289 {
 290         u32 reg;
 291         u32 mask;
 292
 293         if (spi_num > SPI_MAX_NUM)
 294                 return -EINVAL;
 295
 296         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 297         reg = __raw_readl(&imx_ccm->CCGR1);
 298         if (enable)
 299                 reg |= mask;
 300         else
 301                 reg &= ~mask;
 302         __raw_writel(reg, &imx_ccm->CCGR1);
 303         return 0;
 304 }
 305
 306 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 307 {
 308         u32 div, post_div;
 309         u32 pll_num, pll_denom;
 310         u64 freq;
 311
 312         switch (pll) {
 313         case PLL_ARM:
 314                 div = __raw_readl(&anatop->pll_arm);
 315                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
 316                         /* Assume the bypass clock is always derived from OSC */
 317                         return infreq;
 318                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
 319
 320                 return infreq * div / 2;
 321         case PLL_528:
 322                 div = __raw_readl(&anatop->pll_528);
 323                 if (div & BM_ANADIG_PLL_528_BYPASS)
 324                         return infreq;
 325                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 326
 327                 return infreq * (20 + div * 2);
 328         case PLL_USBOTG:
 329                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
 330                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 331                         return infreq;
 332                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 333
 334                 return infreq * (20 + div * 2);
 335         case PLL_AUDIO:
 336                 div = __raw_readl(&anatop->pll_audio);
 337                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 338                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 339                         return infreq;
 340
 341                 pll_num = __raw_readl(&anatop->pll_audio_num);
 342                 pll_denom = __raw_readl(&anatop->pll_audio_denom);
 343
 344                 post_div = (div & BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT) >>
 345                         BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT;
 346                 if (post_div == 3) {
 347                         printf("Invalid post divider value for PLL_AUDIO\n");
 348                         return 0;
 349                 }
 350                 post_div = 1 << (2 - post_div);
 351                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 352
 353                 freq = (u64)infreq * pll_num / pll_denom;
 354                 freq += infreq * div;
 355                 return lldiv(freq, post_div);
 356         case PLL_VIDEO:
 357                 div = __raw_readl(&anatop->pll_video);
 358                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 359                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 360                         return infreq;
 361
 362                 pll_num = __raw_readl(&anatop->pll_video_num);
 363                 pll_denom = __raw_readl(&anatop->pll_video_denom);
 364
 365                 post_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
 366                         BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 367                 if (post_div == 3) {
 368                         printf("Invalid post divider value for PLL_VIDEO\n");
 369                         return 0;
 370                 }
 371                 post_div = 1 << (2 - post_div);
 372                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 373
 374                 freq = (u64)infreq * pll_num / pll_denom;
 375                 freq += infreq * div;
 376                 return lldiv(freq, post_div);
 377         case PLL_ENET:
 378                 div = __raw_readl(&anatop->pll_enet);
 379                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
 380                         return infreq;
 381                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 382
 383                 return 25000000 * (div + (div >> 1) + 1);
 384         case PLL_USB2:
 385                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
 386                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 387                         return infreq;
 388                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 389
 390                 return infreq * (20 + div * 2);
 391         case PLL_MLB:
 392                 div = __raw_readl(&anatop->pll_mlb);
 393                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
 394                         return infreq;
 395                 /* fallthru: unknown external clock provided on MLB_CLK pin */
 396         default:
 397                 return 0;
 398         }
 399         /* NOTREACHED */
 400 }
 401
 402 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 403 {
 404         u32 div;
 405         u64 freq;
 406
 407         switch (pll) {
 408         case PLL_528:
 409                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
 410                         if (pfd_num == 3) {
 411                                 /* No PFD3 on PPL2 */
 412                                 return 0;
 413                         }
 414                 }
 415                 div = __raw_readl(&anatop->pfd_528);
 416                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
 417                 break;
 418         case PLL_USBOTG:
 419                 div = __raw_readl(&anatop->pfd_480);
 420                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 421                 break;
 422         default:
 423                 /* No PFD on other PLL */
 424                 return 0;
 425         }
 426
 427         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 428                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 429 }
 430
 431 static u32 get_mcu_main_clk(void)
 432 {
 433         u32 reg, freq;
 434
 435         reg = __raw_readl(&imx_ccm->cacrr);
 436         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 437         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 438         freq = decode_pll(PLL_ARM, MXC_HCLK);
 439
 440         return freq / (reg + 1);
 441 }
 442
 443 u32 get_periph_clk(void)
 444 {
 445         u32 reg, div = 0, freq = 0;
 446
 447         reg = __raw_readl(&imx_ccm->cbcdr);
 448         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 449                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 450                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 451                 reg = __raw_readl(&imx_ccm->cbcmr);
 452                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 453                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 454
 455                 switch (reg) {
 456                 case 0:
 457                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 458                         break;
 459                 case 1:
 460                 case 2:
 461                         freq = MXC_HCLK;
 462                         break;
 463                 }
 464         } else {
 465                 reg = __raw_readl(&imx_ccm->cbcmr);
 466                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 467                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 468
 469                 switch (reg) {
 470                 case 0:
 471                         freq = decode_pll(PLL_528, MXC_HCLK);
 472                         break;
 473                 case 1:
 474                         freq = mxc_get_pll_pfd(PLL_528, 2);
 475                         break;
 476                 case 2:
 477                         freq = mxc_get_pll_pfd(PLL_528, 0);
 478                         break;
 479                 case 3:
 480                         /* static / 2 divider */
 481                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
 482                         break;
 483                 }
 484         }
 485
 486         return freq / (div + 1);
 487 }
 488
 489 static u32 get_ipg_clk(void)
 490 {
 491         u32 reg, ipg_podf;
 492
 493         reg = __raw_readl(&imx_ccm->cbcdr);
 494         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 495         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 496
 497         return get_ahb_clk() / (ipg_podf + 1);
 498 }
 499
 500 static u32 get_ipg_per_clk(void)
 501 {
 502         u32 reg, perclk_podf;
 503
 504         reg = __raw_readl(&imx_ccm->cscmr1);
 505         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 506             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 507                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 508                         return MXC_HCLK; /* OSC 24Mhz */
 509         }
 510
 511         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 512
 513         return get_ipg_clk() / (perclk_podf + 1);
 514 }
 515
 516 static u32 get_uart_clk(void)
 517 {
 518         u32 reg, uart_podf;
 519         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 520         reg = __raw_readl(&imx_ccm->cscdr1);
 521
 522         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 523             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 524                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 525                         freq = MXC_HCLK;
 526         }
 527
 528         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 529         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 530
 531         return freq / (uart_podf + 1);
 532 }
 533
 534 static u32 get_cspi_clk(void)
 535 {
 536         u32 reg, cspi_podf;
 537
 538         reg = __raw_readl(&imx_ccm->cscdr2);
 539         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 540                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 541
 542         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
 543             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 544                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 545                         return MXC_HCLK / (cspi_podf + 1);
 546         }
 547
 548         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 549 }
 550
 551 static u32 get_axi_clk(void)
 552 {
 553         u32 root_freq, axi_podf;
 554         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 555
 556         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 557         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 558
 559         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 560                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 561                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 562                 else
 563                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 564         } else {
 565                 root_freq = get_periph_clk();
 566         }
 567         return  root_freq / (axi_podf + 1);
 568 }
 569
 570 static u32 get_emi_slow_clk(void)
 571 {
 572         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 573
 574         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 575         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 576         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 577         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 578         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 579
 580         switch (emi_clk_sel) {
 581         case 0:
 582                 root_freq = get_axi_clk();
 583                 break;
 584         case 1:
 585                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 586                 break;
 587         case 2:
 588                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
 589                 break;
 590         case 3:
 591                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
 592                 break;
 593         }
 594
 595         return root_freq / (emi_slow_podf + 1);
 596 }
 597
 598 static u32 get_nfc_clk(void)
 599 {
 600         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 601         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
 602                 MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 603         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
 604                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 605         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
 606                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 607         u32 root_freq;
 608
 609         switch (nfc_clk_sel) {
 610         case 0:
 611                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 612                 break;
 613         case 1:
 614                 root_freq = decode_pll(PLL_528, MXC_HCLK);
 615                 break;
 616         case 2:
 617                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 618                 break;
 619         case 3:
 620                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 621                 break;
 622         case 4:
 623                 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
 624                 break;
 625         default:
 626                 return 0;
 627         }
 628
 629         return root_freq / (pred + 1) / (podf + 1);
 630 }
 631
 632 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
 633                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
 634                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
 635
 636 static int set_nfc_clk(u32 ref, u32 freq_khz)
 637 {
 638         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 639         u32 podf;
 640         u32 pred;
 641         int nfc_clk_sel;
 642         u32 root_freq;
 643         u32 min_err = ~0;
 644         u32 nfc_val = ~0;
 645         u32 freq = freq_khz * 1000;
 646
 647         for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
 648                 u32 act_freq;
 649                 u32 err;
 650
 651                 if (ref < 4 && ref != nfc_clk_sel)
 652                         continue;
 653
 654                 switch (nfc_clk_sel) {
 655                 case 0:
 656                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
 657                         break;
 658                 case 1:
 659                         root_freq = decode_pll(PLL_528, MXC_HCLK);
 660                         break;
 661                 case 2:
 662                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 663                         break;
 664                 case 3:
 665                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 666                         break;
 667                 }
 668                 if (root_freq < freq)
 669                         continue;
 670
 671                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
 672                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
 673                 act_freq = root_freq / pred / podf;
 674                 err = (freq - act_freq) * 100 / freq;
 675                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
 676                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
 677                 if (act_freq > freq)
 678                         continue;
 679                 if (err < min_err) {
 680                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 681                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 682                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 683                         min_err = err;
 684                         if (err == 0)
 685                                 break;
 686                 }
 687         }
 688
 689         if (nfc_val == ~0 || min_err > 10)
 690                 return -EINVAL;
 691
 692         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
 693                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
 694                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
 695                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
 696                         &imx_ccm->cs2cdr);
 697         } else {
 698                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
 699         }
 700         return 0;
 701 }
 702
 703 static u32 get_mmdc_ch0_clk(void)
 704 {
 705         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 706         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 707
 708         u32 freq, podf, per2_clk2_podf;
 709
 710         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
 711             is_cpu_type(MXC_CPU_MX6SL)) {
 712                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 713                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 714                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 715                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 716                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 717                         if (is_cpu_type(MXC_CPU_MX6SL)) {
 718                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 719                                         freq = MXC_HCLK;
 720                                 else
 721                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 722                         } else {
 723                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 724                                         freq = decode_pll(PLL_528, MXC_HCLK);
 725                                 else
 726                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 727                         }
 728                 } else {
 729                         per2_clk2_podf = 0;
 730                         switch ((cbcmr &
 731                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 732                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 733                         case 0:
 734                                 freq = decode_pll(PLL_528, MXC_HCLK);
 735                                 break;
 736                         case 1:
 737                                 freq = mxc_get_pll_pfd(PLL_528, 2);
 738                                 break;
 739                         case 2:
 740                                 freq = mxc_get_pll_pfd(PLL_528, 0);
 741                                 break;
 742                         case 3:
 743                                 /* static / 2 divider */
 744                                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
 745                                 break;
 746                         }
 747                 }
 748                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 749         } else {
 750                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 751                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 752                 return get_periph_clk() / (podf + 1);
 753         }
 754 }
 755
 756 #ifdef CONFIG_FSL_QSPI
 757 /* qspi_num can be from 0 - 1 */
 758 void enable_qspi_clk(int qspi_num)
 759 {
 760         u32 reg = 0;
 761         /* Enable QuadSPI clock */
 762         switch (qspi_num) {
 763         case 0:
 764                 /* disable the clock gate */
 765                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 766
 767                 /* set 50M  : (50 = 396 / 2 / 4) */
 768                 reg = readl(&imx_ccm->cscmr1);
 769                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 770                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 771                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 772                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 773                 writel(reg, &imx_ccm->cscmr1);
 774
 775                 /* enable the clock gate */
 776                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 777                 break;
 778         case 1:
 779                 /*
 780                  * disable the clock gate
 781                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 782                  * disable both of them.
 783                  */
 784                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 785                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 786
 787                 /* set 50M  : (50 = 396 / 2 / 4) */
 788                 reg = readl(&imx_ccm->cs2cdr);
 789                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 790                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 791                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 792                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 793                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 794                 writel(reg, &imx_ccm->cs2cdr);
 795
 796                 /*enable the clock gate*/
 797                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 798                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 799                 break;
 800         default:
 801                 break;
 802         }
 803 }
 804 #endif
 805
 806 #ifdef CONFIG_FEC_MXC
 807 int enable_fec_anatop_clock(enum enet_freq freq)
 808 {
 809         u32 reg = 0;
 810         s32 timeout = 100000;
 811
 812         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 813                 return -EINVAL;
 814
 815         reg = readl(&anatop->pll_enet);
 816         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 817         reg |= freq;
 818
 819         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 820             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 821                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 822                 writel(reg, &anatop->pll_enet);
 823                 while (timeout--) {
 824                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 825                                 break;
 826                 }
 827                 if (timeout < 0)
 828                         return -ETIMEDOUT;
 829         }
 830
 831         /* Enable FEC clock */
 832         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 833         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 834         writel(reg, &anatop->pll_enet);
 835
 836 #ifdef CONFIG_SOC_MX6SX
 837         /*
 838          * Set enet ahb clock to 200MHz
 839          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 840          */
 841         reg = readl(&imx_ccm->chsccdr);
 842         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 843                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 844                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 845         /* PLL2 PFD2 */
 846         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 847         /* Div = 2*/
 848         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 849         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 850         writel(reg, &imx_ccm->chsccdr);
 851
 852         /* Enable enet system clock */
 853         reg = readl(&imx_ccm->CCGR3);
 854         reg |= MXC_CCM_CCGR3_ENET_MASK;
 855         writel(reg, &imx_ccm->CCGR3);
 856 #endif
 857         return 0;
 858 }
 859 #endif
 860
 861 static u32 get_usdhc_clk(u32 port)
 862 {
 863         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 864         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 865         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 866
 867         switch (port) {
 868         case 0:
 869                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 870                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 871                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 872
 873                 break;
 874         case 1:
 875                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 876                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 877                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 878
 879                 break;
 880         case 2:
 881                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 882                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 883                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 884
 885                 break;
 886         case 3:
 887                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 888                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 889                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 890
 891                 break;
 892         default:
 893                 break;
 894         }
 895
 896         if (clk_sel)
 897                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 898         else
 899                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 900
 901         return root_freq / (usdhc_podf + 1);
 902 }
 903
 904 u32 imx_get_uartclk(void)
 905 {
 906         return get_uart_clk();
 907 }
 908
 909 u32 imx_get_fecclk(void)
 910 {
 911         return mxc_get_clock(MXC_IPG_CLK);
 912 }
 913
 914 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 915 static int enable_enet_pll(uint32_t en)
 916 {
 917         u32 reg;
 918         s32 timeout = 100000;
 919
 920         /* Enable PLLs */
 921         reg = readl(&anatop->pll_enet);
 922         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 923         writel(reg, &anatop->pll_enet);
 924         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 925         while (timeout--) {
 926                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 927                         break;
 928         }
 929         if (timeout <= 0)
 930                 return -EIO;
 931         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 932         writel(reg, &anatop->pll_enet);
 933         reg |= en;
 934         writel(reg, &anatop->pll_enet);
 935         return 0;
 936 }
 937 #endif
 938
 939 #ifdef CONFIG_CMD_SATA
 940 static void ungate_sata_clock(void)
 941 {
 942         /* Enable SATA clock. */
 943         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 944 }
 945
 946 int enable_sata_clock(void)
 947 {
 948         ungate_sata_clock();
 949         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 950 }
 951
 952 void disable_sata_clock(void)
 953 {
 954         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 955 }
 956 #endif
 957
 958 #ifdef CONFIG_PCIE_IMX
 959 static void ungate_pcie_clock(void)
 960 {
 961         /* Enable PCIe clock. */
 962         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 963 }
 964
 965 int enable_pcie_clock(void)
 966 {
 967         u32 lvds1_clk_sel;
 968
 969         /*
 970          * Here be dragons!
 971          *
 972          * The register ANATOP_MISC1 is not documented in the Freescale
 973          * MX6RM. The register that is mapped in the ANATOP space and
 974          * marked as ANATOP_MISC1 is actually documented in the PMU section
 975          * of the datasheet as PMU_MISC1.
 976          *
 977          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 978          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 979          * for PCI express link that is clocked from the i.MX6.
 980          */
 981 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
 982 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
 983 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
 984 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
 985 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
 986
 987         if (is_cpu_type(MXC_CPU_MX6SX))
 988                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 989         else
 990                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
 991
 992         clrsetbits_le32(&anatop_regs->ana_misc1,
 993                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 994                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 995                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 996
 997         /* PCIe reference clock sourced from AXI. */
 998         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 999
1000         /* Party time! Ungate the clock to the PCIe. */
1001 #ifdef CONFIG_CMD_SATA
1002         ungate_sata_clock();
1003 #endif
1004         ungate_pcie_clock();
1005
1006         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1007                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1008 }
1009 #endif
1010
1011 #ifdef CONFIG_SECURE_BOOT
1012 void hab_caam_clock_enable(unsigned char enable)
1013 {
1014         u32 reg;
1015
1016         /* CG4 ~ CG6, CAAM clocks */
1017         reg = __raw_readl(&imx_ccm->CCGR0);
1018         if (enable)
1019                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1020                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1021                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1022         else
1023                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1024                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1025                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1026         __raw_writel(reg, &imx_ccm->CCGR0);
1027
1028         /* EMI slow clk */
1029         reg = __raw_readl(&imx_ccm->CCGR6);
1030         if (enable)
1031                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1032         else
1033                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1034         __raw_writel(reg, &imx_ccm->CCGR6);
1035 }
1036 #endif
1037
1038 static void enable_pll3(void)
1039 {
1040         /* make sure pll3 is enabled */
1041         if ((readl(&anatop->usb1_pll_480_ctrl) &
1042                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1043                 /* enable pll's power */
1044                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1045                        &anatop->usb1_pll_480_ctrl_set);
1046                 writel(0x80, &anatop->ana_misc2_clr);
1047                 /* wait for pll lock */
1048                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1049                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1050                         ;
1051                 /* disable bypass */
1052                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1053                        &anatop->usb1_pll_480_ctrl_clr);
1054                 /* enable pll output */
1055                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1056                        &anatop->usb1_pll_480_ctrl_set);
1057         }
1058 }
1059
1060 void enable_thermal_clk(void)
1061 {
1062         enable_pll3();
1063 }
1064
1065 void ipu_clk_enable(void)
1066 {
1067         u32 reg = readl(&imx_ccm->CCGR3);
1068         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1069         writel(reg, &imx_ccm->CCGR3);
1070 }
1071
1072 void ipu_clk_disable(void)
1073 {
1074         u32 reg = readl(&imx_ccm->CCGR3);
1075         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1076         writel(reg, &imx_ccm->CCGR3);
1077 }
1078
1079 void ipu_di_clk_enable(int di)
1080 {
1081         switch (di) {
1082         case 0:
1083                 setbits_le32(&imx_ccm->CCGR3,
1084                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1085                 break;
1086         case 1:
1087                 setbits_le32(&imx_ccm->CCGR3,
1088                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1089                 break;
1090         default:
1091                 printf("%s: Invalid DI index %d\n", __func__, di);
1092         }
1093 }
1094
1095 void ipu_di_clk_disable(int di)
1096 {
1097         switch (di) {
1098         case 0:
1099                 clrbits_le32(&imx_ccm->CCGR3,
1100                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1101                 break;
1102         case 1:
1103                 clrbits_le32(&imx_ccm->CCGR3,
1104                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1105                 break;
1106         default:
1107                 printf("%s: Invalid DI index %d\n", __func__, di);
1108         }
1109 }
1110
1111 void ldb_clk_enable(int ldb)
1112 {
1113         switch (ldb) {
1114         case 0:
1115                 setbits_le32(&imx_ccm->CCGR3,
1116                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1117                 break;
1118         case 1:
1119                 setbits_le32(&imx_ccm->CCGR3,
1120                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1121                 break;
1122         default:
1123                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1124         }
1125 }
1126
1127 void ldb_clk_disable(int ldb)
1128 {
1129         switch (ldb) {
1130         case 0:
1131                 clrbits_le32(&imx_ccm->CCGR3,
1132                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1133                 break;
1134         case 1:
1135                 clrbits_le32(&imx_ccm->CCGR3,
1136                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1137                 break;
1138         default:
1139                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1140         }
1141 }
1142
1143 #ifdef CONFIG_VIDEO_MXS
1144 void lcdif_clk_enable(void)
1145 {
1146         setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1147         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1148 }
1149
1150 void lcdif_clk_disable(void)
1151 {
1152         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1153         clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1154 }
1155
1156 #define CBCMR_LCDIF_MASK        MXC_CCM_CBCMR_LCDIF_PODF_MASK
1157 #define CSCDR2_LCDIF_MASK       (MXC_CCM_CSCDR2_LCDIF_PRED_MASK |       \
1158                                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK)
1159
1160 static u32 get_lcdif_root_clk(u32 cscdr2)
1161 {
1162         int lcdif_pre_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) >>
1163                 MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET;
1164         int lcdif_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK) >>
1165                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET;
1166         u32 root_freq;
1167
1168         switch (lcdif_clk_sel) {
1169         case 0:
1170                 switch (lcdif_pre_clk_sel) {
1171                 case 0:
1172                         root_freq = decode_pll(PLL_528, MXC_HCLK);
1173                         break;
1174                 case 1:
1175                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
1176                         break;
1177                 case 2:
1178                         root_freq = decode_pll(PLL_VIDEO, MXC_HCLK);
1179                         break;
1180                 case 3:
1181                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
1182                         break;
1183                 case 4:
1184                         root_freq = mxc_get_pll_pfd(PLL_528, 1);
1185                         break;
1186                 case 5:
1187                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
1188                         break;
1189                 default:
1190                         return 0;
1191                 }
1192                 break;
1193         case 1:
1194                 root_freq = mxc_get_pll_pfd(PLL_VIDEO, 0);
1195                 break;
1196         case 2:
1197                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1198                 break;
1199         case 3:
1200                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
1201                 break;
1202         default:
1203                 return 0;
1204         }
1205
1206         return root_freq;
1207 }
1208
1209 static int set_lcdif_pll(u32 ref, u32 freq_khz,
1210                         unsigned post_div)
1211 {
1212         int ret;
1213         u64 freq = freq_khz * 1000;
1214         u32 post_div_mask = 1 << (2 - post_div);
1215         int mul = 1;
1216         u32 min_err = ~0;
1217         u32 reg;
1218         int num = 0;
1219         int denom = 1;
1220         const int min_div = 27;
1221         const int max_div = 54;
1222         const int div_mask = 0x7f;
1223         const u32 max_freq = ref * max_div / post_div;
1224         const u32 min_freq = ref * min_div / post_div;
1225
1226         if (freq > max_freq || freq < min_freq) {
1227                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03uMHz\n",
1228                         freq_khz / 1000, freq_khz % 1000,
1229                         min_freq / 1000000, min_freq / 1000 % 1000,
1230                         max_freq / 1000000, max_freq / 1000 % 1000);
1231                 return -EINVAL;
1232         }
1233         {
1234                 int d = post_div;
1235                 int m = lldiv(freq * d + ref - 1, ref);
1236                 u32 err;
1237                 u32 f;
1238
1239                 debug("%s@%d: d=%d m=%d max_div=%u min_div=%u\n", __func__, __LINE__,
1240                         d, m, max_div, min_div);
1241                 if (m > max_div || m < min_div)
1242                         return -EINVAL;
1243
1244                 f = ref * m / d;
1245                 if (f > freq) {
1246                         debug("%s@%d: d=%d m=%d f=%u freq=%llu\n", __func__, __LINE__,
1247                                 d, m, f, freq);
1248                         return -EINVAL;
1249                 }
1250                 err = freq - f;
1251                 debug("%s@%d: d=%d m=%d f=%u freq=%llu err=%d\n", __func__, __LINE__,
1252                         d, m, f, freq, err);
1253                 if (err < min_err) {
1254                         mul = m;
1255                         min_err = err;
1256                 }
1257         }
1258         if (min_err == ~0) {
1259                 printf("Cannot set VIDEO PLL to %u.%03uMHz\n",
1260                         freq_khz / 1000, freq_khz % 1000);
1261                 return -EINVAL;
1262         }
1263
1264         debug("Setting M=%3u D=%u N=%d DE=%u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1265                 mul, post_div, num, denom,
1266                 freq_khz / post_div / 1000, freq_khz / post_div % 1000,
1267                 ref * mul / post_div / 1000000,
1268                 ref * mul / post_div / 1000 % 1000);
1269
1270         reg = readl(&anatop->pll_video);
1271         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1272
1273         reg = (reg & ~(div_mask |
1274                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)) |
1275                 mul | (post_div_mask << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT);
1276         writel(reg, &anatop->pll_video);
1277
1278         ret = wait_pll_lock(&anatop->pll_video);
1279         if (ret) {
1280                 printf("Video PLL failed to lock\n");
1281                 return ret;
1282         }
1283
1284         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1285         return 0;
1286 }
1287
1288 static int set_lcdif_clk(u32 ref, u32 freq_khz)
1289 {
1290         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1291         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1292         u32 cbcmr_val;
1293         u32 cscdr2_val;
1294         u32 freq = freq_khz * 1000;
1295         u32 act_freq;
1296         u32 err;
1297         u32 min_div = 27;
1298         u32 max_div = 54;
1299         u32 min_pll_khz = ref * min_div / 4 / 1000;
1300         u32 max_pll_khz = ref * max_div / 1000;
1301         u32 pll_khz;
1302         u32 post_div = 0;
1303         u32 m;
1304         u32 min_err = ~0;
1305         u32 best_m = 0;
1306         u32 best_pred = 1;
1307         u32 best_podf = 1;
1308         u32 div;
1309         unsigned pd;
1310
1311         if (freq_khz > max_pll_khz)
1312                 return -EINVAL;
1313
1314         for (pd = 1; min_err && pd <= 4; pd <<= 1) {
1315                 for (m = max(min_div, DIV_ROUND_UP(648000 / pd, freq_khz * 64));
1316                      m <= max_div; m++) {
1317                         u32 err;
1318                         int pred = 0;
1319                         int podf = 0;
1320                         u32 root_freq = ref * m / pd;
1321
1322                         div = DIV_ROUND_UP(root_freq, freq);
1323
1324                         while (pred * podf == 0 && div <= 64) {
1325                                 int p1, p2;
1326
1327                                 for (p1 = 1; p1 <= 8; p1++) {
1328                                         for (p2 = 1; p2 <= 8; p2++) {
1329                                                 if (p1 * p2 == div) {
1330                                                         podf = p1;
1331                                                         pred = p2;
1332                                                         break;
1333                                                 }
1334                                         }
1335                                 }
1336                                 if (pred * podf == 0) {
1337                                         div++;
1338                                 }
1339                         }
1340                         if (pred * podf == 0)
1341                                 continue;
1342
1343                         /* relative error in per mille */
1344                         act_freq = root_freq / div;
1345                         err = abs(act_freq - freq) / freq_khz;
1346
1347                         if (err < min_err) {
1348                                 best_m = m;
1349                                 best_pred = pred;
1350                                 best_podf = podf;
1351                                 post_div = pd;
1352                                 min_err = err;
1353                                 if (err <= 10)
1354                                         break;
1355                         }
1356                 }
1357         }
1358         if (min_err > 50)
1359                 return -EINVAL;
1360
1361         pll_khz = ref / 1000 * best_m;
1362         if (pll_khz > max_pll_khz)
1363                 return -EINVAL;
1364
1365         if (pll_khz < min_pll_khz)
1366                 return -EINVAL;
1367
1368         err = set_lcdif_pll(ref, pll_khz / post_div, post_div);
1369         if (err)
1370                 return err;
1371
1372         cbcmr_val = (best_podf - 1) << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET;
1373         cscdr2_val = (best_pred - 1) << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET;
1374
1375         if ((cbcmr & CBCMR_LCDIF_MASK) != cbcmr_val) {
1376                 debug("changing cbcmr from %08x to %08x\n", cbcmr,
1377                         (cbcmr & ~CBCMR_LCDIF_MASK) | cbcmr_val);
1378                 clrsetbits_le32(&imx_ccm->cbcmr,
1379                                 CBCMR_LCDIF_MASK,
1380                                 cbcmr_val);
1381         } else {
1382                 debug("Leaving cbcmr unchanged [%08x]\n", cbcmr);
1383         }
1384         if ((cscdr2 & CSCDR2_LCDIF_MASK) != cscdr2_val) {
1385                 debug("changing cscdr2 from %08x to %08x\n", cscdr2,
1386                         (cscdr2 & ~CSCDR2_LCDIF_MASK) | cscdr2_val);
1387                 clrsetbits_le32(&imx_ccm->cscdr2,
1388                                 CSCDR2_LCDIF_MASK,
1389                                 cscdr2_val);
1390         } else {
1391                 debug("Leaving cscdr2 unchanged [%08x]\n", cscdr2);
1392         }
1393         return 0;
1394 }
1395
1396 void mxs_set_lcdclk(u32 khz)
1397 {
1398         set_lcdif_clk(CONFIG_SYS_MX6_HCLK, khz);
1399 }
1400
1401 static u32 get_lcdif_clk(void)
1402 {
1403         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1404         u32 podf = ((cbcmr & MXC_CCM_CBCMR_LCDIF_PODF_MASK) >>
1405                 MXC_CCM_CBCMR_LCDIF_PODF_OFFSET) + 1;
1406         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1407         u32 pred = ((cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRED_MASK) >>
1408                 MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET) + 1;
1409         u32 root_freq = get_lcdif_root_clk(cscdr2);
1410
1411         return root_freq / pred / podf;
1412 }
1413 #endif
1414
1415 unsigned int mxc_get_clock(enum mxc_clock clk)
1416 {
1417         switch (clk) {
1418         case MXC_ARM_CLK:
1419                 return get_mcu_main_clk();
1420         case MXC_PER_CLK:
1421                 return get_periph_clk();
1422         case MXC_AHB_CLK:
1423                 return get_ahb_clk();
1424         case MXC_IPG_CLK:
1425                 return get_ipg_clk();
1426         case MXC_IPG_PERCLK:
1427         case MXC_I2C_CLK:
1428                 return get_ipg_per_clk();
1429         case MXC_UART_CLK:
1430                 return get_uart_clk();
1431         case MXC_CSPI_CLK:
1432                 return get_cspi_clk();
1433         case MXC_AXI_CLK:
1434                 return get_axi_clk();
1435         case MXC_EMI_SLOW_CLK:
1436                 return get_emi_slow_clk();
1437         case MXC_DDR_CLK:
1438                 return get_mmdc_ch0_clk();
1439         case MXC_ESDHC_CLK:
1440                 return get_usdhc_clk(0);
1441         case MXC_ESDHC2_CLK:
1442                 return get_usdhc_clk(1);
1443         case MXC_ESDHC3_CLK:
1444                 return get_usdhc_clk(2);
1445         case MXC_ESDHC4_CLK:
1446                 return get_usdhc_clk(3);
1447         case MXC_SATA_CLK:
1448                 return get_ahb_clk();
1449         case MXC_NFC_CLK:
1450                 return get_nfc_clk();
1451 #ifdef CONFIG_VIDEO_MXS
1452         case MXC_LCDIF_CLK:
1453                 return get_lcdif_clk();
1454 #endif
1455         default:
1456                 printf("Unsupported MXC CLK: %d\n", clk);
1457         }
1458
1459         return 0;
1460 }
1461
1462 /* Config CPU clock */
1463 static int set_arm_clk(u32 ref, u32 freq_khz)
1464 {
1465         int ret;
1466         int d;
1467         int div = 0;
1468         int mul = 0;
1469         u32 min_err = ~0;
1470         u32 reg;
1471         const int min_div = 54;
1472         const int max_div = 108;
1473         const int div_mask = 0x7f;
1474         const u32 max_freq = ref * max_div / 2;
1475         const u32 min_freq = ref * min_div / 8 / 2;
1476
1477         if (freq_khz > max_freq / 1000 || freq_khz < min_freq / 1000) {
1478                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1479                         freq_khz / 1000, freq_khz % 1000,
1480                         min_freq / 1000000, min_freq / 1000 % 1000,
1481                         max_freq / 1000000, max_freq / 1000 % 1000);
1482                 return -EINVAL;
1483         }
1484
1485         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1486                 int m = freq_khz * 2 * d / (ref / 1000);
1487                 u32 f;
1488                 u32 err;
1489
1490                 if (m > max_div) {
1491                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1492                                 d, m);
1493                         break;
1494                 }
1495
1496                 f = ref * m / d / 2;
1497                 if (f > freq_khz * 1000) {
1498                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1499                                 d, m, f, freq_khz);
1500                         if (--m < min_div)
1501                                 return -EINVAL;
1502                         f = ref * m / d / 2;
1503                 }
1504                 err = freq_khz * 1000 - f;
1505                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1506                         d, m, f, freq_khz, err);
1507                 if (err < min_err) {
1508                         mul = m;
1509                         div = d;
1510                         min_err = err;
1511                         if (err == 0)
1512                                 break;
1513                 }
1514         }
1515         if (min_err == ~0)
1516                 return -EINVAL;
1517         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1518                 mul, div, freq_khz / 1000, freq_khz % 1000,
1519                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1520
1521         reg = readl(&anatop->pll_arm);
1522         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1523
1524         reg = (reg & ~div_mask) | mul;
1525         writel(reg, &anatop->pll_arm);
1526
1527         writel(div - 1, &imx_ccm->cacrr);
1528
1529         ret = wait_pll_lock(&anatop->pll_video);
1530         if (ret) {
1531                 printf("ARM PLL failed to lock\n");
1532                 return ret;
1533         }
1534
1535         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1536
1537         return 0;
1538 }
1539
1540 /*
1541  * This function assumes the expected core clock has to be changed by
1542  * modifying the PLL. This is NOT true always but for most of the times,
1543  * it is. So it assumes the PLL output freq is the same as the expected
1544  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1545  * In the latter case, it will try to increase the presc value until
1546  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1547  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1548  * on the targeted PLL and reference input clock to the PLL. Lastly,
1549  * it sets the register based on these values along with the dividers.
1550  * Note 1) There is no value checking for the passed-in divider values
1551  *         so the caller has to make sure those values are sensible.
1552  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1553  *         exceed NFC_CLK_MAX.
1554  */
1555 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1556 {
1557         int ret;
1558
1559         freq *= 1000;
1560
1561         switch (clk) {
1562         case MXC_ARM_CLK:
1563                 ret = set_arm_clk(ref, freq);
1564                 break;
1565
1566         case MXC_NFC_CLK:
1567                 ret = set_nfc_clk(ref, freq);
1568                 break;
1569
1570         default:
1571                 printf("Warning: Unsupported or invalid clock type: %d\n",
1572                         clk);
1573                 return -EINVAL;
1574         }
1575
1576         return ret;
1577 }
1578
1579 /*
1580  * Dump some core clocks.
1581  */
1582 #define print_pll(pll)  {                               \
1583         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1584         printf("%-12s %4d.%03d MHz\n", #pll,            \
1585                 __pll / 1000000, __pll / 1000 % 1000);  \
1586         }
1587
1588 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1589
1590 #define print_clk(clk)  {                               \
1591         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1592         printf("%-12s %4d.%03d MHz\n", #clk,            \
1593                 __clk / 1000000, __clk / 1000 % 1000);  \
1594         }
1595
1596 #define print_pfd(pll, pfd)     {                                       \
1597         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1598         if (__pfd & (0x80 << 8 * pfd)) {                                \
1599                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1600         } else {                                                        \
1601                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1602                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1603                         pll * 18 / __pfd,                               \
1604                         pll * 18 * 1000 / __pfd % 1000);                \
1605         }                                                               \
1606 }
1607
1608 static void do_mx6_showclocks(void)
1609 {
1610         print_pll(PLL_ARM);
1611         print_pll(PLL_528);
1612         print_pll(PLL_USBOTG);
1613         print_pll(PLL_AUDIO);
1614         print_pll(PLL_VIDEO);
1615         print_pll(PLL_ENET);
1616         print_pll(PLL_USB2);
1617         printf("\n");
1618
1619         print_pfd(480, 0);
1620         print_pfd(480, 1);
1621         print_pfd(480, 2);
1622         print_pfd(480, 3);
1623         print_pfd(528, 0);
1624         print_pfd(528, 1);
1625         print_pfd(528, 2);
1626         printf("\n");
1627
1628         print_clk(IPG);
1629         print_clk(UART);
1630         print_clk(CSPI);
1631         print_clk(AHB);
1632         print_clk(AXI);
1633         print_clk(DDR);
1634         print_clk(ESDHC);
1635         print_clk(ESDHC2);
1636         print_clk(ESDHC3);
1637         print_clk(ESDHC4);
1638         print_clk(EMI_SLOW);
1639         print_clk(NFC);
1640         print_clk(IPG_PER);
1641         print_clk(ARM);
1642 #ifdef CONFIG_VIDEO_MXS
1643         print_clk(LCDIF);
1644 #endif
1645 }
1646
1647 static struct clk_lookup {
1648         const char *name;
1649         unsigned int index;
1650 } mx6_clk_lookup[] = {
1651         { "arm", MXC_ARM_CLK, },
1652         { "nfc", MXC_NFC_CLK, },
1653 };
1654
1655 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1656 {
1657         int i;
1658         unsigned long freq;
1659         unsigned long ref = ~0UL;
1660
1661         if (argc < 2) {
1662                 do_mx6_showclocks();
1663                 return CMD_RET_SUCCESS;
1664         } else if (argc == 2 || argc > 4) {
1665                 return CMD_RET_USAGE;
1666         }
1667
1668         freq = simple_strtoul(argv[2], NULL, 0);
1669         if (freq == 0) {
1670                 printf("Invalid clock frequency %lu\n", freq);
1671                 return CMD_RET_FAILURE;
1672         }
1673         if (argc > 3) {
1674                 ref = simple_strtoul(argv[3], NULL, 0);
1675         }
1676         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1677                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1678                         switch (mx6_clk_lookup[i].index) {
1679                         case MXC_ARM_CLK:
1680                                 if (argc > 3)
1681                                         return CMD_RET_USAGE;
1682                                 ref = MXC_HCLK;
1683                                 break;
1684
1685                         case MXC_NFC_CLK:
1686                                 if (argc > 3 && ref > 3) {
1687                                         printf("Invalid clock selector value: %lu\n", ref);
1688                                         return CMD_RET_FAILURE;
1689                                 }
1690                                 break;
1691                         }
1692                         printf("Setting %s clock to %lu MHz\n",
1693                                 mx6_clk_lookup[i].name, freq);
1694                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1695                                 break;
1696                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1697                         printf("%s clock set to %lu.%03lu MHz\n",
1698                                 mx6_clk_lookup[i].name,
1699                                 freq / 1000000, freq / 1000 % 1000);
1700                         return CMD_RET_SUCCESS;
1701                 }
1702         }
1703         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1704                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1705                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1706                         printf("\t%s\n", mx6_clk_lookup[i].name);
1707                 }
1708         } else {
1709                 printf("Failed to set clock %s to %s MHz\n",
1710                         argv[1], argv[2]);
1711         }
1712         return CMD_RET_FAILURE;
1713 }
1714
1715 #ifndef CONFIG_SOC_MX6SX
1716 void enable_ipu_clock(void)
1717 {
1718         int reg = readl(&imx_ccm->CCGR3);
1719         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1720         writel(reg, &imx_ccm->CCGR3);
1721
1722         if (is_mx6dqp()) {
1723                 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1724                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1725         }
1726 }
1727 #endif
1728 /***************************************************/
1729
1730 U_BOOT_CMD(
1731         clocks, 4, 0, do_clocks,
1732         "display/set clocks",
1733         "                    - display clock settings\n"
1734         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1735 );