arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_ARM,        /* PLL1: ARM PLL */
  18         PLL_528,        /* PLL2: System Bus PLL*/
  19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
  20         PLL_AUDIO,      /* PLL4: Audio PLL */
  21         PLL_VIDEO,      /* PLL5: Video PLL */
  22         PLL_ENET,       /* PLL6: ENET PLL */
  23         PLL_USB2,       /* PLL7: USB2 PLL */
  24         PLL_MLB,        /* PLL8: MLB PLL */
  25 };
  26
  27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
  28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
  29
  30 int clk_enable(struct clk *clk)
  31 {
  32         int ret = 0;
  33
  34         if (!clk)
  35                 return 0;
  36         if (clk->usecount == 0) {
  37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
  38                 ret = clk->enable(clk);
  39                 if (ret)
  40                         return ret;
  41                 clk->usecount++;
  42         }
  43         assert(clk->usecount > 0);
  44         return ret;
  45 }
  46
  47 void clk_disable(struct clk *clk)
  48 {
  49         if (!clk)
  50                 return;
  51
  52         assert(clk->usecount > 0);
  53         if (!(--clk->usecount)) {
  54                 if (clk->disable) {
  55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
  56                         clk->disable(clk);
  57                 }
  58         }
  59 }
  60
  61 int clk_get_usecount(struct clk *clk)
  62 {
  63         if (clk == NULL)
  64                 return 0;
  65
  66         return clk->usecount;
  67 }
  68
  69 u32 clk_get_rate(struct clk *clk)
  70 {
  71         if (!clk)
  72                 return 0;
  73
  74         return clk->rate;
  75 }
  76
  77 struct clk *clk_get_parent(struct clk *clk)
  78 {
  79         if (!clk)
  80                 return 0;
  81
  82         return clk->parent;
  83 }
  84
  85 int clk_set_rate(struct clk *clk, unsigned long rate)
  86 {
  87         if (clk && clk->set_rate)
  88                 clk->set_rate(clk, rate);
  89         return clk->rate;
  90 }
  91
  92 long clk_round_rate(struct clk *clk, unsigned long rate)
  93 {
  94         if (clk == NULL || !clk->round_rate)
  95                 return 0;
  96
  97         return clk->round_rate(clk, rate);
  98 }
  99
 100 int clk_set_parent(struct clk *clk, struct clk *parent)
 101 {
 102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
 103                 clk ? clk->parent : NULL);
 104
 105         if (!clk || clk == parent)
 106                 return 0;
 107
 108         if (clk->set_parent) {
 109                 int ret;
 110
 111                 ret = clk->set_parent(clk, parent);
 112                 if (ret)
 113                         return ret;
 114         }
 115         clk->parent = parent;
 116         return 0;
 117 }
 118
 119 #define PLL_LOCK_BIT            (1 << 31)
 120
 121 static inline int wait_pll_lock(u32 *reg)
 122 {
 123         int loops = 0;
 124         u32 val;
 125
 126         while (!((val = readl(reg)) & PLL_LOCK_BIT)) {
 127                 loops++;
 128                 if (loops > 1000)
 129                         break;
 130                 udelay(1);
 131         }
 132         if (!(val & PLL_LOCK_BIT) && !(readl(reg) & PLL_LOCK_BIT))
 133                 return -ETIMEDOUT;
 134         return 0;
 135 }
 136
 137 #ifdef CONFIG_MXC_OCOTP
 138 void enable_ocotp_clk(unsigned char enable)
 139 {
 140         u32 reg;
 141         static int enabled __attribute__((section(".data")));
 142
 143         if (enabled < 0) {
 144                 printf("ERROR: unbalanced enable/disable ocotp_clk\n");
 145                 hang();
 146         }
 147         if (enable && enabled++)
 148                 return;
 149         if (!enable && --enabled)
 150                 return;
 151
 152         reg = __raw_readl(&imx_ccm->CCGR2);
 153         if (enable)
 154                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 155         else
 156                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 157         __raw_writel(reg, &imx_ccm->CCGR2);
 158 }
 159 #endif
 160
 161 #ifdef CONFIG_NAND_MXS
 162 void setup_gpmi_io_clk(u32 cfg)
 163 {
 164         /* Disable clocks per ERR007177 from MX6 errata */
 165         clrbits_le32(&imx_ccm->CCGR4,
 166                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 167                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 168                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 169                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 170                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 171
 172         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 173
 174         clrsetbits_le32(&imx_ccm->cs2cdr,
 175                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 176                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 177                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 178                         cfg);
 179
 180         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 181         setbits_le32(&imx_ccm->CCGR4,
 182                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 183                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 184                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 185                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 186                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 187 }
 188 #endif
 189
 190 void enable_usboh3_clk(unsigned char enable)
 191 {
 192         u32 reg;
 193
 194         reg = __raw_readl(&imx_ccm->CCGR6);
 195         if (enable)
 196                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
 197         else
 198                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
 199         __raw_writel(reg, &imx_ccm->CCGR6);
 200
 201 }
 202
 203 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 204 void enable_enet_clk(unsigned char enable)
 205 {
 206         u32 mask, *addr;
 207
 208         if (is_cpu_type(MXC_CPU_MX6UL)) {
 209                 mask = MXC_CCM_CCGR3_ENET_MASK;
 210                 addr = &imx_ccm->CCGR3;
 211         } else {
 212                 mask = MXC_CCM_CCGR1_ENET_MASK;
 213                 addr = &imx_ccm->CCGR1;
 214         }
 215
 216         if (enable)
 217                 setbits_le32(addr, mask);
 218         else
 219                 clrbits_le32(addr, mask);
 220 }
 221 #endif
 222
 223 #ifdef CONFIG_MXC_UART
 224 void enable_uart_clk(unsigned char enable)
 225 {
 226         u32 mask;
 227
 228         if (is_cpu_type(MXC_CPU_MX6UL))
 229                 mask = MXC_CCM_CCGR5_UART_MASK;
 230         else
 231                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 232
 233         if (enable)
 234                 setbits_le32(&imx_ccm->CCGR5, mask);
 235         else
 236                 clrbits_le32(&imx_ccm->CCGR5, mask);
 237 }
 238 #endif
 239
 240 #ifdef CONFIG_MMC
 241 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 242 {
 243         u32 mask;
 244
 245         if (bus_num > 3)
 246                 return -EINVAL;
 247
 248         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 249         if (enable)
 250                 setbits_le32(&imx_ccm->CCGR6, mask);
 251         else
 252                 clrbits_le32(&imx_ccm->CCGR6, mask);
 253
 254         return 0;
 255 }
 256 #endif
 257
 258 #ifdef CONFIG_SYS_I2C_MXC
 259 /* i2c_num can be from 0 - 3 */
 260 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 261 {
 262         u32 reg;
 263         u32 mask;
 264         u32 *addr;
 265
 266         if (i2c_num > 3)
 267                 return -EINVAL;
 268         if (i2c_num < 3) {
 269                 mask = MXC_CCM_CCGR_CG_MASK
 270                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 271                         + (i2c_num << 1));
 272                 reg = __raw_readl(&imx_ccm->CCGR2);
 273                 if (enable)
 274                         reg |= mask;
 275                 else
 276                         reg &= ~mask;
 277                 __raw_writel(reg, &imx_ccm->CCGR2);
 278         } else {
 279                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 280                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 281                         addr = &imx_ccm->CCGR6;
 282                 } else {
 283                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 284                         addr = &imx_ccm->CCGR1;
 285                 }
 286                 reg = __raw_readl(addr);
 287                 if (enable)
 288                         reg |= mask;
 289                 else
 290                         reg &= ~mask;
 291                 __raw_writel(reg, addr);
 292         }
 293         return 0;
 294 }
 295 #endif
 296
 297 /* spi_num can be from 0 - SPI_MAX_NUM */
 298 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 299 {
 300         u32 reg;
 301         u32 mask;
 302
 303         if (spi_num > SPI_MAX_NUM)
 304                 return -EINVAL;
 305
 306         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 307         reg = __raw_readl(&imx_ccm->CCGR1);
 308         if (enable)
 309                 reg |= mask;
 310         else
 311                 reg &= ~mask;
 312         __raw_writel(reg, &imx_ccm->CCGR1);
 313         return 0;
 314 }
 315
 316 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 317 {
 318         u32 div, post_div;
 319         u32 pll_num, pll_denom;
 320         u64 freq;
 321
 322         switch (pll) {
 323         case PLL_ARM:
 324                 div = __raw_readl(&anatop->pll_arm);
 325                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
 326                         /* Assume the bypass clock is always derived from OSC */
 327                         return infreq;
 328                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
 329
 330                 return infreq * div / 2;
 331         case PLL_528:
 332                 div = __raw_readl(&anatop->pll_528);
 333                 if (div & BM_ANADIG_PLL_528_BYPASS)
 334                         return infreq;
 335                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 336
 337                 return infreq * (20 + div * 2);
 338         case PLL_USBOTG:
 339                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
 340                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 341                         return infreq;
 342                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 343
 344                 return infreq * (20 + div * 2);
 345         case PLL_AUDIO:
 346                 div = __raw_readl(&anatop->pll_audio);
 347                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 348                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 349                         return infreq;
 350
 351                 pll_num = __raw_readl(&anatop->pll_audio_num);
 352                 pll_denom = __raw_readl(&anatop->pll_audio_denom);
 353
 354                 post_div = (div & BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT) >>
 355                         BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT;
 356                 if (post_div == 3) {
 357                         printf("Invalid post divider value for PLL_AUDIO\n");
 358                         return 0;
 359                 }
 360                 post_div = 1 << (2 - post_div);
 361                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 362
 363                 freq = (u64)infreq * pll_num / pll_denom;
 364                 freq += infreq * div;
 365                 return lldiv(freq, post_div);
 366         case PLL_VIDEO:
 367                 div = __raw_readl(&anatop->pll_video);
 368                 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
 369                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 370                         return infreq;
 371
 372                 pll_num = __raw_readl(&anatop->pll_video_num);
 373                 pll_denom = __raw_readl(&anatop->pll_video_denom);
 374
 375                 post_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
 376                         BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 377                 if (post_div == 3) {
 378                         printf("Invalid post divider value for PLL_VIDEO\n");
 379                         return 0;
 380                 }
 381                 post_div = 1 << (2 - post_div);
 382                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 383
 384                 freq = (u64)infreq * pll_num / pll_denom;
 385                 freq += infreq * div;
 386                 return lldiv(freq, post_div);
 387         case PLL_ENET:
 388                 div = __raw_readl(&anatop->pll_enet);
 389                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
 390                         return infreq;
 391                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 392
 393                 return 25000000 * (div + (div >> 1) + 1);
 394         case PLL_USB2:
 395                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
 396                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 397                         return infreq;
 398                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 399
 400                 return infreq * (20 + div * 2);
 401         case PLL_MLB:
 402                 div = __raw_readl(&anatop->pll_mlb);
 403                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
 404                         return infreq;
 405                 /* fallthru: unknown external clock provided on MLB_CLK pin */
 406         default:
 407                 return 0;
 408         }
 409         /* NOTREACHED */
 410 }
 411
 412 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 413 {
 414         u32 div;
 415         u64 freq;
 416
 417         switch (pll) {
 418         case PLL_528:
 419                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
 420                         if (pfd_num == 3) {
 421                                 /* No PFD3 on PPL2 */
 422                                 return 0;
 423                         }
 424                 }
 425                 div = __raw_readl(&anatop->pfd_528);
 426                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
 427                 break;
 428         case PLL_USBOTG:
 429                 div = __raw_readl(&anatop->pfd_480);
 430                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 431                 break;
 432         default:
 433                 /* No PFD on other PLL */
 434                 return 0;
 435         }
 436
 437         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 438                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 439 }
 440
 441 static u32 get_mcu_main_clk(void)
 442 {
 443         u32 reg, freq;
 444
 445         reg = __raw_readl(&imx_ccm->cacrr);
 446         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 447         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 448         freq = decode_pll(PLL_ARM, MXC_HCLK);
 449
 450         return freq / (reg + 1);
 451 }
 452
 453 u32 get_periph_clk(void)
 454 {
 455         u32 reg, div = 0, freq = 0;
 456
 457         reg = __raw_readl(&imx_ccm->cbcdr);
 458         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 459                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 460                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 461                 reg = __raw_readl(&imx_ccm->cbcmr);
 462                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 463                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 464
 465                 switch (reg) {
 466                 case 0:
 467                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 468                         break;
 469                 case 1:
 470                 case 2:
 471                         freq = MXC_HCLK;
 472                         break;
 473                 }
 474         } else {
 475                 reg = __raw_readl(&imx_ccm->cbcmr);
 476                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 477                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 478
 479                 switch (reg) {
 480                 case 0:
 481                         freq = decode_pll(PLL_528, MXC_HCLK);
 482                         break;
 483                 case 1:
 484                         freq = mxc_get_pll_pfd(PLL_528, 2);
 485                         break;
 486                 case 2:
 487                         freq = mxc_get_pll_pfd(PLL_528, 0);
 488                         break;
 489                 case 3:
 490                         /* static / 2 divider */
 491                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
 492                         break;
 493                 }
 494         }
 495
 496         return freq / (div + 1);
 497 }
 498
 499 static u32 get_ipg_clk(void)
 500 {
 501         u32 reg, ipg_podf;
 502
 503         reg = __raw_readl(&imx_ccm->cbcdr);
 504         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 505         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 506
 507         return get_ahb_clk() / (ipg_podf + 1);
 508 }
 509
 510 static u32 get_ipg_per_clk(void)
 511 {
 512         u32 reg, perclk_podf;
 513
 514         reg = __raw_readl(&imx_ccm->cscmr1);
 515         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 516             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 517                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 518                         return MXC_HCLK; /* OSC 24Mhz */
 519         }
 520
 521         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 522
 523         return get_ipg_clk() / (perclk_podf + 1);
 524 }
 525
 526 static u32 get_uart_clk(void)
 527 {
 528         u32 reg, uart_podf;
 529         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 530         reg = __raw_readl(&imx_ccm->cscdr1);
 531
 532         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 533             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 534                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 535                         freq = MXC_HCLK;
 536         }
 537
 538         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 539         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 540
 541         return freq / (uart_podf + 1);
 542 }
 543
 544 static u32 get_cspi_clk(void)
 545 {
 546         u32 reg, cspi_podf;
 547
 548         reg = __raw_readl(&imx_ccm->cscdr2);
 549         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 550                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 551
 552         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
 553             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 554                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 555                         return MXC_HCLK / (cspi_podf + 1);
 556         }
 557
 558         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 559 }
 560
 561 static u32 get_axi_clk(void)
 562 {
 563         u32 root_freq, axi_podf;
 564         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 565
 566         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 567         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 568
 569         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 570                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 571                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 572                 else
 573                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 574         } else {
 575                 root_freq = get_periph_clk();
 576         }
 577         return  root_freq / (axi_podf + 1);
 578 }
 579
 580 static u32 get_emi_slow_clk(void)
 581 {
 582         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 583
 584         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 585         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 586         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 587         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 588         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 589
 590         switch (emi_clk_sel) {
 591         case 0:
 592                 root_freq = get_axi_clk();
 593                 break;
 594         case 1:
 595                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 596                 break;
 597         case 2:
 598                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
 599                 break;
 600         case 3:
 601                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
 602                 break;
 603         }
 604
 605         return root_freq / (emi_slow_podf + 1);
 606 }
 607
 608 static inline unsigned long get_nfc_root_clk(int nfc_clk_sel)
 609 {
 610         switch (nfc_clk_sel) {
 611         case 0:
 612                 return mxc_get_pll_pfd(PLL_528, 0);
 613                 break;
 614         case 1:
 615                 return decode_pll(PLL_528, MXC_HCLK);
 616                 break;
 617         case 2:
 618                 return decode_pll(PLL_USBOTG, MXC_HCLK);
 619                 break;
 620         case 3:
 621                 return mxc_get_pll_pfd(PLL_528, 2);
 622                 break;
 623         case 4:
 624                 return mxc_get_pll_pfd(PLL_USBOTG, 3);
 625         default:
 626                 return 0;
 627         }
 628 }
 629
 630 static u32 get_nfc_clk(void)
 631 {
 632         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 633         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
 634                 MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 635         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
 636                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 637         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
 638                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 639         u32 root_freq = get_nfc_root_clk(nfc_clk_sel);
 640
 641         return root_freq / (pred + 1) / (podf + 1);
 642 }
 643
 644 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
 645                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
 646                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
 647
 648 static int set_nfc_clk(u32 ref, u32 freq_khz)
 649 {
 650         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 651         u32 podf;
 652         u32 pred;
 653         int nfc_clk_sel;
 654         u32 root_freq;
 655         u32 min_err = ~0;
 656         u32 nfc_val = ~0;
 657         u32 freq = freq_khz * 1000;
 658         int num_sel = is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) ? 5 : 4;
 659
 660         for (nfc_clk_sel = 0; nfc_clk_sel < num_sel; nfc_clk_sel++) {
 661                 u32 act_freq;
 662                 u32 err;
 663
 664                 if (ref < num_sel && ref != nfc_clk_sel)
 665                         continue;
 666
 667                 switch (nfc_clk_sel) {
 668                 case 0:
 669                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
 670                         break;
 671                 case 1:
 672                         root_freq = decode_pll(PLL_528, MXC_HCLK);
 673                         break;
 674                 case 2:
 675                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 676                         break;
 677                 case 3:
 678                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 679                         break;
 680                 case 4:
 681                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
 682                         break;
 683                 }
 684                 if (root_freq < freq)
 685                         continue;
 686
 687                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
 688                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
 689                 act_freq = root_freq / pred / podf;
 690                 err = (freq - act_freq) / (freq / 1000);
 691                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
 692                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
 693                 if (act_freq > freq)
 694                         continue;
 695                 if (err < min_err) {
 696                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 697                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 698                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 699                         min_err = err;
 700                         if (err == 0)
 701                                 break;
 702                 }
 703         }
 704
 705         if (nfc_val == ~0 || min_err > 100)
 706                 return -EINVAL;
 707
 708         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
 709                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
 710                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
 711 #ifdef CONFIG_NAND_MXS
 712                 setup_gpmi_io_clk(nfc_val);
 713 #else
 714                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
 715                         &imx_ccm->cs2cdr);
 716 #endif
 717         } else {
 718                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
 719         }
 720         return 0;
 721 }
 722
 723 static u32 get_mmdc_ch0_clk(void)
 724 {
 725         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 726         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 727
 728         u32 freq, podf, per2_clk2_podf;
 729
 730         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
 731             is_cpu_type(MXC_CPU_MX6SL)) {
 732                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 733                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 734                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 735                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 736                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 737                         if (is_cpu_type(MXC_CPU_MX6SL)) {
 738                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 739                                         freq = MXC_HCLK;
 740                                 else
 741                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 742                         } else {
 743                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 744                                         freq = decode_pll(PLL_528, MXC_HCLK);
 745                                 else
 746                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 747                         }
 748                 } else {
 749                         per2_clk2_podf = 0;
 750                         switch ((cbcmr &
 751                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 752                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 753                         case 0:
 754                                 freq = decode_pll(PLL_528, MXC_HCLK);
 755                                 break;
 756                         case 1:
 757                                 freq = mxc_get_pll_pfd(PLL_528, 2);
 758                                 break;
 759                         case 2:
 760                                 freq = mxc_get_pll_pfd(PLL_528, 0);
 761                                 break;
 762                         case 3:
 763                                 /* static / 2 divider */
 764                                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
 765                                 break;
 766                         }
 767                 }
 768                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 769         } else {
 770                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 771                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 772                 return get_periph_clk() / (podf + 1);
 773         }
 774 }
 775
 776 #ifdef CONFIG_FSL_QSPI
 777 /* qspi_num can be from 0 - 1 */
 778 void enable_qspi_clk(int qspi_num)
 779 {
 780         u32 reg = 0;
 781         /* Enable QuadSPI clock */
 782         switch (qspi_num) {
 783         case 0:
 784                 /* disable the clock gate */
 785                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 786
 787                 /* set 50M  : (50 = 396 / 2 / 4) */
 788                 reg = readl(&imx_ccm->cscmr1);
 789                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 790                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 791                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 792                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 793                 writel(reg, &imx_ccm->cscmr1);
 794
 795                 /* enable the clock gate */
 796                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 797                 break;
 798         case 1:
 799                 /*
 800                  * disable the clock gate
 801                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 802                  * disable both of them.
 803                  */
 804                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 805                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 806
 807                 /* set 50M  : (50 = 396 / 2 / 4) */
 808                 reg = readl(&imx_ccm->cs2cdr);
 809                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 810                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 811                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 812                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 813                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 814                 writel(reg, &imx_ccm->cs2cdr);
 815
 816                 /*enable the clock gate*/
 817                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 818                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 819                 break;
 820         default:
 821                 break;
 822         }
 823 }
 824 #endif
 825
 826 #ifdef CONFIG_FEC_MXC
 827 int enable_fec_anatop_clock(enum enet_freq freq)
 828 {
 829         u32 reg = 0;
 830         s32 timeout = 100000;
 831
 832         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 833                 return -EINVAL;
 834
 835         reg = readl(&anatop->pll_enet);
 836         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 837         reg |= freq;
 838
 839         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 840             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 841                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 842                 writel(reg, &anatop->pll_enet);
 843                 while (timeout--) {
 844                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 845                                 break;
 846                 }
 847                 if (timeout < 0)
 848                         return -ETIMEDOUT;
 849         }
 850
 851         /* Enable FEC clock */
 852         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 853         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 854         writel(reg, &anatop->pll_enet);
 855
 856 #ifdef CONFIG_SOC_MX6SX
 857         /*
 858          * Set enet ahb clock to 200MHz
 859          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 860          */
 861         reg = readl(&imx_ccm->chsccdr);
 862         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 863                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 864                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 865         /* PLL2 PFD2 */
 866         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 867         /* Div = 2*/
 868         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 869         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 870         writel(reg, &imx_ccm->chsccdr);
 871
 872         /* Enable enet system clock */
 873         reg = readl(&imx_ccm->CCGR3);
 874         reg |= MXC_CCM_CCGR3_ENET_MASK;
 875         writel(reg, &imx_ccm->CCGR3);
 876 #endif
 877         return 0;
 878 }
 879 #endif
 880
 881 static u32 get_usdhc_clk(u32 port)
 882 {
 883         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 884         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 885         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 886
 887         switch (port) {
 888         case 0:
 889                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 890                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 891                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 892
 893                 break;
 894         case 1:
 895                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 896                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 897                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 898
 899                 break;
 900         case 2:
 901                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 902                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 903                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 904
 905                 break;
 906         case 3:
 907                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 908                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 909                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 910
 911                 break;
 912         default:
 913                 break;
 914         }
 915
 916         if (clk_sel)
 917                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 918         else
 919                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 920
 921         return root_freq / (usdhc_podf + 1);
 922 }
 923
 924 u32 imx_get_uartclk(void)
 925 {
 926         return get_uart_clk();
 927 }
 928
 929 u32 imx_get_fecclk(void)
 930 {
 931         return mxc_get_clock(MXC_IPG_CLK);
 932 }
 933
 934 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 935 static int enable_enet_pll(uint32_t en)
 936 {
 937         u32 reg;
 938         s32 timeout = 100000;
 939
 940         /* Enable PLLs */
 941         reg = readl(&anatop->pll_enet);
 942         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 943         writel(reg, &anatop->pll_enet);
 944         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 945         while (timeout--) {
 946                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 947                         break;
 948         }
 949         if (timeout <= 0)
 950                 return -EIO;
 951         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 952         writel(reg, &anatop->pll_enet);
 953         reg |= en;
 954         writel(reg, &anatop->pll_enet);
 955         return 0;
 956 }
 957 #endif
 958
 959 #ifdef CONFIG_CMD_SATA
 960 static void ungate_sata_clock(void)
 961 {
 962         /* Enable SATA clock. */
 963         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 964 }
 965
 966 int enable_sata_clock(void)
 967 {
 968         ungate_sata_clock();
 969         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 970 }
 971
 972 void disable_sata_clock(void)
 973 {
 974         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 975 }
 976 #endif
 977
 978 #ifdef CONFIG_PCIE_IMX
 979 static void ungate_pcie_clock(void)
 980 {
 981         /* Enable PCIe clock. */
 982         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 983 }
 984
 985 int enable_pcie_clock(void)
 986 {
 987         u32 lvds1_clk_sel;
 988
 989         /*
 990          * Here be dragons!
 991          *
 992          * The register ANATOP_MISC1 is not documented in the Freescale
 993          * MX6RM. The register that is mapped in the ANATOP space and
 994          * marked as ANATOP_MISC1 is actually documented in the PMU section
 995          * of the datasheet as PMU_MISC1.
 996          *
 997          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 998          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 999          * for PCI express link that is clocked from the i.MX6.
1000          */
1001 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
1002 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
1003 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
1004 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1005 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1006
1007         if (is_cpu_type(MXC_CPU_MX6SX))
1008                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
1009         else
1010                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
1011
1012         clrsetbits_le32(&anatop_regs->ana_misc1,
1013                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
1014                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
1015                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
1016
1017         /* PCIe reference clock sourced from AXI. */
1018         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
1019
1020         /* Party time! Ungate the clock to the PCIe. */
1021 #ifdef CONFIG_CMD_SATA
1022         ungate_sata_clock();
1023 #endif
1024         ungate_pcie_clock();
1025
1026         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
1027                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
1028 }
1029 #endif
1030
1031 #ifdef CONFIG_SECURE_BOOT
1032 void hab_caam_clock_enable(unsigned char enable)
1033 {
1034         u32 reg;
1035
1036         /* CG4 ~ CG6, CAAM clocks */
1037         reg = __raw_readl(&imx_ccm->CCGR0);
1038         if (enable)
1039                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1040                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1041                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1042         else
1043                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
1044                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1045                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1046         __raw_writel(reg, &imx_ccm->CCGR0);
1047
1048         /* EMI slow clk */
1049         reg = __raw_readl(&imx_ccm->CCGR6);
1050         if (enable)
1051                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1052         else
1053                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1054         __raw_writel(reg, &imx_ccm->CCGR6);
1055 }
1056 #endif
1057
1058 static void enable_pll3(void)
1059 {
1060         /* make sure pll3 is enabled */
1061         if ((readl(&anatop->usb1_pll_480_ctrl) &
1062                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1063                 /* enable pll's power */
1064                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1065                        &anatop->usb1_pll_480_ctrl_set);
1066                 writel(0x80, &anatop->ana_misc2_clr);
1067                 /* wait for pll lock */
1068                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1069                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1070                         ;
1071                 /* disable bypass */
1072                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1073                        &anatop->usb1_pll_480_ctrl_clr);
1074                 /* enable pll output */
1075                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1076                        &anatop->usb1_pll_480_ctrl_set);
1077         }
1078 }
1079
1080 void enable_thermal_clk(void)
1081 {
1082         enable_pll3();
1083 }
1084
1085 void ipu_clk_enable(void)
1086 {
1087         u32 reg = readl(&imx_ccm->CCGR3);
1088         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1089         writel(reg, &imx_ccm->CCGR3);
1090 }
1091
1092 void ipu_clk_disable(void)
1093 {
1094         u32 reg = readl(&imx_ccm->CCGR3);
1095         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1096         writel(reg, &imx_ccm->CCGR3);
1097 }
1098
1099 void ipu_di_clk_enable(int di)
1100 {
1101         switch (di) {
1102         case 0:
1103                 setbits_le32(&imx_ccm->CCGR3,
1104                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1105                 break;
1106         case 1:
1107                 setbits_le32(&imx_ccm->CCGR3,
1108                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1109                 break;
1110         default:
1111                 printf("%s: Invalid DI index %d\n", __func__, di);
1112         }
1113 }
1114
1115 void ipu_di_clk_disable(int di)
1116 {
1117         switch (di) {
1118         case 0:
1119                 clrbits_le32(&imx_ccm->CCGR3,
1120                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1121                 break;
1122         case 1:
1123                 clrbits_le32(&imx_ccm->CCGR3,
1124                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1125                 break;
1126         default:
1127                 printf("%s: Invalid DI index %d\n", __func__, di);
1128         }
1129 }
1130
1131 void ldb_clk_enable(int ldb)
1132 {
1133         switch (ldb) {
1134         case 0:
1135                 setbits_le32(&imx_ccm->CCGR3,
1136                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1137                 break;
1138         case 1:
1139                 setbits_le32(&imx_ccm->CCGR3,
1140                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1141                 break;
1142         default:
1143                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1144         }
1145 }
1146
1147 void ldb_clk_disable(int ldb)
1148 {
1149         switch (ldb) {
1150         case 0:
1151                 clrbits_le32(&imx_ccm->CCGR3,
1152                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1153                 break;
1154         case 1:
1155                 clrbits_le32(&imx_ccm->CCGR3,
1156                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1157                 break;
1158         default:
1159                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1160         }
1161 }
1162
1163 #ifdef CONFIG_VIDEO_MXS
1164 void lcdif_clk_enable(void)
1165 {
1166         setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1167         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1168 }
1169
1170 void lcdif_clk_disable(void)
1171 {
1172         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1173         clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1174 }
1175
1176 #define CBCMR_LCDIF_MASK        MXC_CCM_CBCMR_LCDIF_PODF_MASK
1177 #define CSCDR2_LCDIF_MASK       (MXC_CCM_CSCDR2_LCDIF_PRED_MASK |       \
1178                                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK)
1179
1180 static u32 get_lcdif_root_clk(u32 cscdr2)
1181 {
1182         int lcdif_pre_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) >>
1183                 MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET;
1184         int lcdif_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK) >>
1185                 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET;
1186         u32 root_freq;
1187
1188         switch (lcdif_clk_sel) {
1189         case 0:
1190                 switch (lcdif_pre_clk_sel) {
1191                 case 0:
1192                         root_freq = decode_pll(PLL_528, MXC_HCLK);
1193                         break;
1194                 case 1:
1195                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
1196                         break;
1197                 case 2:
1198                         root_freq = decode_pll(PLL_VIDEO, MXC_HCLK);
1199                         break;
1200                 case 3:
1201                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
1202                         break;
1203                 case 4:
1204                         root_freq = mxc_get_pll_pfd(PLL_528, 1);
1205                         break;
1206                 case 5:
1207                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
1208                         break;
1209                 default:
1210                         return 0;
1211                 }
1212                 break;
1213         case 1:
1214                 root_freq = mxc_get_pll_pfd(PLL_VIDEO, 0);
1215                 break;
1216         case 2:
1217                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1218                 break;
1219         case 3:
1220                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
1221                 break;
1222         default:
1223                 return 0;
1224         }
1225
1226         return root_freq;
1227 }
1228
1229 static int set_lcdif_pll(u32 ref, u32 freq_khz,
1230                         unsigned post_div)
1231 {
1232         int ret;
1233         u64 freq = freq_khz * 1000;
1234         u32 post_div_mask = 1 << (2 - post_div);
1235         int mul = 1;
1236         u32 min_err = ~0;
1237         u32 reg;
1238         int num = 0;
1239         int denom = 1;
1240         const int min_div = 27;
1241         const int max_div = 54;
1242         const int div_mask = 0x7f;
1243         const u32 max_freq = ref * max_div / post_div;
1244         const u32 min_freq = ref * min_div / post_div;
1245
1246         if (freq > max_freq || freq < min_freq) {
1247                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03uMHz\n",
1248                         freq_khz / 1000, freq_khz % 1000,
1249                         min_freq / 1000000, min_freq / 1000 % 1000,
1250                         max_freq / 1000000, max_freq / 1000 % 1000);
1251                 return -EINVAL;
1252         }
1253         {
1254                 int d = post_div;
1255                 int m = lldiv(freq * d + ref - 1, ref);
1256                 u32 err;
1257                 u32 f;
1258
1259                 debug("%s@%d: d=%d m=%d max_div=%u min_div=%u\n", __func__, __LINE__,
1260                         d, m, max_div, min_div);
1261                 if (m > max_div || m < min_div)
1262                         return -EINVAL;
1263
1264                 f = ref * m / d;
1265                 if (f > freq) {
1266                         debug("%s@%d: d=%d m=%d f=%u freq=%llu\n", __func__, __LINE__,
1267                                 d, m, f, freq);
1268                         return -EINVAL;
1269                 }
1270                 err = freq - f;
1271                 debug("%s@%d: d=%d m=%d f=%u freq=%llu err=%d\n", __func__, __LINE__,
1272                         d, m, f, freq, err);
1273                 if (err < min_err) {
1274                         mul = m;
1275                         min_err = err;
1276                 }
1277         }
1278         if (min_err == ~0) {
1279                 printf("Cannot set VIDEO PLL to %u.%03uMHz\n",
1280                         freq_khz / 1000, freq_khz % 1000);
1281                 return -EINVAL;
1282         }
1283
1284         debug("Setting M=%3u D=%u N=%d DE=%u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1285                 mul, post_div, num, denom,
1286                 freq_khz / post_div / 1000, freq_khz / post_div % 1000,
1287                 ref * mul / post_div / 1000000,
1288                 ref * mul / post_div / 1000 % 1000);
1289
1290         reg = readl(&anatop->pll_video);
1291         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1292
1293         reg = (reg & ~(div_mask |
1294                         BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)) |
1295                 mul | (post_div_mask << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT);
1296         writel(reg, &anatop->pll_video);
1297
1298         ret = wait_pll_lock(&anatop->pll_video);
1299         if (ret) {
1300                 printf("Video PLL failed to lock\n");
1301                 return ret;
1302         }
1303
1304         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1305         return 0;
1306 }
1307
1308 static int set_lcdif_clk(u32 ref, u32 freq_khz)
1309 {
1310         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1311         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1312         u32 cbcmr_val;
1313         u32 cscdr2_val;
1314         u32 freq = freq_khz * 1000;
1315         u32 act_freq;
1316         u32 err;
1317         u32 min_div = 27;
1318         u32 max_div = 54;
1319         u32 min_pll_khz = ref * min_div / 4 / 1000;
1320         u32 max_pll_khz = ref * max_div / 1000;
1321         u32 pll_khz;
1322         u32 post_div = 0;
1323         u32 m;
1324         u32 min_err = ~0;
1325         u32 best_m = 0;
1326         u32 best_pred = 1;
1327         u32 best_podf = 1;
1328         u32 div;
1329         unsigned pd;
1330
1331         if (freq_khz > max_pll_khz)
1332                 return -EINVAL;
1333
1334         for (pd = 1; min_err && pd <= 4; pd <<= 1) {
1335                 for (m = max(min_div, DIV_ROUND_UP(648000 / pd, freq_khz * 64));
1336                      m <= max_div; m++) {
1337                         u32 err;
1338                         int pred = 0;
1339                         int podf = 0;
1340                         u32 root_freq = ref * m / pd;
1341
1342                         div = DIV_ROUND_UP(root_freq, freq);
1343
1344                         while (pred * podf == 0 && div <= 64) {
1345                                 int p1, p2;
1346
1347                                 for (p1 = 1; p1 <= 8; p1++) {
1348                                         for (p2 = 1; p2 <= 8; p2++) {
1349                                                 if (p1 * p2 == div) {
1350                                                         podf = p1;
1351                                                         pred = p2;
1352                                                         break;
1353                                                 }
1354                                         }
1355                                 }
1356                                 if (pred * podf == 0) {
1357                                         div++;
1358                                 }
1359                         }
1360                         if (pred * podf == 0)
1361                                 continue;
1362
1363                         /* relative error in per mille */
1364                         act_freq = root_freq / div;
1365                         err = abs(act_freq - freq) / freq_khz;
1366
1367                         if (err < min_err) {
1368                                 best_m = m;
1369                                 best_pred = pred;
1370                                 best_podf = podf;
1371                                 post_div = pd;
1372                                 min_err = err;
1373                                 if (err <= 10)
1374                                         break;
1375                         }
1376                 }
1377         }
1378         if (min_err > 50)
1379                 return -EINVAL;
1380
1381         pll_khz = ref / 1000 * best_m;
1382         if (pll_khz > max_pll_khz)
1383                 return -EINVAL;
1384
1385         if (pll_khz < min_pll_khz)
1386                 return -EINVAL;
1387
1388         err = set_lcdif_pll(ref, pll_khz / post_div, post_div);
1389         if (err)
1390                 return err;
1391
1392         cbcmr_val = (best_podf - 1) << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET;
1393         cscdr2_val = (best_pred - 1) << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET;
1394
1395         if ((cbcmr & CBCMR_LCDIF_MASK) != cbcmr_val) {
1396                 debug("changing cbcmr from %08x to %08x\n", cbcmr,
1397                         (cbcmr & ~CBCMR_LCDIF_MASK) | cbcmr_val);
1398                 clrsetbits_le32(&imx_ccm->cbcmr,
1399                                 CBCMR_LCDIF_MASK,
1400                                 cbcmr_val);
1401         } else {
1402                 debug("Leaving cbcmr unchanged [%08x]\n", cbcmr);
1403         }
1404         if ((cscdr2 & CSCDR2_LCDIF_MASK) != cscdr2_val) {
1405                 debug("changing cscdr2 from %08x to %08x\n", cscdr2,
1406                         (cscdr2 & ~CSCDR2_LCDIF_MASK) | cscdr2_val);
1407                 clrsetbits_le32(&imx_ccm->cscdr2,
1408                                 CSCDR2_LCDIF_MASK,
1409                                 cscdr2_val);
1410         } else {
1411                 debug("Leaving cscdr2 unchanged [%08x]\n", cscdr2);
1412         }
1413         return 0;
1414 }
1415
1416 void mxs_set_lcdclk(u32 khz)
1417 {
1418         set_lcdif_clk(CONFIG_SYS_MX6_HCLK, khz);
1419 }
1420
1421 static u32 get_lcdif_clk(void)
1422 {
1423         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1424         u32 podf = ((cbcmr & MXC_CCM_CBCMR_LCDIF_PODF_MASK) >>
1425                 MXC_CCM_CBCMR_LCDIF_PODF_OFFSET) + 1;
1426         u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1427         u32 pred = ((cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRED_MASK) >>
1428                 MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET) + 1;
1429         u32 root_freq = get_lcdif_root_clk(cscdr2);
1430
1431         return root_freq / pred / podf;
1432 }
1433 #endif
1434
1435 unsigned int mxc_get_clock(enum mxc_clock clk)
1436 {
1437         switch (clk) {
1438         case MXC_ARM_CLK:
1439                 return get_mcu_main_clk();
1440         case MXC_PER_CLK:
1441                 return get_periph_clk();
1442         case MXC_AHB_CLK:
1443                 return get_ahb_clk();
1444         case MXC_IPG_CLK:
1445                 return get_ipg_clk();
1446         case MXC_IPG_PERCLK:
1447         case MXC_I2C_CLK:
1448                 return get_ipg_per_clk();
1449         case MXC_UART_CLK:
1450                 return get_uart_clk();
1451         case MXC_CSPI_CLK:
1452                 return get_cspi_clk();
1453         case MXC_AXI_CLK:
1454                 return get_axi_clk();
1455         case MXC_EMI_SLOW_CLK:
1456                 return get_emi_slow_clk();
1457         case MXC_DDR_CLK:
1458                 return get_mmdc_ch0_clk();
1459         case MXC_ESDHC_CLK:
1460                 return get_usdhc_clk(0);
1461         case MXC_ESDHC2_CLK:
1462                 return get_usdhc_clk(1);
1463         case MXC_ESDHC3_CLK:
1464                 return get_usdhc_clk(2);
1465         case MXC_ESDHC4_CLK:
1466                 return get_usdhc_clk(3);
1467         case MXC_SATA_CLK:
1468                 return get_ahb_clk();
1469         case MXC_NFC_CLK:
1470                 return get_nfc_clk();
1471 #ifdef CONFIG_VIDEO_MXS
1472         case MXC_LCDIF_CLK:
1473                 return get_lcdif_clk();
1474 #endif
1475         default:
1476                 printf("Unsupported MXC CLK: %d\n", clk);
1477         }
1478
1479         return 0;
1480 }
1481
1482 /* Config CPU clock */
1483 static int set_arm_clk(u32 ref, u32 freq_khz)
1484 {
1485         int ret;
1486         int d;
1487         int div = 0;
1488         int mul = 0;
1489         u32 min_err = ~0;
1490         u32 reg;
1491         const int min_div = 54;
1492         const int max_div = 108;
1493         const int div_mask = 0x7f;
1494         const u32 max_freq = ref * max_div / 2;
1495         const u32 min_freq = ref * min_div / 8 / 2;
1496
1497         if (freq_khz > max_freq / 1000 || freq_khz < min_freq / 1000) {
1498                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1499                         freq_khz / 1000, freq_khz % 1000,
1500                         min_freq / 1000000, min_freq / 1000 % 1000,
1501                         max_freq / 1000000, max_freq / 1000 % 1000);
1502                 return -EINVAL;
1503         }
1504
1505         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1506                 int m = freq_khz * 2 * d / (ref / 1000);
1507                 u32 f;
1508                 u32 err;
1509
1510                 if (m > max_div) {
1511                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1512                                 d, m);
1513                         break;
1514                 }
1515
1516                 f = ref * m / d / 2;
1517                 if (f > freq_khz * 1000) {
1518                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1519                                 d, m, f, freq_khz);
1520                         if (--m < min_div)
1521                                 return -EINVAL;
1522                         f = ref * m / d / 2;
1523                 }
1524                 err = freq_khz * 1000 - f;
1525                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1526                         d, m, f, freq_khz, err);
1527                 if (err < min_err) {
1528                         mul = m;
1529                         div = d;
1530                         min_err = err;
1531                         if (err == 0)
1532                                 break;
1533                 }
1534         }
1535         if (min_err == ~0)
1536                 return -EINVAL;
1537         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1538                 mul, div, freq_khz / 1000, freq_khz % 1000,
1539                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1540
1541         reg = readl(&anatop->pll_arm);
1542         setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1543
1544         reg = (reg & ~div_mask) | mul;
1545         writel(reg, &anatop->pll_arm);
1546
1547         writel(div - 1, &imx_ccm->cacrr);
1548
1549         ret = wait_pll_lock(&anatop->pll_video);
1550         if (ret) {
1551                 printf("ARM PLL failed to lock\n");
1552                 return ret;
1553         }
1554
1555         clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1556
1557         return 0;
1558 }
1559
1560 /*
1561  * This function assumes the expected core clock has to be changed by
1562  * modifying the PLL. This is NOT true always but for most of the times,
1563  * it is. So it assumes the PLL output freq is the same as the expected
1564  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1565  * In the latter case, it will try to increase the presc value until
1566  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1567  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1568  * on the targeted PLL and reference input clock to the PLL. Lastly,
1569  * it sets the register based on these values along with the dividers.
1570  * Note 1) There is no value checking for the passed-in divider values
1571  *         so the caller has to make sure those values are sensible.
1572  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1573  *         exceed NFC_CLK_MAX.
1574  */
1575 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1576 {
1577         int ret;
1578
1579         freq *= 1000;
1580
1581         switch (clk) {
1582         case MXC_ARM_CLK:
1583                 ret = set_arm_clk(ref, freq);
1584                 break;
1585
1586         case MXC_NFC_CLK:
1587                 ret = set_nfc_clk(ref, freq);
1588                 break;
1589
1590         default:
1591                 printf("Warning: Unsupported or invalid clock type: %d\n",
1592                         clk);
1593                 return -EINVAL;
1594         }
1595
1596         return ret;
1597 }
1598
1599 /*
1600  * Dump some core clocks.
1601  */
1602 #define print_pll(pll)  {                               \
1603         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1604         printf("%-12s %4d.%03d MHz\n", #pll,            \
1605                 __pll / 1000000, __pll / 1000 % 1000);  \
1606         }
1607
1608 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1609
1610 #define print_clk(clk)  {                               \
1611         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1612         printf("%-12s %4d.%03d MHz\n", #clk,            \
1613                 __clk / 1000000, __clk / 1000 % 1000);  \
1614         }
1615
1616 #define print_pfd(pll, pfd)     {                                       \
1617         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1618         if (__pfd & (0x80 << 8 * pfd)) {                                \
1619                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1620         } else {                                                        \
1621                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1622                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1623                         pll * 18 / __pfd,                               \
1624                         pll * 18 * 1000 / __pfd % 1000);                \
1625         }                                                               \
1626 }
1627
1628 static void do_mx6_showclocks(void)
1629 {
1630         print_pll(PLL_ARM);
1631         print_pll(PLL_528);
1632         print_pll(PLL_USBOTG);
1633         print_pll(PLL_AUDIO);
1634         print_pll(PLL_VIDEO);
1635         print_pll(PLL_ENET);
1636         print_pll(PLL_USB2);
1637         printf("\n");
1638
1639         print_pfd(480, 0);
1640         print_pfd(480, 1);
1641         print_pfd(480, 2);
1642         print_pfd(480, 3);
1643         print_pfd(528, 0);
1644         print_pfd(528, 1);
1645         print_pfd(528, 2);
1646         printf("\n");
1647
1648         print_clk(IPG);
1649         print_clk(UART);
1650         print_clk(CSPI);
1651         print_clk(AHB);
1652         print_clk(AXI);
1653         print_clk(DDR);
1654         print_clk(ESDHC);
1655         print_clk(ESDHC2);
1656         print_clk(ESDHC3);
1657         print_clk(ESDHC4);
1658         print_clk(EMI_SLOW);
1659         print_clk(NFC);
1660         print_clk(IPG_PER);
1661         print_clk(ARM);
1662 #ifdef CONFIG_VIDEO_MXS
1663         print_clk(LCDIF);
1664 #endif
1665 }
1666
1667 static struct clk_lookup {
1668         const char *name;
1669         unsigned int index;
1670 } mx6_clk_lookup[] = {
1671         { "arm", MXC_ARM_CLK, },
1672         { "nfc", MXC_NFC_CLK, },
1673 };
1674
1675 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1676 {
1677         int i;
1678         unsigned long freq;
1679         unsigned long ref = ~0UL;
1680
1681         if (argc < 2) {
1682                 do_mx6_showclocks();
1683                 return CMD_RET_SUCCESS;
1684         } else if (argc == 2 || argc > 4) {
1685                 return CMD_RET_USAGE;
1686         }
1687
1688         freq = simple_strtoul(argv[2], NULL, 0);
1689         if (freq == 0) {
1690                 printf("Invalid clock frequency %lu\n", freq);
1691                 return CMD_RET_FAILURE;
1692         }
1693         if (argc > 3) {
1694                 ref = simple_strtoul(argv[3], NULL, 0);
1695         }
1696         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1697                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1698                         switch (mx6_clk_lookup[i].index) {
1699                         case MXC_ARM_CLK:
1700                                 if (argc > 3)
1701                                         return CMD_RET_USAGE;
1702                                 ref = MXC_HCLK;
1703                                 break;
1704
1705                         case MXC_NFC_CLK:
1706                                 if (argc > 3 && ref > 3) {
1707                                         printf("Invalid clock selector value: %lu\n", ref);
1708                                         return CMD_RET_FAILURE;
1709                                 }
1710                                 break;
1711                         }
1712                         printf("Setting %s clock to %lu MHz\n",
1713                                 mx6_clk_lookup[i].name, freq);
1714                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1715                                 break;
1716                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1717                         printf("%s clock set to %lu.%03lu MHz\n",
1718                                 mx6_clk_lookup[i].name,
1719                                 freq / 1000000, freq / 1000 % 1000);
1720                         return CMD_RET_SUCCESS;
1721                 }
1722         }
1723         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1724                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1725                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1726                         printf("\t%s\n", mx6_clk_lookup[i].name);
1727                 }
1728         } else {
1729                 printf("Failed to set clock %s to %s MHz\n",
1730                         argv[1], argv[2]);
1731         }
1732         return CMD_RET_FAILURE;
1733 }
1734
1735 #ifndef CONFIG_SOC_MX6SX
1736 void enable_ipu_clock(void)
1737 {
1738         int reg = readl(&imx_ccm->CCGR3);
1739         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1740         writel(reg, &imx_ccm->CCGR3);
1741
1742         if (is_mx6dqp()) {
1743                 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1744                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1745         }
1746 }
1747 #endif
1748 /***************************************************/
1749
1750 U_BOOT_CMD(
1751         clocks, 4, 0, do_clocks,
1752         "display/set clocks",
1753         "                    - display clock settings\n"
1754         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1755 );