arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/errno.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/sys_proto.h>
  14
  15 enum pll_clocks {
  16         PLL_SYS,        /* System PLL */
  17         PLL_BUS,        /* System Bus PLL*/
  18         PLL_USBOTG,     /* OTG USB PLL */
  19         PLL_ENET,       /* ENET PLL */
  20 };
  21
  22 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  23
  24 #ifdef CONFIG_MXC_OCOTP
  25 void enable_ocotp_clk(unsigned char enable)
  26 {
  27         u32 reg;
  28
  29         reg = __raw_readl(&imx_ccm->CCGR2);
  30         if (enable)
  31                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  32         else
  33                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
  34         __raw_writel(reg, &imx_ccm->CCGR2);
  35 }
  36 #endif
  37
  38 void enable_usboh3_clk(unsigned char enable)
  39 {
  40         u32 reg;
  41
  42         reg = __raw_readl(&imx_ccm->CCGR6);
  43         if (enable)
  44                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
  45         else
  46                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
  47         __raw_writel(reg, &imx_ccm->CCGR6);
  48
  49 }
  50
  51 #ifdef CONFIG_SYS_I2C_MXC
  52 /* i2c_num can be from 0 - 2 */
  53 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  54 {
  55         u32 reg;
  56         u32 mask;
  57
  58         if (i2c_num > 2)
  59                 return -EINVAL;
  60
  61         mask = MXC_CCM_CCGR_CG_MASK
  62                 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
  63         reg = __raw_readl(&imx_ccm->CCGR2);
  64         if (enable)
  65                 reg |= mask;
  66         else
  67                 reg &= ~mask;
  68         __raw_writel(reg, &imx_ccm->CCGR2);
  69         return 0;
  70 }
  71 #endif
  72
  73 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
  74 {
  75         u32 div;
  76
  77         switch (pll) {
  78         case PLL_SYS:
  79                 div = __raw_readl(&imx_ccm->analog_pll_sys);
  80                 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
  81
  82                 return infreq * (div >> 1);
  83         case PLL_BUS:
  84                 div = __raw_readl(&imx_ccm->analog_pll_528);
  85                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
  86
  87                 return infreq * (20 + (div << 1));
  88         case PLL_USBOTG:
  89                 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
  90                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
  91
  92                 return infreq * (20 + (div << 1));
  93         case PLL_ENET:
  94                 div = __raw_readl(&imx_ccm->analog_pll_enet);
  95                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
  96
  97                 return 25000000 * (div + (div >> 1) + 1);
  98         default:
  99                 return 0;
 100         }
 101         /* NOTREACHED */
 102 }
 103 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 104 {
 105         u32 div;
 106         u64 freq;
 107
 108         switch (pll) {
 109         case PLL_BUS:
 110                 if (pfd_num == 3) {
 111                         /* No PFD3 on PPL2 */
 112                         return 0;
 113                 }
 114                 div = __raw_readl(&imx_ccm->analog_pfd_528);
 115                 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
 116                 break;
 117         case PLL_USBOTG:
 118                 div = __raw_readl(&imx_ccm->analog_pfd_480);
 119                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 120                 break;
 121         default:
 122                 /* No PFD on other PLL                                       */
 123                 return 0;
 124         }
 125
 126         return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 127                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 128 }
 129
 130 static u32 get_mcu_main_clk(void)
 131 {
 132         u32 reg, freq;
 133
 134         reg = __raw_readl(&imx_ccm->cacrr);
 135         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 136         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 137         freq = decode_pll(PLL_SYS, MXC_HCLK);
 138
 139         return freq / (reg + 1);
 140 }
 141
 142 u32 get_periph_clk(void)
 143 {
 144         u32 reg, freq = 0;
 145
 146         reg = __raw_readl(&imx_ccm->cbcdr);
 147         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 148                 reg = __raw_readl(&imx_ccm->cbcmr);
 149                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 150                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 151
 152                 switch (reg) {
 153                 case 0:
 154                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 155                         break;
 156                 case 1:
 157                 case 2:
 158                         freq = MXC_HCLK;
 159                         break;
 160                 default:
 161                         break;
 162                 }
 163         } else {
 164                 reg = __raw_readl(&imx_ccm->cbcmr);
 165                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 166                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 167
 168                 switch (reg) {
 169                 case 0:
 170                         freq = decode_pll(PLL_BUS, MXC_HCLK);
 171                         break;
 172                 case 1:
 173                         freq = mxc_get_pll_pfd(PLL_BUS, 2);
 174                         break;
 175                 case 2:
 176                         freq = mxc_get_pll_pfd(PLL_BUS, 0);
 177                         break;
 178                 case 3:
 179                         /* static / 2 divider */
 180                         freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 181                         break;
 182                 default:
 183                         break;
 184                 }
 185         }
 186
 187         return freq;
 188 }
 189
 190 static u32 get_ipg_clk(void)
 191 {
 192         u32 reg, ipg_podf;
 193
 194         reg = __raw_readl(&imx_ccm->cbcdr);
 195         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 196         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 197
 198         return get_ahb_clk() / (ipg_podf + 1);
 199 }
 200
 201 static u32 get_ipg_per_clk(void)
 202 {
 203         u32 reg, perclk_podf;
 204
 205         reg = __raw_readl(&imx_ccm->cscmr1);
 206         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 207
 208         return get_ipg_clk() / (perclk_podf + 1);
 209 }
 210
 211 static u32 get_uart_clk(void)
 212 {
 213         u32 reg, uart_podf;
 214         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 215         reg = __raw_readl(&imx_ccm->cscdr1);
 216 #ifdef CONFIG_MX6SL
 217         if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 218                 freq = MXC_HCLK;
 219 #endif
 220         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 221         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 222
 223         return freq / (uart_podf + 1);
 224 }
 225
 226 static u32 get_cspi_clk(void)
 227 {
 228         u32 reg, cspi_podf;
 229
 230         reg = __raw_readl(&imx_ccm->cscdr2);
 231         reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
 232         cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 233
 234         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 235 }
 236
 237 static u32 get_axi_clk(void)
 238 {
 239         u32 root_freq, axi_podf;
 240         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 241
 242         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 243         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 244
 245         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 246                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 247                         root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 248                 else
 249                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 250         } else
 251                 root_freq = get_periph_clk();
 252
 253         return  root_freq / (axi_podf + 1);
 254 }
 255
 256 static u32 get_emi_slow_clk(void)
 257 {
 258         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 259
 260         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 261         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 262         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 263         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 264         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 265
 266         switch (emi_clk_sel) {
 267         case 0:
 268                 root_freq = get_axi_clk();
 269                 break;
 270         case 1:
 271                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 272                 break;
 273         case 2:
 274                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
 275                 break;
 276         case 3:
 277                 root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
 278                 break;
 279         }
 280
 281         return root_freq / (emi_slow_podf + 1);
 282 }
 283
 284 #ifdef CONFIG_MX6SL
 285 static u32 get_mmdc_ch0_clk(void)
 286 {
 287         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 288         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 289         u32 freq, podf;
 290
 291         podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
 292                         >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 293
 294         switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 295                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 296         case 0:
 297                 freq = decode_pll(PLL_BUS, MXC_HCLK);
 298                 break;
 299         case 1:
 300                 freq = mxc_get_pll_pfd(PLL_BUS, 2);
 301                 break;
 302         case 2:
 303                 freq = mxc_get_pll_pfd(PLL_BUS, 0);
 304                 break;
 305         case 3:
 306                 /* static / 2 divider */
 307                 freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
 308         }
 309
 310         return freq / (podf + 1);
 311
 312 }
 313 #else
 314 static u32 get_mmdc_ch0_clk(void)
 315 {
 316         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 317         u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 318                                 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 319
 320         return get_periph_clk() / (mmdc_ch0_podf + 1);
 321 }
 322 #endif
 323
 324 #ifdef CONFIG_FEC_MXC
 325 int enable_fec_anatop_clock(void)
 326 {
 327         u32 reg = 0;
 328         s32 timeout = 100000;
 329
 330         struct anatop_regs __iomem *anatop =
 331                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 332
 333         reg = readl(&anatop->pll_enet);
 334         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 335             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 336                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 337                 writel(reg, &anatop->pll_enet);
 338                 while (timeout--) {
 339                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 340                                 break;
 341                 }
 342                 if (timeout < 0)
 343                         return -ETIMEDOUT;
 344         }
 345
 346         /* Enable FEC clock */
 347         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 348         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 349         writel(reg, &anatop->pll_enet);
 350
 351         return 0;
 352 }
 353 #endif
 354
 355 static u32 get_usdhc_clk(u32 port)
 356 {
 357         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 358         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 359         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 360
 361         switch (port) {
 362         case 0:
 363                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 364                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 365                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 366
 367                 break;
 368         case 1:
 369                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 370                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 371                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 372
 373                 break;
 374         case 2:
 375                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 376                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 377                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 378
 379                 break;
 380         case 3:
 381                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 382                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 383                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 384
 385                 break;
 386         default:
 387                 break;
 388         }
 389
 390         if (clk_sel)
 391                 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
 392         else
 393                 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
 394
 395         return root_freq / (usdhc_podf + 1);
 396 }
 397
 398 u32 imx_get_uartclk(void)
 399 {
 400         return get_uart_clk();
 401 }
 402
 403 u32 imx_get_fecclk(void)
 404 {
 405         return decode_pll(PLL_ENET, MXC_HCLK);
 406 }
 407
 408 int enable_sata_clock(void)
 409 {
 410         u32 reg = 0;
 411         s32 timeout = 100000;
 412         struct mxc_ccm_reg *const imx_ccm
 413                 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
 414
 415         /* Enable sata clock */
 416         reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
 417         reg |= MXC_CCM_CCGR5_SATA_MASK;
 418         writel(reg, &imx_ccm->CCGR5);
 419
 420         /* Enable PLLs */
 421         reg = readl(&imx_ccm->analog_pll_enet);
 422         reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
 423         writel(reg, &imx_ccm->analog_pll_enet);
 424         reg |= BM_ANADIG_PLL_SYS_ENABLE;
 425         while (timeout--) {
 426                 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
 427                         break;
 428         }
 429         if (timeout <= 0)
 430                 return -EIO;
 431         reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
 432         writel(reg, &imx_ccm->analog_pll_enet);
 433         reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
 434         writel(reg, &imx_ccm->analog_pll_enet);
 435
 436         return 0 ;
 437 }
 438
 439 unsigned int mxc_get_clock(enum mxc_clock clk)
 440 {
 441         switch (clk) {
 442         case MXC_ARM_CLK:
 443                 return get_mcu_main_clk();
 444         case MXC_PER_CLK:
 445                 return get_periph_clk();
 446         case MXC_AHB_CLK:
 447                 return get_ahb_clk();
 448         case MXC_IPG_CLK:
 449                 return get_ipg_clk();
 450         case MXC_IPG_PERCLK:
 451         case MXC_I2C_CLK:
 452                 return get_ipg_per_clk();
 453         case MXC_UART_CLK:
 454                 return get_uart_clk();
 455         case MXC_CSPI_CLK:
 456                 return get_cspi_clk();
 457         case MXC_AXI_CLK:
 458                 return get_axi_clk();
 459         case MXC_EMI_SLOW_CLK:
 460                 return get_emi_slow_clk();
 461         case MXC_DDR_CLK:
 462                 return get_mmdc_ch0_clk();
 463         case MXC_ESDHC_CLK:
 464                 return get_usdhc_clk(0);
 465         case MXC_ESDHC2_CLK:
 466                 return get_usdhc_clk(1);
 467         case MXC_ESDHC3_CLK:
 468                 return get_usdhc_clk(2);
 469         case MXC_ESDHC4_CLK:
 470                 return get_usdhc_clk(3);
 471         case MXC_SATA_CLK:
 472                 return get_ahb_clk();
 473         default:
 474                 break;
 475         }
 476
 477         return -1;
 478 }
 479
 480 /*
 481  * Dump some core clockes.
 482  */
 483 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 484 {
 485         u32 freq;
 486         freq = decode_pll(PLL_SYS, MXC_HCLK);
 487         printf("PLL_SYS    %8d MHz\n", freq / 1000000);
 488         freq = decode_pll(PLL_BUS, MXC_HCLK);
 489         printf("PLL_BUS    %8d MHz\n", freq / 1000000);
 490         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 491         printf("PLL_OTG    %8d MHz\n", freq / 1000000);
 492         freq = decode_pll(PLL_ENET, MXC_HCLK);
 493         printf("PLL_NET    %8d MHz\n", freq / 1000000);
 494
 495         printf("\n");
 496         printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 497         printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
 498 #ifdef CONFIG_MXC_SPI
 499         printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
 500 #endif
 501         printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
 502         printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
 503         printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
 504         printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
 505         printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
 506         printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
 507         printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
 508         printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
 509         printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
 510
 511         return 0;
 512 }
 513
 514 void enable_ipu_clock(void)
 515 {
 516         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 517         int reg;
 518         reg = readl(&mxc_ccm->CCGR3);
 519         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 520         writel(reg, &mxc_ccm->CCGR3);
 521 }
 522 /***************************************************/
 523
 524 U_BOOT_CMD(
 525         clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
 526         "display clocks",
 527         ""
 528 );