arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_ARM,        /* PLL1: ARM PLL */
  18         PLL_528,        /* PLL2: System Bus PLL*/
  19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
  20         PLL_AUDIO,      /* PLL4: Audio PLL */
  21         PLL_VIDEO,      /* PLL5: Video PLL */
  22         PLL_ENET,       /* PLL6: ENET PLL */
  23         PLL_USB2,       /* PLL7: USB2 PLL */
  24         PLL_MLB,        /* PLL8: MLB PLL */
  25 };
  26
  27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
  28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
  29
  30 int clk_enable(struct clk *clk)
  31 {
  32         int ret = 0;
  33
  34         if (!clk)
  35                 return 0;
  36         if (clk->usecount == 0) {
  37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
  38                 ret = clk->enable(clk);
  39                 if (ret)
  40                         return ret;
  41                 clk->usecount++;
  42         }
  43         assert(clk->usecount > 0);
  44         return ret;
  45 }
  46
  47 void clk_disable(struct clk *clk)
  48 {
  49         if (!clk)
  50                 return;
  51
  52         assert(clk->usecount > 0);
  53         if (!(--clk->usecount)) {
  54                 if (clk->disable) {
  55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
  56                         clk->disable(clk);
  57                 }
  58         }
  59 }
  60
  61 int clk_get_usecount(struct clk *clk)
  62 {
  63         if (clk == NULL)
  64                 return 0;
  65
  66         return clk->usecount;
  67 }
  68
  69 u32 clk_get_rate(struct clk *clk)
  70 {
  71         if (!clk)
  72                 return 0;
  73
  74         return clk->rate;
  75 }
  76
  77 struct clk *clk_get_parent(struct clk *clk)
  78 {
  79         if (!clk)
  80                 return 0;
  81
  82         return clk->parent;
  83 }
  84
  85 int clk_set_rate(struct clk *clk, unsigned long rate)
  86 {
  87         if (clk && clk->set_rate)
  88                 clk->set_rate(clk, rate);
  89         return clk->rate;
  90 }
  91
  92 long clk_round_rate(struct clk *clk, unsigned long rate)
  93 {
  94         if (clk == NULL || !clk->round_rate)
  95                 return 0;
  96
  97         return clk->round_rate(clk, rate);
  98 }
  99
 100 int clk_set_parent(struct clk *clk, struct clk *parent)
 101 {
 102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
 103                 clk ? clk->parent : NULL);
 104
 105         if (!clk || clk == parent)
 106                 return 0;
 107
 108         if (clk->set_parent) {
 109                 int ret;
 110
 111                 ret = clk->set_parent(clk, parent);
 112                 if (ret)
 113                         return ret;
 114         }
 115         clk->parent = parent;
 116         return 0;
 117 }
 118
 119 #ifdef CONFIG_MXC_OCOTP
 120 void enable_ocotp_clk(unsigned char enable)
 121 {
 122         u32 reg;
 123
 124         reg = __raw_readl(&imx_ccm->CCGR2);
 125         if (enable)
 126                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 127         else
 128                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 129         __raw_writel(reg, &imx_ccm->CCGR2);
 130 }
 131 #endif
 132
 133 #ifdef CONFIG_NAND_MXS
 134 void setup_gpmi_io_clk(u32 cfg)
 135 {
 136         /* Disable clocks per ERR007177 from MX6 errata */
 137         clrbits_le32(&imx_ccm->CCGR4,
 138                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 139                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 140                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 141                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 142                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 143
 144         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 145
 146         clrsetbits_le32(&imx_ccm->cs2cdr,
 147                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 148                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 149                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 150                         cfg);
 151
 152         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 153         setbits_le32(&imx_ccm->CCGR4,
 154                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 155                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 156                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 158                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 159 }
 160 #endif
 161
 162 void enable_usboh3_clk(unsigned char enable)
 163 {
 164         u32 reg;
 165
 166         reg = __raw_readl(&imx_ccm->CCGR6);
 167         if (enable)
 168                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
 169         else
 170                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
 171         __raw_writel(reg, &imx_ccm->CCGR6);
 172
 173 }
 174
 175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 176 void enable_enet_clk(unsigned char enable)
 177 {
 178         u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
 179
 180         if (enable)
 181                 setbits_le32(&imx_ccm->CCGR1, mask);
 182         else
 183                 clrbits_le32(&imx_ccm->CCGR1, mask);
 184 }
 185 #endif
 186
 187 #ifdef CONFIG_MXC_UART
 188 void enable_uart_clk(unsigned char enable)
 189 {
 190         u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 191
 192         if (enable)
 193                 setbits_le32(&imx_ccm->CCGR5, mask);
 194         else
 195                 clrbits_le32(&imx_ccm->CCGR5, mask);
 196 }
 197 #endif
 198
 199 #ifdef CONFIG_SPI
 200 /* spi_num can be from 0 - 4 */
 201 int enable_cspi_clock(unsigned char enable, unsigned spi_num)
 202 {
 203         u32 mask;
 204
 205         if (spi_num > 4)
 206                 return -EINVAL;
 207
 208         mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
 209         if (enable)
 210                 setbits_le32(&imx_ccm->CCGR1, mask);
 211         else
 212                 clrbits_le32(&imx_ccm->CCGR1, mask);
 213
 214         return 0;
 215 }
 216 #endif
 217
 218 #ifdef CONFIG_MMC
 219 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 220 {
 221         u32 mask;
 222
 223         if (bus_num > 3)
 224                 return -EINVAL;
 225
 226         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 227         if (enable)
 228                 setbits_le32(&imx_ccm->CCGR6, mask);
 229         else
 230                 clrbits_le32(&imx_ccm->CCGR6, mask);
 231
 232         return 0;
 233 }
 234 #endif
 235
 236 #ifdef CONFIG_SYS_I2C_MXC
 237 /* i2c_num can be from 0 - 3 */
 238 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 239 {
 240         u32 reg;
 241         u32 mask;
 242
 243         if (i2c_num > 3)
 244                 return -EINVAL;
 245         if (i2c_num < 3) {
 246                 mask = MXC_CCM_CCGR_CG_MASK
 247                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 248                         + (i2c_num << 1));
 249                 reg = __raw_readl(&imx_ccm->CCGR2);
 250                 if (enable)
 251                         reg |= mask;
 252                 else
 253                         reg &= ~mask;
 254                 __raw_writel(reg, &imx_ccm->CCGR2);
 255         } else {
 256                 mask = MXC_CCM_CCGR_CG_MASK
 257                         << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
 258                 reg = __raw_readl(&imx_ccm->CCGR1);
 259                 if (enable)
 260                         reg |= mask;
 261                 else
 262                         reg &= ~mask;
 263                 __raw_writel(reg, &imx_ccm->CCGR1);
 264         }
 265         return 0;
 266 }
 267 #endif
 268
 269 /* spi_num can be from 0 - SPI_MAX_NUM */
 270 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 271 {
 272         u32 reg;
 273         u32 mask;
 274
 275         if (spi_num > SPI_MAX_NUM)
 276                 return -EINVAL;
 277
 278         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 279         reg = __raw_readl(&imx_ccm->CCGR1);
 280         if (enable)
 281                 reg |= mask;
 282         else
 283                 reg &= ~mask;
 284         __raw_writel(reg, &imx_ccm->CCGR1);
 285         return 0;
 286 }
 287 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 288 {
 289         u32 div;
 290
 291         switch (pll) {
 292         case PLL_ARM:
 293                 div = __raw_readl(&anatop->pll_arm);
 294                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
 295                         /* Assume the bypass clock is always derived from OSC */
 296                         return infreq;
 297                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
 298
 299                 return infreq * div / 2;
 300         case PLL_528:
 301                 div = __raw_readl(&anatop->pll_528);
 302                 if (div & BM_ANADIG_PLL_528_BYPASS)
 303                         return infreq;
 304                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 305
 306                 return infreq * (20 + div * 2);
 307         case PLL_USBOTG:
 308                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
 309                 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
 310                         return infreq;
 311                 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
 312
 313                 return infreq * (20 + div * 2);
 314         case PLL_AUDIO:
 315                 div = __raw_readl(&anatop->pll_audio);
 316                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 317                         return infreq;
 318                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 319
 320                 return infreq * div;
 321         case PLL_VIDEO:
 322                 div = __raw_readl(&anatop->pll_video);
 323                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 324                         return infreq;
 325                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 326
 327                 return infreq * div;
 328         case PLL_ENET:
 329                 div = __raw_readl(&anatop->pll_enet);
 330                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
 331                         return infreq;
 332                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 333
 334                 return 25000000 * (div + (div >> 1) + 1);
 335         case PLL_USB2:
 336                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
 337                 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
 338                         return infreq;
 339                 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
 340
 341                 return infreq * (20 + div * 2);
 342         case PLL_MLB:
 343                 div = __raw_readl(&anatop->pll_mlb);
 344                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
 345                         return infreq;
 346                 /* unknown external clock provided on MLB_CLK pin */
 347                 return 0;
 348         }
 349         return 0;
 350 }
 351 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 352 {
 353         u32 div;
 354         u64 freq;
 355         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 356
 357         switch (pll) {
 358         case PLL_528:
 359                 if (pfd_num == 3) {
 360                         /* No PFD3 on PLL2 */
 361                         return 0;
 362                 }
 363                 div = __raw_readl(&anatop->pfd_528);
 364                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
 365                 break;
 366         case PLL_USBOTG:
 367                 div = __raw_readl(&anatop->pfd_480);
 368                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 369                 break;
 370         default:
 371                 /* No PFD on other PLL */
 372                 return 0;
 373         }
 374
 375         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 376                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 377 }
 378
 379 static u32 get_mcu_main_clk(void)
 380 {
 381         u32 reg, freq;
 382
 383         reg = __raw_readl(&imx_ccm->cacrr);
 384         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 385         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 386         freq = decode_pll(PLL_ARM, MXC_HCLK);
 387
 388         return freq / (reg + 1);
 389 }
 390
 391 u32 get_periph_clk(void)
 392 {
 393         u32 reg, freq = 0;
 394
 395         reg = __raw_readl(&imx_ccm->cbcdr);
 396         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 397                 reg = __raw_readl(&imx_ccm->cbcmr);
 398                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 399                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 400
 401                 switch (reg) {
 402                 case 0:
 403                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 404                         break;
 405                 case 1:
 406                 case 2:
 407                         freq = MXC_HCLK;
 408                         break;
 409                 }
 410         } else {
 411                 reg = __raw_readl(&imx_ccm->cbcmr);
 412                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 413                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 414
 415                 switch (reg) {
 416                 case 0:
 417                         freq = decode_pll(PLL_528, MXC_HCLK);
 418                         break;
 419                 case 1:
 420                         freq = mxc_get_pll_pfd(PLL_528, 2);
 421                         break;
 422                 case 2:
 423                         freq = mxc_get_pll_pfd(PLL_528, 0);
 424                         break;
 425                 case 3:
 426                         /* static / 2 divider */
 427                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
 428                         break;
 429                 }
 430         }
 431
 432         return freq;
 433 }
 434
 435 static u32 get_ipg_clk(void)
 436 {
 437         u32 reg, ipg_podf;
 438
 439         reg = __raw_readl(&imx_ccm->cbcdr);
 440         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 441         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 442
 443         return get_ahb_clk() / (ipg_podf + 1);
 444 }
 445
 446 static u32 get_ipg_per_clk(void)
 447 {
 448         u32 reg, perclk_podf;
 449
 450         reg = __raw_readl(&imx_ccm->cscmr1);
 451 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 452         if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 453                 return MXC_HCLK; /* OSC 24Mhz */
 454 #endif
 455         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 456
 457         return get_ipg_clk() / (perclk_podf + 1);
 458 }
 459
 460 static u32 get_uart_clk(void)
 461 {
 462         u32 reg, uart_podf;
 463         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 464         reg = __raw_readl(&imx_ccm->cscdr1);
 465 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 466         if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 467                 freq = MXC_HCLK;
 468 #endif
 469         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 470         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 471
 472         return freq / (uart_podf + 1);
 473 }
 474
 475 static u32 get_cspi_clk(void)
 476 {
 477         u32 reg, cspi_podf;
 478
 479         reg = __raw_readl(&imx_ccm->cscdr2);
 480         reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
 481         cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 482
 483         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 484 }
 485
 486 static u32 get_axi_clk(void)
 487 {
 488         u32 root_freq, axi_podf;
 489         u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);
 490
 491         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 492         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 493
 494         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 495                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 496                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 497                 else
 498                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 499         } else
 500                 root_freq = get_periph_clk();
 501
 502         return  root_freq / (axi_podf + 1);
 503 }
 504
 505 static u32 get_emi_slow_clk(void)
 506 {
 507         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 508
 509         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 510         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 511         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 512         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 513         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 514
 515         switch (emi_clk_sel) {
 516         case 0:
 517                 root_freq = get_axi_clk();
 518                 break;
 519         case 1:
 520                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 521                 break;
 522         case 2:
 523                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
 524                 break;
 525         case 3:
 526                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
 527                 break;
 528         }
 529
 530         return root_freq / (emi_slow_podf + 1);
 531 }
 532
 533 static u32 get_nfc_clk(void)
 534 {
 535         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 536         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 537         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 538         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
 539                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 540         u32 root_freq;
 541
 542         switch (nfc_clk_sel) {
 543         case 0:
 544                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 545                 break;
 546         case 1:
 547                 root_freq = decode_pll(PLL_528, MXC_HCLK);
 548                 break;
 549         case 2:
 550                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 551                 break;
 552         case 3:
 553                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 554                 break;
 555         }
 556
 557         return root_freq / (pred + 1) / (podf + 1);
 558 }
 559
 560 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
 561                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
 562                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
 563
 564 static int set_nfc_clk(u32 ref, u32 freq_khz)
 565 {
 566         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 567         u32 podf;
 568         u32 pred;
 569         int nfc_clk_sel;
 570         u32 root_freq;
 571         u32 min_err = ~0;
 572         u32 nfc_val = ~0;
 573         u32 freq = freq_khz * 1000;
 574
 575         for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
 576                 u32 act_freq;
 577                 u32 err;
 578
 579                 if (ref < 4 && ref != nfc_clk_sel)
 580                         continue;
 581
 582                 switch (nfc_clk_sel) {
 583                 case 0:
 584                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
 585                         break;
 586                 case 1:
 587                         root_freq = decode_pll(PLL_528, MXC_HCLK);
 588                         break;
 589                 case 2:
 590                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 591                         break;
 592                 case 3:
 593                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 594                         break;
 595                 }
 596                 if (root_freq < freq)
 597                         continue;
 598
 599                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
 600                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
 601                 act_freq = root_freq / pred / podf;
 602                 err = (freq - act_freq) * 100 / freq;
 603                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
 604                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
 605                 if (act_freq > freq)
 606                         continue;
 607                 if (err < min_err) {
 608                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 609                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 610                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 611                         min_err = err;
 612                         if (err == 0)
 613                                 break;
 614                 }
 615         }
 616
 617         if (nfc_val == ~0 || min_err > 10)
 618                 return -EINVAL;
 619
 620         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
 621                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
 622                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
 623                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
 624                         &imx_ccm->cs2cdr);
 625         } else {
 626                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
 627         }
 628         return 0;
 629 }
 630
 631 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
 632 static u32 get_mmdc_ch0_clk(void)
 633 {
 634         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 635         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 636         u32 freq, podf;
 637
 638         podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
 639                         >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 640
 641         switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 642                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 643         case 0:
 644                 freq = decode_pll(PLL_528, MXC_HCLK);
 645                 break;
 646         case 1:
 647                 freq = mxc_get_pll_pfd(PLL_528, 2);
 648                 break;
 649         case 2:
 650                 freq = mxc_get_pll_pfd(PLL_528, 0);
 651                 break;
 652         case 3:
 653                 /* static / 2 divider */
 654                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
 655         }
 656
 657         return freq / (podf + 1);
 658
 659 }
 660 #else
 661 static u32 get_mmdc_ch0_clk(void)
 662 {
 663         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 664         u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 665                                 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 666
 667         return get_periph_clk() / (mmdc_ch0_podf + 1);
 668 }
 669 #endif
 670
 671 #ifdef CONFIG_SOC_MX6SX
 672 /* qspi_num can be from 0 - 1 */
 673 void enable_qspi_clk(int qspi_num)
 674 {
 675         u32 reg = 0;
 676         /* Enable QuadSPI clock */
 677         switch (qspi_num) {
 678         case 0:
 679                 /* disable the clock gate */
 680                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 681
 682                 /* set 50M  : (50 = 396 / 2 / 4) */
 683                 reg = readl(&imx_ccm->cscmr1);
 684                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 685                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 686                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 687                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 688                 writel(reg, &imx_ccm->cscmr1);
 689
 690                 /* enable the clock gate */
 691                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 692                 break;
 693         case 1:
 694                 /*
 695                  * disable the clock gate
 696                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 697                  * disable both of them.
 698                  */
 699                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 700                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 701
 702                 /* set 50M  : (50 = 396 / 2 / 4) */
 703                 reg = readl(&imx_ccm->cs2cdr);
 704                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 705                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 706                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 707                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 708                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 709                 writel(reg, &imx_ccm->cs2cdr);
 710
 711                 /*enable the clock gate*/
 712                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 713                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 714                 break;
 715         default:
 716                 break;
 717         }
 718 }
 719 #endif
 720
 721 #ifdef CONFIG_FEC_MXC
 722 int enable_fec_anatop_clock(enum enet_freq freq)
 723 {
 724         u32 reg = 0;
 725         s32 timeout = 100000;
 726
 727         struct anatop_regs __iomem *anatop =
 728                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 729
 730         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 731                 return -EINVAL;
 732
 733         reg = readl(&anatop->pll_enet);
 734         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 735         reg |= freq;
 736
 737         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 738             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 739                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 740                 writel(reg, &anatop->pll_enet);
 741                 while (timeout--) {
 742                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 743                                 break;
 744                 }
 745                 if (timeout < 0)
 746                         return -ETIMEDOUT;
 747         }
 748
 749         /* Enable FEC clock */
 750         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 751         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 752         writel(reg, &anatop->pll_enet);
 753
 754 #ifdef CONFIG_SOC_MX6SX
 755         /*
 756          * Set enet ahb clock to 200MHz
 757          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 758          */
 759         reg = readl(&imx_ccm->chsccdr);
 760         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 761                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 762                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 763         /* PLL2 PFD2 */
 764         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 765         /* Div = 2*/
 766         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 767         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 768         writel(reg, &imx_ccm->chsccdr);
 769
 770         /* Enable enet system clock */
 771         reg = readl(&imx_ccm->CCGR3);
 772         reg |= MXC_CCM_CCGR3_ENET_MASK;
 773         writel(reg, &imx_ccm->CCGR3);
 774 #endif
 775         return 0;
 776 }
 777 #endif
 778
 779 static u32 get_usdhc_clk(u32 port)
 780 {
 781         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 782         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 783         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 784
 785         switch (port) {
 786         case 0:
 787                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 788                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 789                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 790
 791                 break;
 792         case 1:
 793                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 794                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 795                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 796
 797                 break;
 798         case 2:
 799                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 800                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 801                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 802
 803                 break;
 804         case 3:
 805                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 806                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 807                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 808
 809                 break;
 810         default:
 811                 break;
 812         }
 813
 814         if (clk_sel)
 815                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 816         else
 817                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 818
 819         return root_freq / (usdhc_podf + 1);
 820 }
 821
 822 u32 imx_get_uartclk(void)
 823 {
 824         return get_uart_clk();
 825 }
 826
 827 u32 imx_get_fecclk(void)
 828 {
 829         return mxc_get_clock(MXC_IPG_CLK);
 830 }
 831
 832 static int enable_enet_pll(uint32_t en)
 833 {
 834         u32 reg;
 835         s32 timeout = 100000;
 836
 837         /* Enable PLLs */
 838         reg = readl(&anatop->pll_enet);
 839         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 840         writel(reg, &anatop->pll_enet);
 841         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 842         while (timeout--) {
 843                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 844                         break;
 845         }
 846         if (timeout <= 0)
 847                 return -EIO;
 848         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 849         writel(reg, &anatop->pll_enet);
 850         reg |= en;
 851         writel(reg, &anatop->pll_enet);
 852         return 0;
 853 }
 854
 855 #ifndef CONFIG_SOC_MX6SX
 856 static void ungate_sata_clock(void)
 857 {
 858         struct mxc_ccm_reg *const imx_ccm =
 859                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 860
 861         /* Enable SATA clock. */
 862         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 863 }
 864 #endif
 865
 866 static void ungate_pcie_clock(void)
 867 {
 868         struct mxc_ccm_reg *const imx_ccm =
 869                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 870
 871         /* Enable PCIe clock. */
 872         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 873 }
 874
 875 #ifndef CONFIG_SOC_MX6SX
 876 int enable_sata_clock(void)
 877 {
 878         ungate_sata_clock();
 879         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 880 }
 881
 882 void disable_sata_clock(void)
 883 {
 884         struct mxc_ccm_reg *const imx_ccm =
 885                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 886
 887         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 888 }
 889 #endif
 890
 891 int enable_pcie_clock(void)
 892 {
 893         struct anatop_regs *anatop_regs =
 894                 (struct anatop_regs *)ANATOP_BASE_ADDR;
 895         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 896         u32 lvds1_clk_sel;
 897
 898         /*
 899          * Here be dragons!
 900          *
 901          * The register ANATOP_MISC1 is not documented in the Freescale
 902          * MX6RM. The register that is mapped in the ANATOP space and
 903          * marked as ANATOP_MISC1 is actually documented in the PMU section
 904          * of the datasheet as PMU_MISC1.
 905          *
 906          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 907          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 908          * for PCI express link that is clocked from the i.MX6.
 909          */
 910 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
 911 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
 912 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
 913 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
 914 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
 915
 916         if (is_cpu_type(MXC_CPU_MX6SX))
 917                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 918         else
 919                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
 920
 921         clrsetbits_le32(&anatop_regs->ana_misc1,
 922                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 923                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 924                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 925
 926         /* PCIe reference clock sourced from AXI. */
 927         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 928
 929         /* Party time! Ungate the clock to the PCIe. */
 930 #ifndef CONFIG_SOC_MX6SX
 931         ungate_sata_clock();
 932 #endif
 933         ungate_pcie_clock();
 934
 935         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
 936                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 937 }
 938
 939 #ifdef CONFIG_SECURE_BOOT
 940 void hab_caam_clock_enable(unsigned char enable)
 941 {
 942         u32 reg;
 943
 944         /* CG4 ~ CG6, CAAM clocks */
 945         reg = __raw_readl(&imx_ccm->CCGR0);
 946         if (enable)
 947                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 948                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 949                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 950         else
 951                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 952                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 953                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 954         __raw_writel(reg, &imx_ccm->CCGR0);
 955
 956         /* EMI slow clk */
 957         reg = __raw_readl(&imx_ccm->CCGR6);
 958         if (enable)
 959                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
 960         else
 961                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
 962         __raw_writel(reg, &imx_ccm->CCGR6);
 963 }
 964 #endif
 965
 966 static void enable_pll3(void)
 967 {
 968         struct anatop_regs __iomem *anatop =
 969                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 970
 971         /* make sure pll3 is enabled */
 972         if ((readl(&anatop->usb1_pll_480_ctrl) &
 973                         BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
 974                 /* enable pll's power */
 975                 writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
 976                        &anatop->usb1_pll_480_ctrl_set);
 977                 writel(0x80, &anatop->ana_misc2_clr);
 978                 /* wait for pll lock */
 979                 while ((readl(&anatop->usb1_pll_480_ctrl) &
 980                         BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
 981                         ;
 982                 /* disable bypass */
 983                 writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
 984                        &anatop->usb1_pll_480_ctrl_clr);
 985                 /* enable pll output */
 986                 writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
 987                        &anatop->usb1_pll_480_ctrl_set);
 988         }
 989 }
 990
 991 void enable_thermal_clk(void)
 992 {
 993         enable_pll3();
 994 }
 995
 996 void ipu_clk_enable(void)
 997 {
 998         u32 reg = readl(&imx_ccm->CCGR3);
 999         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1000         writel(reg, &imx_ccm->CCGR3);
1001 }
1002
1003 void ipu_clk_disable(void)
1004 {
1005         u32 reg = readl(&imx_ccm->CCGR3);
1006         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1007         writel(reg, &imx_ccm->CCGR3);
1008 }
1009
1010 void ipu_di_clk_enable(int di)
1011 {
1012         switch (di) {
1013         case 0:
1014                 setbits_le32(&imx_ccm->CCGR3,
1015                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1016                 break;
1017         case 1:
1018                 setbits_le32(&imx_ccm->CCGR3,
1019                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1020                 break;
1021         default:
1022                 printf("%s: Invalid DI index %d\n", __func__, di);
1023         }
1024 }
1025
1026 void ipu_di_clk_disable(int di)
1027 {
1028         switch (di) {
1029         case 0:
1030                 clrbits_le32(&imx_ccm->CCGR3,
1031                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1032                 break;
1033         case 1:
1034                 clrbits_le32(&imx_ccm->CCGR3,
1035                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1036                 break;
1037         default:
1038                 printf("%s: Invalid DI index %d\n", __func__, di);
1039         }
1040 }
1041
1042 void ldb_clk_enable(int ldb)
1043 {
1044         switch (ldb) {
1045         case 0:
1046                 setbits_le32(&imx_ccm->CCGR3,
1047                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1048                 break;
1049         case 1:
1050                 setbits_le32(&imx_ccm->CCGR3,
1051                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1052                 break;
1053         default:
1054                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1055         }
1056 }
1057
1058 void ldb_clk_disable(int ldb)
1059 {
1060         switch (ldb) {
1061         case 0:
1062                 clrbits_le32(&imx_ccm->CCGR3,
1063                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1064                 break;
1065         case 1:
1066                 clrbits_le32(&imx_ccm->CCGR3,
1067                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1068                 break;
1069         default:
1070                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1071         }
1072 }
1073
1074 void ocotp_clk_enable(void)
1075 {
1076         u32 reg = readl(&imx_ccm->CCGR2);
1077         reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1078         writel(reg, &imx_ccm->CCGR2);
1079 }
1080
1081 void ocotp_clk_disable(void)
1082 {
1083         u32 reg = readl(&imx_ccm->CCGR2);
1084         reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1085         writel(reg, &imx_ccm->CCGR2);
1086 }
1087
1088 unsigned int mxc_get_clock(enum mxc_clock clk)
1089 {
1090         switch (clk) {
1091         case MXC_ARM_CLK:
1092                 return get_mcu_main_clk();
1093         case MXC_PER_CLK:
1094                 return get_periph_clk();
1095         case MXC_AHB_CLK:
1096                 return get_ahb_clk();
1097         case MXC_IPG_CLK:
1098                 return get_ipg_clk();
1099         case MXC_IPG_PERCLK:
1100         case MXC_I2C_CLK:
1101                 return get_ipg_per_clk();
1102         case MXC_UART_CLK:
1103                 return get_uart_clk();
1104         case MXC_CSPI_CLK:
1105                 return get_cspi_clk();
1106         case MXC_AXI_CLK:
1107                 return get_axi_clk();
1108         case MXC_EMI_SLOW_CLK:
1109                 return get_emi_slow_clk();
1110         case MXC_DDR_CLK:
1111                 return get_mmdc_ch0_clk();
1112         case MXC_ESDHC_CLK:
1113                 return get_usdhc_clk(0);
1114         case MXC_ESDHC2_CLK:
1115                 return get_usdhc_clk(1);
1116         case MXC_ESDHC3_CLK:
1117                 return get_usdhc_clk(2);
1118         case MXC_ESDHC4_CLK:
1119                 return get_usdhc_clk(3);
1120         case MXC_SATA_CLK:
1121                 return get_ahb_clk();
1122         case MXC_NFC_CLK:
1123                 return get_nfc_clk();
1124         default:
1125                 printf("Unsupported MXC CLK: %d\n", clk);
1126         }
1127
1128         return 0;
1129 }
1130
1131 static inline int gcd(int m, int n)
1132 {
1133         int t;
1134         while (m > 0) {
1135                 if (n > m) {
1136                         t = m;
1137                         m = n;
1138                         n = t;
1139                 } /* swap */
1140                 m -= n;
1141         }
1142         return n;
1143 }
1144
1145 /* Config CPU clock */
1146 static int set_arm_clk(u32 ref, u32 freq_khz)
1147 {
1148         int d;
1149         int div = 0;
1150         int mul = 0;
1151         u32 min_err = ~0;
1152         u32 reg;
1153
1154         if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1155                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1156                         freq_khz / 1000, freq_khz % 1000,
1157                         54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1158                         108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1159                 return -EINVAL;
1160         }
1161
1162         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1163                 int m = freq_khz * 2 * d / (ref / 1000);
1164                 u32 f;
1165                 u32 err;
1166
1167                 if (m > 108) {
1168                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1169                                 d, m);
1170                         break;
1171                 }
1172
1173                 f = ref * m / d / 2;
1174                 if (f > freq_khz * 1000) {
1175                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1176                                 d, m, f, freq_khz);
1177                         if (--m < 54)
1178                                 return -EINVAL;
1179                         f = ref * m / d / 2;
1180                 }
1181                 err = freq_khz * 1000 - f;
1182                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1183                         d, m, f, freq_khz, err);
1184                 if (err < min_err) {
1185                         mul = m;
1186                         div = d;
1187                         min_err = err;
1188                         if (err == 0)
1189                                 break;
1190                 }
1191         }
1192         if (min_err == ~0)
1193                 return -EINVAL;
1194         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1195                 mul, div, freq_khz / 1000, freq_khz % 1000,
1196                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1197
1198         reg = readl(&anatop->pll_arm);
1199         debug("anadig_pll_arm=%08x -> %08x\n",
1200                 reg, (reg & ~0x7f) | mul);
1201
1202         reg |= 1 << 16;
1203         writel(reg, &anatop->pll_arm); /* bypass PLL */
1204
1205         reg = (reg & ~0x7f) | mul;
1206         writel(reg, &anatop->pll_arm);
1207
1208         writel(div - 1, &imx_ccm->cacrr);
1209
1210         reg &= ~(1 << 16);
1211         writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1212
1213         return 0;
1214 }
1215
1216 /*
1217  * This function assumes the expected core clock has to be changed by
1218  * modifying the PLL. This is NOT true always but for most of the times,
1219  * it is. So it assumes the PLL output freq is the same as the expected
1220  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1221  * In the latter case, it will try to increase the presc value until
1222  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1223  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1224  * on the targeted PLL and reference input clock to the PLL. Lastly,
1225  * it sets the register based on these values along with the dividers.
1226  * Note 1) There is no value checking for the passed-in divider values
1227  *         so the caller has to make sure those values are sensible.
1228  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1229  *         exceed NFC_CLK_MAX.
1230  *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
1231  *         177MHz for higher voltage, this function fixes the max to 133MHz.
1232  *      4) This function should not have allowed diag_printf() calls since
1233  *         the serial driver has been stoped. But leave then here to allow
1234  *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1235  */
1236 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1237 {
1238         int ret;
1239
1240         freq *= 1000;
1241
1242         switch (clk) {
1243         case MXC_ARM_CLK:
1244                 ret = set_arm_clk(ref, freq);
1245                 break;
1246
1247         case MXC_NFC_CLK:
1248                 ret = set_nfc_clk(ref, freq);
1249                 break;
1250
1251         default:
1252                 printf("Warning: Unsupported or invalid clock type: %d\n",
1253                         clk);
1254                 return -EINVAL;
1255         }
1256
1257         return ret;
1258 }
1259
1260 /*
1261  * Dump some core clocks.
1262  */
1263 #define print_pll(pll)  {                               \
1264         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1265         printf("%-12s %4d.%03d MHz\n", #pll,            \
1266                 __pll / 1000000, __pll / 1000 % 1000);  \
1267         }
1268
1269 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1270
1271 #define print_clk(clk)  {                               \
1272         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1273         printf("%-12s %4d.%03d MHz\n", #clk,            \
1274                 __clk / 1000000, __clk / 1000 % 1000);  \
1275         }
1276
1277 #define print_pfd(pll, pfd)     {                                       \
1278         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1279         if (__pfd & (0x80 << 8 * pfd)) {                                \
1280                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1281         } else {                                                        \
1282                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1283                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1284                         pll * 18 / __pfd,                               \
1285                         pll * 18 * 1000 / __pfd % 1000);                \
1286         }                                                               \
1287 }
1288
1289 static void do_mx6_showclocks(void)
1290 {
1291         print_pll(PLL_ARM);
1292         print_pll(PLL_528);
1293         print_pll(PLL_USBOTG);
1294         print_pll(PLL_AUDIO);
1295         print_pll(PLL_VIDEO);
1296         print_pll(PLL_ENET);
1297         print_pll(PLL_USB2);
1298         printf("\n");
1299
1300         print_pfd(480, 0);
1301         print_pfd(480, 1);
1302         print_pfd(480, 2);
1303         print_pfd(480, 3);
1304         print_pfd(528, 0);
1305         print_pfd(528, 1);
1306         print_pfd(528, 2);
1307         printf("\n");
1308
1309         print_clk(IPG);
1310         print_clk(UART);
1311         print_clk(CSPI);
1312         print_clk(AHB);
1313         print_clk(AXI);
1314         print_clk(DDR);
1315         print_clk(ESDHC);
1316         print_clk(ESDHC2);
1317         print_clk(ESDHC3);
1318         print_clk(ESDHC4);
1319         print_clk(EMI_SLOW);
1320         print_clk(NFC);
1321         print_clk(IPG_PER);
1322         print_clk(ARM);
1323 }
1324
1325 static struct clk_lookup {
1326         const char *name;
1327         unsigned int index;
1328 } mx6_clk_lookup[] = {
1329         { "arm", MXC_ARM_CLK, },
1330         { "nfc", MXC_NFC_CLK, },
1331 };
1332
1333 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1334 {
1335         int i;
1336         unsigned long freq;
1337         unsigned long ref = ~0UL;
1338
1339         if (argc < 2) {
1340                 do_mx6_showclocks();
1341                 return CMD_RET_SUCCESS;
1342         } else if (argc == 2 || argc > 4) {
1343                 return CMD_RET_USAGE;
1344         }
1345
1346         freq = simple_strtoul(argv[2], NULL, 0);
1347         if (freq == 0) {
1348                 printf("Invalid clock frequency %lu\n", freq);
1349                 return CMD_RET_FAILURE;
1350         }
1351         if (argc > 3) {
1352                 ref = simple_strtoul(argv[3], NULL, 0);
1353         }
1354         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1355                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1356                         switch (mx6_clk_lookup[i].index) {
1357                         case MXC_ARM_CLK:
1358                                 if (argc > 3)
1359                                         return CMD_RET_USAGE;
1360                                 ref = MXC_HCLK;
1361                                 break;
1362
1363                         case MXC_NFC_CLK:
1364                                 if (argc > 3 && ref > 3) {
1365                                         printf("Invalid clock selector value: %lu\n", ref);
1366                                         return CMD_RET_FAILURE;
1367                                 }
1368                                 break;
1369                         }
1370                         printf("Setting %s clock to %lu MHz\n",
1371                                 mx6_clk_lookup[i].name, freq);
1372                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1373                                 break;
1374                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1375                         printf("%s clock set to %lu.%03lu MHz\n",
1376                                 mx6_clk_lookup[i].name,
1377                                 freq / 1000000, freq / 1000 % 1000);
1378                         return CMD_RET_SUCCESS;
1379                 }
1380         }
1381         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1382                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1383                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1384                         printf("\t%s\n", mx6_clk_lookup[i].name);
1385                 }
1386         } else {
1387                 printf("Failed to set clock %s to %s MHz\n",
1388                         argv[1], argv[2]);
1389         }
1390         return CMD_RET_FAILURE;
1391 }
1392
1393 #ifndef CONFIG_SOC_MX6SX
1394 void enable_ipu_clock(void)
1395 {
1396         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1397         int reg;
1398         reg = readl(&mxc_ccm->CCGR3);
1399         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1400         writel(reg, &mxc_ccm->CCGR3);
1401 }
1402 #endif
1403 /***************************************************/
1404
1405 U_BOOT_CMD(
1406         clocks, 4, 0, do_clocks,
1407         "display/set clocks",
1408         "                    - display clock settings\n"
1409         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1410 );