3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/armv7.h>
15 #include <asm/bootm.h>
16 #include <asm/pl310.h>
17 #include <asm/errno.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/regs-ocotp.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/imx-common/boot_mode.h>
24 #include <asm/imx-common/dma.h>
26 #include <asm/arch/mxc_hdmi.h>
27 #include <asm/arch/crm_regs.h>
29 #include <imx_thermal.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define __data __attribute__((section(".data")))
35 #ifdef CONFIG_MX6_TEMPERATURE_MIN
36 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
38 #define TEMPERATURE_MIN (-40)
40 #ifdef CONFIG_MX6_TEMPERATURE_HOT
41 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
43 #define TEMPERATURE_HOT 80
45 #ifdef CONFIG_MX6_TEMPERATURE_MAX
46 #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
48 #define TEMPERATURE_MAX 125
50 #define TEMP_AVG_COUNT 5
51 #define TEMP_WARN_THRESHOLD 5
67 #if defined(CONFIG_IMX6_THERMAL)
68 static const struct imx_thermal_plat imx6_thermal_plat = {
69 .regs = (void *)ANATOP_BASE_ADDR,
74 U_BOOT_DEVICE(imx6_thermal) = {
75 .name = "imx_thermal",
76 .platdata = &imx6_thermal_plat,
82 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
83 return readl(&scu->config) & 3;
88 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
89 u32 reg = readl(&anatop->digprog_sololite);
90 u32 type = ((reg >> 16) & 0xff);
93 if (type != MXC_CPU_MX6SL) {
94 reg = readl(&anatop->digprog);
95 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
96 cfg = readl(&scu->config) & 3;
97 type = ((reg >> 16) & 0xff);
98 if (type == MXC_CPU_MX6DL) {
100 type = MXC_CPU_MX6SOLO;
103 if (type == MXC_CPU_MX6Q) {
109 major = ((reg >> 8) & 0xff);
111 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
113 type = MXC_CPU_MX6QP;
115 type = MXC_CPU_MX6DP;
117 reg &= 0xff; /* mx6 silicon revision */
118 return (type << 12) | (reg + (0x10 * (major + 1)));
122 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
123 * defines a 2-bit SPEED_GRADING
125 #define OCOTP_CFG3_SPEED_SHIFT 16
126 #define OCOTP_CFG3_SPEED_800MHZ 0
127 #define OCOTP_CFG3_SPEED_850MHZ 1
128 #define OCOTP_CFG3_SPEED_1GHZ 2
129 #define OCOTP_CFG3_SPEED_1P2GHZ 3
131 u32 get_cpu_speed_grade_hz(void)
135 if (fuse_read(0, 3, &val)) {
136 printf("Failed to read speed_grade fuse\n");
139 val >>= OCOTP_CFG3_SPEED_SHIFT;
143 /* Valid for IMX6DQ */
144 case OCOTP_CFG3_SPEED_1P2GHZ:
145 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
147 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
148 case OCOTP_CFG3_SPEED_1GHZ:
150 /* Valid for IMX6DQ */
151 case OCOTP_CFG3_SPEED_850MHZ:
152 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
154 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
155 case OCOTP_CFG3_SPEED_800MHZ:
162 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
163 * defines a 2-bit Temperature Grade
165 * return temperature grade and min/max temperature in celcius
167 #define OCOTP_MEM0_TEMP_SHIFT 6
169 u32 get_cpu_temp_grade(int *minc, int *maxc)
173 if (fuse_read(1, 0, &val)) {
174 printf("Failed to read temp_grade fuse\n");
177 val >>= OCOTP_MEM0_TEMP_SHIFT;
181 if (val == TEMP_AUTOMOTIVE) {
184 } else if (val == TEMP_INDUSTRIAL) {
187 } else if (val == TEMP_EXTCOMMERCIAL) {
198 #ifdef CONFIG_REVISION_TAG
199 u32 __weak get_board_rev(void)
201 u32 cpurev = get_cpu_rev();
202 u32 type = ((cpurev >> 12) & 0xff);
203 if (type == MXC_CPU_MX6SOLO)
204 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
206 if (type == MXC_CPU_MX6D)
207 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
215 struct aipstz_regs *aips1, *aips2;
216 #ifdef CONFIG_SOC_MX6SX
217 struct aipstz_regs *aips3;
220 aips1 = (struct aipstz_regs *)AIPS1_ARB_BASE_ADDR;
221 aips2 = (struct aipstz_regs *)AIPS2_ARB_BASE_ADDR;
222 #ifdef CONFIG_SOC_MX6SX
223 aips3 = (struct aipstz_regs *)AIPS3_ARB_BASE_ADDR;
227 * Set all MPROTx to be non-bufferable, trusted for R/W,
228 * not forced to user-mode.
230 writel(0x77777777, &aips1->mprot0);
231 writel(0x77777777, &aips1->mprot1);
232 writel(0x77777777, &aips2->mprot0);
233 writel(0x77777777, &aips2->mprot1);
236 * Set all OPACRx to be non-bufferable, not require
237 * supervisor privilege level for access,allow for
238 * write access and untrusted master access.
240 writel(0x00000000, &aips1->opacr0);
241 writel(0x00000000, &aips1->opacr1);
242 writel(0x00000000, &aips1->opacr2);
243 writel(0x00000000, &aips1->opacr3);
244 writel(0x00000000, &aips1->opacr4);
245 writel(0x00000000, &aips2->opacr0);
246 writel(0x00000000, &aips2->opacr1);
247 writel(0x00000000, &aips2->opacr2);
248 writel(0x00000000, &aips2->opacr3);
249 writel(0x00000000, &aips2->opacr4);
251 #ifdef CONFIG_SOC_MX6SX
253 * Set all MPROTx to be non-bufferable, trusted for R/W,
254 * not forced to user-mode.
256 writel(0x77777777, &aips3->mprot0);
257 writel(0x77777777, &aips3->mprot1);
260 * Set all OPACRx to be non-bufferable, not require
261 * supervisor privilege level for access,allow for
262 * write access and untrusted master access.
264 writel(0x00000000, &aips3->opacr0);
265 writel(0x00000000, &aips3->opacr1);
266 writel(0x00000000, &aips3->opacr2);
267 writel(0x00000000, &aips3->opacr3);
268 writel(0x00000000, &aips3->opacr4);
272 static void clear_ldo_ramp(void)
274 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
277 /* ROM may modify LDO ramp up time according to fuse setting, so in
278 * order to be in the safe side we neeed to reset these settings to
279 * match the reset value: 0'b00
281 reg = readl(&anatop->ana_misc2);
282 reg &= ~(0x3f << 24);
283 writel(reg, &anatop->ana_misc2);
287 * Set the PMU_REG_CORE register
289 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
290 * Possible values are from 0.725V to 1.450V in steps of
293 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
295 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
296 u32 val, step, old, reg = readl(&anatop->reg_core);
300 val = 0x00; /* Power gated off */
302 val = 0x1F; /* Power FET switched full on. No regulation */
304 val = (mv - 700) / 25;
322 old = (reg & (0x1F << shift)) >> shift;
323 step = abs(val - old);
327 reg = (reg & ~(0x1F << shift)) | (val << shift);
328 writel(reg, &anatop->reg_core);
331 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
339 static u32 __data thermal_calib;
341 #define FACTOR0 10000000
342 #define FACTOR1 15976
343 #define FACTOR2 4297157
345 int raw_to_celsius(unsigned int raw, unsigned int raw_25c, unsigned int raw_hot,
346 unsigned int hot_temp)
350 if (raw_hot != 0 && hot_temp != 0) {
351 unsigned int raw_n40c, ratio;
353 ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
354 raw_n40c = raw_25c + (13 * ratio) / 20;
356 temperature = (raw_n40c - raw) * 100 / ratio - 40;
358 temperature = TEMPERATURE_MIN;
360 u64 temp64 = FACTOR0;
363 * Derived from linear interpolation:
364 * slope = 0.4297157 - (0.0015976 * 25C fuse)
365 * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
366 * (Nmeas - n1) / (Tmeas - t1) = slope
367 * We want to reduce this down to the minimum computation necessary
368 * for each temperature read. Also, we want Tmeas in millicelsius
369 * and we don't want to lose precision from integer division. So...
370 * Tmeas = (Nmeas - n1) / slope + t1
371 * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
372 * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
373 * Let constant c1 = (-1000 / slope)
374 * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
375 * Let constant c2 = n1 *c1 + 1000 * t1
376 * milli_Tmeas = c2 - Nmeas * c1
379 do_div(temp64, FACTOR1 * raw_25c - FACTOR2);
381 c2 = raw_25c * c1 + 1000 * 25;
382 temperature = (c2 - raw * c1) / 1000;
387 int read_cpu_temperature(void)
389 unsigned int reg, tmp, i;
390 unsigned int raw_25c, raw_hot, hot_temp;
392 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
393 struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
395 if (!thermal_calib) {
396 if (fuse_read(1, 6, &thermal_calib) != 0) {
397 printf("Failed to read thermal calibration data\n");
402 if (thermal_calib == 0 || thermal_calib == 0xffffffff)
403 return TEMPERATURE_MIN;
406 * [31:20] sensor value @ 25C
407 * [19:8] sensor value of hot
408 * [7:0] hot temperature value */
409 raw_25c = thermal_calib >> 20;
410 raw_hot = (thermal_calib & 0xfff00) >> 8;
411 hot_temp = thermal_calib & 0xff;
413 /* now we only using single measure, every time we measure
414 * the temperature, we will power on/off the anadig module
416 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
417 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
419 /* write measure freq */
420 writel(327, &anatop->tempsense1);
421 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
422 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
423 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
425 /* average the temperature value over multiple readings */
426 for (i = 0; i < TEMP_AVG_COUNT; i++) {
430 while ((readl(&anatop->tempsense0) &
431 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
436 if ((readl(&anatop->tempsense0) &
437 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
439 printf("Failed to read temp sensor\n");
445 reg = (readl(&anatop->tempsense0) &
446 BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
447 BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
451 tmp = (tmp * i + reg) / (i + 1);
452 writel(BM_ANADIG_TEMPSENSE0_FINISHED,
453 &anatop->tempsense0_clr);
456 temperature = raw_to_celsius(tmp, raw_25c, raw_hot, hot_temp);
458 /* power down anatop thermal sensor */
459 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
460 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
465 int check_cpu_temperature(int boot)
467 static int __data max_temp;
468 int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
469 int tmp = read_cpu_temperature();
472 if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
473 printf("Temperature: can't get valid data!\n");
478 if (tmp > boot_limit) {
479 printf("CPU is %d C, too hot, resetting...\n", tmp);
483 if (tmp > max_temp) {
484 if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
485 printf("WARNING: CPU temperature %d C\n", tmp);
489 printf("Temperature: %d C, calibration data 0x%x\n",
491 while (tmp >= boot_limit) {
493 printf("CPU is %d C, too hot to boot, waiting...\n",
500 tmp = read_cpu_temperature();
501 if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
502 printf("WARNING: CPU temperature %d C\n", tmp);
509 static void imx_set_wdog_powerdown(bool enable)
511 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
512 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
513 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
515 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
516 writew(enable, &wdog3->wmcr);
518 /* Write to the PDE (Power Down Enable) bit */
519 writew(enable, &wdog1->wmcr);
520 writew(enable, &wdog2->wmcr);
523 static void set_ahb_rate(u32 val)
525 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
528 div = get_periph_clk() / val - 1;
529 reg = readl(&mxc_ccm->cbcdr);
531 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
532 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
535 static void clear_mmdc_ch_mask(void)
537 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
539 reg = readl(&mxc_ccm->ccdr);
541 /* Clear MMDC channel mask */
542 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
543 writel(reg, &mxc_ccm->ccdr);
546 static void init_bandgap(void)
548 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
550 * Ensure the bandgap has stabilized.
552 while (!(readl(&anatop->ana_misc0) & 0x80))
555 * For best noise performance of the analog blocks using the
556 * outputs of the bandgap, the reftop_selfbiasoff bit should
559 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
562 #ifdef CONFIG_SOC_MX6SL
563 static void set_preclk_from_osc(void)
565 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
568 reg = readl(&mxc_ccm->cscmr1);
569 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
570 writel(reg, &mxc_ccm->cscmr1);
574 #define SRC_SCR_WARM_RESET_ENABLE 0
576 static void init_src(void)
578 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
582 * force warm reset sources to generate cold reset
583 * for a more reliable restart
585 val = readl(&src_regs->scr);
586 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
587 writel(val, &src_regs->scr);
590 int arch_cpu_init(void)
594 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
595 clear_mmdc_ch_mask();
598 * Disable self-bias circuit in the analog bandap.
599 * The self-bias circuit is used by the bandgap during startup.
600 * This bit should be set after the bandgap has initialized.
605 * When low freq boot is enabled, ROM will not set AHB
606 * freq, so we need to ensure AHB freq is 132MHz in such
609 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
610 set_ahb_rate(132000000);
612 /* Set perclk to source from OSC 24MHz */
613 #if defined(CONFIG_SOC_MX6SL)
614 set_preclk_from_osc();
617 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
619 #ifdef CONFIG_VIDEO_IPUV3
620 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
622 #ifdef CONFIG_APBH_DMA
623 /* Timer is required for Initializing APBH DMA */
633 int board_postclk_init(void)
635 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
640 #ifndef CONFIG_SYS_DCACHE_OFF
641 void enable_caches(void)
643 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
644 enum dcache_option option = DCACHE_WRITETHROUGH;
646 enum dcache_option option = DCACHE_WRITEBACK;
649 /* Avoid random hang when download by usb */
650 invalidate_dcache_all();
652 /* Enable D-cache. I-cache is already enabled in start.S */
655 /* Enable caching on OCRAM and ROM */
656 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
659 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
665 #if defined(CONFIG_FEC_MXC)
666 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
668 unsigned int mac0, mac1;
671 if (dev_id < 0 || dev_id > 2)
674 if (fuse_read(4, 2, &mac0)) {
675 printf("Failed to read MAC0 fuse\n");
678 if (fuse_read(4, 3, &mac1)) {
679 printf("Failed to read MAC1 fuse\n");
696 void boot_mode_apply(unsigned cfg_val)
699 struct src *psrc = (struct src *)SRC_BASE_ADDR;
700 writel(cfg_val, &psrc->gpr9);
701 reg = readl(&psrc->gpr10);
706 writel(reg, &psrc->gpr10);
709 * cfg_val will be used for
710 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
711 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
712 * instead of SBMR1 to determine the boot device.
714 const struct boot_mode soc_boot_modes[] = {
715 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
716 /* reserved value should start rom usb */
717 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
718 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
719 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
720 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
721 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
722 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
723 /* 4 bit bus width */
724 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
725 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
726 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
727 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
733 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
734 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
737 u32 reg, periph1, periph2;
739 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
742 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
743 * to make sure PFD is working right, otherwise, PFDs may
744 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
745 * workaround in ROM code, as bus clock need it
748 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
749 ANATOP_PFD_CLKGATE_MASK(1) |
750 ANATOP_PFD_CLKGATE_MASK(2) |
751 ANATOP_PFD_CLKGATE_MASK(3);
752 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
753 ANATOP_PFD_CLKGATE_MASK(3);
755 reg = readl(&ccm->cbcmr);
756 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
757 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
758 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
759 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
761 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
762 if ((periph2 != 0x2) && (periph1 != 0x2))
763 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
765 if ((periph2 != 0x1) && (periph1 != 0x1) &&
766 (periph2 != 0x3) && (periph1 != 0x3))
767 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
769 writel(mask480, &anatop->pfd_480_set);
770 writel(mask528, &anatop->pfd_528_set);
771 writel(mask480, &anatop->pfd_480_clr);
772 writel(mask528, &anatop->pfd_528_clr);
775 #ifdef CONFIG_IMX_HDMI
776 void imx_enable_hdmi_phy(void)
778 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
780 reg = readb(&hdmi->phy_conf0);
781 reg |= HDMI_PHY_CONF0_PDZ_MASK;
782 writeb(reg, &hdmi->phy_conf0);
784 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
785 writeb(reg, &hdmi->phy_conf0);
787 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
788 writeb(reg, &hdmi->phy_conf0);
789 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
792 void imx_setup_hdmi(void)
794 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
795 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
798 /* Turn on HDMI PHY clock */
799 reg = readl(&mxc_ccm->CCGR2);
800 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
801 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
802 writel(reg, &mxc_ccm->CCGR2);
803 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
804 reg = readl(&mxc_ccm->chsccdr);
805 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
806 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
807 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
808 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
809 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
810 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
811 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
812 writel(reg, &mxc_ccm->chsccdr);
816 #ifndef CONFIG_SYS_L2CACHE_OFF
817 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
818 void v7_outer_cache_enable(void)
820 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
825 * Set bit 22 in the auxiliary control register. If this bit
826 * is cleared, PL310 treats Normal Shared Non-cacheable
827 * accesses as Cacheable no-allocate.
829 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
831 #if defined CONFIG_SOC_MX6SL
832 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
833 val = readl(&iomux->gpr[11]);
834 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
835 /* L2 cache configured as OCRAM, reset it */
836 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
837 writel(val, &iomux->gpr[11]);
841 /* Must disable the L2 before changing the latency parameters */
842 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
844 writel(0x132, &pl310->pl310_tag_latency_ctrl);
845 writel(0x132, &pl310->pl310_data_latency_ctrl);
847 val = readl(&pl310->pl310_prefetch_ctrl);
849 /* Turn on the L2 I/D prefetch */
853 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
854 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
855 * But according to ARM PL310 errata: 752271
856 * ID: 752271: Double linefill feature can cause data corruption
857 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
858 * Workaround: The only workaround to this erratum is to disable the
859 * double linefill feature. This is the default behavior.
862 #ifndef CONFIG_SOC_MX6Q
865 writel(val, &pl310->pl310_prefetch_ctrl);
867 val = readl(&pl310->pl310_power_ctrl);
868 val |= L2X0_DYNAMIC_CLK_GATING_EN;
869 val |= L2X0_STNDBY_MODE_EN;
870 writel(val, &pl310->pl310_power_ctrl);
872 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
875 void v7_outer_cache_disable(void)
877 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
879 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
881 #endif /* !CONFIG_SYS_L2CACHE_OFF */