3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <imx_thermal.h>
16 #include <asm/armv7.h>
17 #include <asm/bootm.h>
18 #include <asm/pl310.h>
19 #include <asm/errno.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/regs-ocotp.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/mxc_hdmi.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/imx-common/boot_mode.h>
28 #include <asm/imx-common/dma.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define __data __attribute__((section(".data")))
34 #ifdef CONFIG_MX6_TEMPERATURE_MIN
35 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
37 #define TEMPERATURE_MIN (-40)
39 #ifdef CONFIG_MX6_TEMPERATURE_HOT
40 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
42 #define TEMPERATURE_HOT 80
44 #ifdef CONFIG_MX6_TEMPERATURE_MAX
45 #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
47 #define TEMPERATURE_MAX 125
49 #define TEMP_AVG_COUNT 5
50 #define TEMP_WARN_THRESHOLD 5
66 #if defined(CONFIG_IMX6_THERMAL)
67 static const struct imx_thermal_plat imx6_thermal_plat = {
68 .regs = (void *)ANATOP_BASE_ADDR,
73 U_BOOT_DEVICE(imx6_thermal) = {
74 .name = "imx_thermal",
75 .platdata = &imx6_thermal_plat,
81 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
82 return readl(&scu->config) & 3;
87 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
88 u32 reg = readl(&anatop->digprog_sololite);
89 u32 type = ((reg >> 16) & 0xff);
92 if (type != MXC_CPU_MX6SL) {
93 reg = readl(&anatop->digprog);
94 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
95 u32 cfg = readl(&scu->config) & 3;
96 type = ((reg >> 16) & 0xff);
97 if (type == MXC_CPU_MX6DL) {
99 type = MXC_CPU_MX6SOLO;
102 if (type == MXC_CPU_MX6Q) {
108 major = ((reg >> 8) & 0xff);
109 reg &= 0xff; /* mx6 silicon revision */
110 return (type << 12) | (reg + (0x10 * (major + 1)));
114 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
115 * defines a 2-bit SPEED_GRADING
117 #define OCOTP_CFG3_SPEED_SHIFT 16
118 #define OCOTP_CFG3_SPEED_800MHZ 0
119 #define OCOTP_CFG3_SPEED_850MHZ 1
120 #define OCOTP_CFG3_SPEED_1GHZ 2
121 #define OCOTP_CFG3_SPEED_1P2GHZ 3
123 u32 get_cpu_speed_grade_hz(void)
125 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
126 struct fuse_bank *bank = &ocotp->bank[0];
127 struct fuse_bank0_regs *fuse =
128 (struct fuse_bank0_regs *)bank->fuse_regs;
131 val = readl(&fuse->cfg3);
132 val >>= OCOTP_CFG3_SPEED_SHIFT;
136 /* Valid for IMX6DQ */
137 case OCOTP_CFG3_SPEED_1P2GHZ:
138 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
140 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
141 case OCOTP_CFG3_SPEED_1GHZ:
143 /* Valid for IMX6DQ */
144 case OCOTP_CFG3_SPEED_850MHZ:
145 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
147 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
148 case OCOTP_CFG3_SPEED_800MHZ:
155 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
156 * defines a 2-bit Temperature Grade
158 * return temperature grade and min/max temperature in celcius
160 #define OCOTP_MEM0_TEMP_SHIFT 6
162 u32 get_cpu_temp_grade(int *minc, int *maxc)
164 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
165 struct fuse_bank *bank = &ocotp->bank[1];
166 struct fuse_bank1_regs *fuse =
167 (struct fuse_bank1_regs *)bank->fuse_regs;
170 val = readl(&fuse->mem0);
171 val >>= OCOTP_MEM0_TEMP_SHIFT;
175 if (val == TEMP_AUTOMOTIVE) {
178 } else if (val == TEMP_INDUSTRIAL) {
181 } else if (val == TEMP_EXTCOMMERCIAL) {
192 #ifdef CONFIG_REVISION_TAG
193 u32 __weak get_board_rev(void)
195 u32 cpurev = get_cpu_rev();
196 u32 type = ((cpurev >> 12) & 0xff);
197 if (type == MXC_CPU_MX6SOLO)
198 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
200 if (type == MXC_CPU_MX6D)
201 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
209 struct aipstz_regs *aips1, *aips2;
210 #ifdef CONFIG_SOC_MX6SX
211 struct aipstz_regs *aips3;
214 aips1 = (struct aipstz_regs *)AIPS1_ARB_BASE_ADDR;
215 aips2 = (struct aipstz_regs *)AIPS2_ARB_BASE_ADDR;
216 #ifdef CONFIG_SOC_MX6SX
217 aips3 = (struct aipstz_regs *)AIPS3_ARB_BASE_ADDR;
221 * Set all MPROTx to be non-bufferable, trusted for R/W,
222 * not forced to user-mode.
224 writel(0x77777777, &aips1->mprot0);
225 writel(0x77777777, &aips1->mprot1);
226 writel(0x77777777, &aips2->mprot0);
227 writel(0x77777777, &aips2->mprot1);
230 * Set all OPACRx to be non-bufferable, not require
231 * supervisor privilege level for access,allow for
232 * write access and untrusted master access.
234 writel(0x00000000, &aips1->opacr0);
235 writel(0x00000000, &aips1->opacr1);
236 writel(0x00000000, &aips1->opacr2);
237 writel(0x00000000, &aips1->opacr3);
238 writel(0x00000000, &aips1->opacr4);
239 writel(0x00000000, &aips2->opacr0);
240 writel(0x00000000, &aips2->opacr1);
241 writel(0x00000000, &aips2->opacr2);
242 writel(0x00000000, &aips2->opacr3);
243 writel(0x00000000, &aips2->opacr4);
245 #ifdef CONFIG_SOC_MX6SX
247 * Set all MPROTx to be non-bufferable, trusted for R/W,
248 * not forced to user-mode.
250 writel(0x77777777, &aips3->mprot0);
251 writel(0x77777777, &aips3->mprot1);
254 * Set all OPACRx to be non-bufferable, not require
255 * supervisor privilege level for access,allow for
256 * write access and untrusted master access.
258 writel(0x00000000, &aips3->opacr0);
259 writel(0x00000000, &aips3->opacr1);
260 writel(0x00000000, &aips3->opacr2);
261 writel(0x00000000, &aips3->opacr3);
262 writel(0x00000000, &aips3->opacr4);
266 static void clear_ldo_ramp(void)
268 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
271 /* ROM may modify LDO ramp up time according to fuse setting, so in
272 * order to be in the safe side we neeed to reset these settings to
273 * match the reset value: 0'b00
275 reg = readl(&anatop->ana_misc2);
276 reg &= ~(0x3f << 24);
277 writel(reg, &anatop->ana_misc2);
281 * Set the PMU_REG_CORE register
283 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
284 * Possible values are from 0.725V to 1.450V in steps of
287 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
289 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
290 u32 val, step, old, reg = readl(&anatop->reg_core);
294 val = 0x00; /* Power gated off */
296 val = 0x1F; /* Power FET switched full on. No regulation */
298 val = (mv - 700) / 25;
316 old = (reg & (0x1F << shift)) >> shift;
317 step = abs(val - old);
321 reg = (reg & ~(0x1F << shift)) | (val << shift);
322 writel(reg, &anatop->reg_core);
325 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
333 static u32 __data thermal_calib;
335 #define FACTOR0 10000000
336 #define FACTOR1 15976
337 #define FACTOR2 4297157
339 int raw_to_celsius(unsigned int raw, unsigned int raw_25c, unsigned int raw_hot,
340 unsigned int hot_temp)
344 if (raw_hot != 0 && hot_temp != 0) {
345 unsigned int raw_n40c, ratio;
347 ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
348 raw_n40c = raw_25c + (13 * ratio) / 20;
350 temperature = (raw_n40c - raw) * 100 / ratio - 40;
352 temperature = TEMPERATURE_MIN;
354 u64 temp64 = FACTOR0;
357 * Derived from linear interpolation:
358 * slope = 0.4297157 - (0.0015976 * 25C fuse)
359 * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
360 * (Nmeas - n1) / (Tmeas - t1) = slope
361 * We want to reduce this down to the minimum computation necessary
362 * for each temperature read. Also, we want Tmeas in millicelsius
363 * and we don't want to lose precision from integer division. So...
364 * Tmeas = (Nmeas - n1) / slope + t1
365 * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
366 * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
367 * Let constant c1 = (-1000 / slope)
368 * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
369 * Let constant c2 = n1 *c1 + 1000 * t1
370 * milli_Tmeas = c2 - Nmeas * c1
373 do_div(temp64, FACTOR1 * raw_25c - FACTOR2);
375 c2 = raw_25c * c1 + 1000 * 25;
376 temperature = (c2 - raw * c1) / 1000;
381 int read_cpu_temperature(void)
383 unsigned int reg, tmp, i;
384 unsigned int raw_25c, raw_hot, hot_temp;
386 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
387 struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
389 if (!thermal_calib) {
391 writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
392 thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
393 writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
397 if (thermal_calib == 0 || thermal_calib == 0xffffffff)
398 return TEMPERATURE_MIN;
401 * [31:20] sensor value @ 25C
402 * [19:8] sensor value of hot
403 * [7:0] hot temperature value */
404 raw_25c = thermal_calib >> 20;
405 raw_hot = (thermal_calib & 0xfff00) >> 8;
406 hot_temp = thermal_calib & 0xff;
408 /* now we only using single measure, every time we measure
409 * the temperature, we will power on/off the anadig module
411 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
412 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
414 /* write measure freq */
415 writel(327, &anatop->tempsense1);
416 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
417 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
418 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
420 /* average the temperature value over multiple readings */
421 for (i = 0; i < TEMP_AVG_COUNT; i++) {
425 while ((readl(&anatop->tempsense0) &
426 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
431 if ((readl(&anatop->tempsense0) &
432 BM_ANADIG_TEMPSENSE0_FINISHED) == 0) {
434 printf("Failed to read temp sensor\n");
440 reg = (readl(&anatop->tempsense0) &
441 BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
442 BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
446 tmp = (tmp * i + reg) / (i + 1);
447 writel(BM_ANADIG_TEMPSENSE0_FINISHED,
448 &anatop->tempsense0_clr);
451 temperature = raw_to_celsius(tmp, raw_25c, raw_hot, hot_temp);
453 /* power down anatop thermal sensor */
454 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
455 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
460 int check_cpu_temperature(int boot)
462 static int __data max_temp;
463 int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
464 int tmp = read_cpu_temperature();
467 if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
468 printf("Temperature: can't get valid data!\n");
473 if (tmp > boot_limit) {
474 printf("CPU is %d C, too hot, resetting...\n", tmp);
478 if (tmp > max_temp) {
479 if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
480 printf("WARNING: CPU temperature %d C\n", tmp);
484 printf("Temperature: %d C, calibration data 0x%x\n",
486 while (tmp >= boot_limit) {
488 printf("CPU is %d C, too hot to boot, waiting...\n",
495 tmp = read_cpu_temperature();
496 if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
497 printf("WARNING: CPU temperature %d C\n", tmp);
504 static void imx_set_wdog_powerdown(bool enable)
506 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
507 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
510 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
511 writew(enable, &wdog3->wmcr);
514 /* Write to the PDE (Power Down Enable) bit */
515 writew(enable, &wdog1->wmcr);
516 writew(enable, &wdog2->wmcr);
519 static void set_ahb_rate(u32 val)
521 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
524 div = get_periph_clk() / val - 1;
525 reg = readl(&mxc_ccm->cbcdr);
527 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
528 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
531 static void clear_mmdc_ch_mask(void)
533 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
535 /* Clear MMDC channel mask */
536 writel(0, &mxc_ccm->ccdr);
539 static void init_bandgap(void)
541 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
543 * Ensure the bandgap has stabilized.
545 while (!(readl(&anatop->ana_misc0) & 0x80))
548 * For best noise performance of the analog blocks using the
549 * outputs of the bandgap, the reftop_selfbiasoff bit should
552 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
555 #ifdef CONFIG_SOC_MX6SL
556 static void set_preclk_from_osc(void)
558 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
561 reg = readl(&mxc_ccm->cscmr1);
562 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
563 writel(reg, &mxc_ccm->cscmr1);
567 #define SRC_SCR_WARM_RESET_ENABLE 0
569 static void init_src(void)
571 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
575 * force warm reset sources to generate cold reset
576 * for a more reliable restart
578 val = readl(&src_regs->scr);
579 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
580 writel(val, &src_regs->scr);
583 int arch_cpu_init(void)
587 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
588 clear_mmdc_ch_mask();
591 * Disable self-bias circuit in the analog bandap.
592 * The self-bias circuit is used by the bandgap during startup.
593 * This bit should be set after the bandgap has initialized.
598 * When low freq boot is enabled, ROM will not set AHB
599 * freq, so we need to ensure AHB freq is 132MHz in such
602 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
603 set_ahb_rate(132000000);
605 /* Set perclk to source from OSC 24MHz */
606 #if defined(CONFIG_SOC_MX6SL)
607 set_preclk_from_osc();
610 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
612 #ifdef CONFIG_VIDEO_IPUV3
613 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
615 #ifdef CONFIG_APBH_DMA
616 /* Timer is required for Initializing APBH DMA */
626 int board_postclk_init(void)
628 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
633 #ifndef CONFIG_SYS_DCACHE_OFF
634 void enable_caches(void)
636 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
637 enum dcache_option option = DCACHE_WRITETHROUGH;
639 enum dcache_option option = DCACHE_WRITEBACK;
642 /* Avoid random hang when download by usb */
643 invalidate_dcache_all();
645 /* Enable D-cache. I-cache is already enabled in start.S */
648 /* Enable caching on OCRAM and ROM */
649 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
652 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
658 #if defined(CONFIG_FEC_MXC)
659 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
661 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
662 struct fuse_bank *bank = &ocotp->bank[4];
663 struct fuse_bank4_regs *fuse =
664 (struct fuse_bank4_regs *)bank->fuse_regs;
666 u32 value = readl(&fuse->mac_addr_high);
667 mac[0] = (value >> 8);
670 value = readl(&fuse->mac_addr_low);
671 mac[2] = value >> 24;
672 mac[3] = value >> 16;
678 void boot_mode_apply(unsigned cfg_val)
681 struct src *psrc = (struct src *)SRC_BASE_ADDR;
682 writel(cfg_val, &psrc->gpr9);
683 reg = readl(&psrc->gpr10);
688 writel(reg, &psrc->gpr10);
691 * cfg_val will be used for
692 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
693 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
694 * instead of SBMR1 to determine the boot device.
696 const struct boot_mode soc_boot_modes[] = {
697 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
698 /* reserved value should start rom usb */
699 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
700 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
701 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
702 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
703 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
704 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
705 /* 4 bit bus width */
706 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
707 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
708 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
709 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
715 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
716 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
719 u32 reg, periph1, periph2;
721 if (is_cpu_type(MXC_CPU_MX6SX))
724 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
725 * to make sure PFD is working right, otherwise, PFDs may
726 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
727 * workaround in ROM code, as bus clock need it
730 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
731 ANATOP_PFD_CLKGATE_MASK(1) |
732 ANATOP_PFD_CLKGATE_MASK(2) |
733 ANATOP_PFD_CLKGATE_MASK(3);
734 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
735 ANATOP_PFD_CLKGATE_MASK(3);
737 reg = readl(&ccm->cbcmr);
738 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
739 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
740 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
741 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
743 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
744 if ((periph2 != 0x2) && (periph1 != 0x2))
745 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
747 if ((periph2 != 0x1) && (periph1 != 0x1) &&
748 (periph2 != 0x3) && (periph1 != 0x3))
749 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
751 writel(mask480, &anatop->pfd_480_set);
752 writel(mask528, &anatop->pfd_528_set);
753 writel(mask480, &anatop->pfd_480_clr);
754 writel(mask528, &anatop->pfd_528_clr);
757 #ifdef CONFIG_IMX_HDMI
758 void imx_enable_hdmi_phy(void)
760 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
762 reg = readb(&hdmi->phy_conf0);
763 reg |= HDMI_PHY_CONF0_PDZ_MASK;
764 writeb(reg, &hdmi->phy_conf0);
766 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
767 writeb(reg, &hdmi->phy_conf0);
769 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
770 writeb(reg, &hdmi->phy_conf0);
771 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
774 void imx_setup_hdmi(void)
776 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
777 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
780 /* Turn on HDMI PHY clock */
781 reg = readl(&mxc_ccm->CCGR2);
782 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
783 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
784 writel(reg, &mxc_ccm->CCGR2);
785 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
786 reg = readl(&mxc_ccm->chsccdr);
787 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
788 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
789 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
790 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
791 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
792 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
793 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
794 writel(reg, &mxc_ccm->chsccdr);
798 #ifndef CONFIG_SYS_L2CACHE_OFF
799 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
800 void v7_outer_cache_enable(void)
802 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
807 * Set bit 22 in the auxiliary control register. If this bit
808 * is cleared, PL310 treats Normal Shared Non-cacheable
809 * accesses as Cacheable no-allocate.
811 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
813 #if defined CONFIG_SOC_MX6SL
814 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
815 val = readl(&iomux->gpr[11]);
816 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
817 /* L2 cache configured as OCRAM, reset it */
818 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
819 writel(val, &iomux->gpr[11]);
823 /* Must disable the L2 before changing the latency parameters */
824 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
826 writel(0x132, &pl310->pl310_tag_latency_ctrl);
827 writel(0x132, &pl310->pl310_data_latency_ctrl);
829 val = readl(&pl310->pl310_prefetch_ctrl);
831 /* Turn on the L2 I/D prefetch */
835 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
836 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
837 * But according to ARM PL310 errata: 752271
838 * ID: 752271: Double linefill feature can cause data corruption
839 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
840 * Workaround: The only workaround to this erratum is to disable the
841 * double linefill feature. This is the default behavior.
844 #ifndef CONFIG_SOC_MX6Q
847 writel(val, &pl310->pl310_prefetch_ctrl);
849 val = readl(&pl310->pl310_power_ctrl);
850 val |= L2X0_DYNAMIC_CLK_GATING_EN;
851 val |= L2X0_STNDBY_MODE_EN;
852 writel(val, &pl310->pl310_power_ctrl);
854 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
857 void v7_outer_cache_disable(void)
859 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
861 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
863 #endif /* !CONFIG_SYS_L2CACHE_OFF */