arch/arm/cpu/armv7/omap-common/emif-common.c

   1 /*
   2  * EMIF programming
   3  *
   4  * (C) Copyright 2010
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * Aneesh V <aneesh@ti.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/emif.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/utils.h>
  18 #include <linux/compiler.h>
  19
  20 static int emif1_enabled = -1, emif2_enabled = -1;
  21
  22 void set_lpmode_selfrefresh(u32 base)
  23 {
  24         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  25         u32 reg;
  26
  27         reg = readl(&emif->emif_pwr_mgmt_ctrl);
  28         reg &= ~EMIF_REG_LP_MODE_MASK;
  29         reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  30         reg &= ~EMIF_REG_SR_TIM_MASK;
  31         writel(reg, &emif->emif_pwr_mgmt_ctrl);
  32
  33         /* dummy read for the new SR_TIM to be loaded */
  34         readl(&emif->emif_pwr_mgmt_ctrl);
  35 }
  36
  37 void force_emif_self_refresh()
  38 {
  39         set_lpmode_selfrefresh(EMIF1_BASE);
  40         set_lpmode_selfrefresh(EMIF2_BASE);
  41 }
  42
  43 inline u32 emif_num(u32 base)
  44 {
  45         if (base == EMIF1_BASE)
  46                 return 1;
  47         else if (base == EMIF2_BASE)
  48                 return 2;
  49         else
  50                 return 0;
  51 }
  52
  53 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  54 {
  55         u32 mr;
  56         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  57
  58         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  59         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  60         if (omap_revision() == OMAP4430_ES2_0)
  61                 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  62         else
  63                 mr = readl(&emif->emif_lpddr2_mode_reg_data);
  64         debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  65               cs, mr_addr, mr);
  66         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  67             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  68             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  69                 return mr & 0xff;
  70         else
  71                 return mr;
  72 }
  73
  74 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  75 {
  76         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  77
  78         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  79         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  80         writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  81 }
  82
  83 void emif_reset_phy(u32 base)
  84 {
  85         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  86         u32 iodft;
  87
  88         iodft = readl(&emif->emif_iodft_tlgc);
  89         iodft |= EMIF_REG_RESET_PHY_MASK;
  90         writel(iodft, &emif->emif_iodft_tlgc);
  91 }
  92
  93 static void do_lpddr2_init(u32 base, u32 cs)
  94 {
  95         u32 mr_addr;
  96         const struct lpddr2_mr_regs *mr_regs;
  97
  98         get_lpddr2_mr_regs(&mr_regs);
  99         /* Wait till device auto initialization is complete */
 100         while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 101                 ;
 102         set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
 103         /*
 104          * tZQINIT = 1 us
 105          * Enough loops assuming a maximum of 2GHz
 106          */
 107
 108         sdelay(2000);
 109
 110         set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
 111         set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 112
 113         /*
 114          * Enable refresh along with writing MR2
 115          * Encoding of RL in MR2 is (RL - 2)
 116          */
 117         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 118         set_mr(base, cs, mr_addr, mr_regs->mr2);
 119
 120         if (mr_regs->mr3 > 0)
 121                 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 122 }
 123
 124 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 125 {
 126         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 127
 128         /* Not NVM */
 129         clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
 130
 131         /*
 132          * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
 133          * when EMIF_SDRAM_CONFIG register is written
 134          */
 135         setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 136
 137         /*
 138          * Set the SDRAM_CONFIG and PHY_CTRL for the
 139          * un-locked frequency & default RL
 140          */
 141         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 142         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 143
 144         do_ext_phy_settings(base, regs);
 145
 146         do_lpddr2_init(base, CS0);
 147         if (regs->sdram_config & EMIF_REG_EBANK_MASK)
 148                 do_lpddr2_init(base, CS1);
 149
 150         writel(regs->sdram_config, &emif->emif_sdram_config);
 151         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 152
 153         /* Enable refresh now */
 154         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 155
 156         }
 157
 158 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 159 {
 160 }
 161
 162 void emif_update_timings(u32 base, const struct emif_regs *regs)
 163 {
 164         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 165
 166         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
 167         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 168         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 169         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
 170         if (omap_revision() == OMAP4430_ES1_0) {
 171                 /* ES1 bug EMIF should be in force idle during freq_update */
 172                 writel(0, &emif->emif_pwr_mgmt_ctrl);
 173         } else {
 174                 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 175                 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 176         }
 177         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
 178         writel(regs->zq_config, &emif->emif_zq_config);
 179         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 180         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 181
 182         if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 183                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 184                         &emif->emif_l3_config);
 185         } else if (omap_revision() >= OMAP4460_ES1_0) {
 186                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
 187                         &emif->emif_l3_config);
 188         } else {
 189                 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
 190                         &emif->emif_l3_config);
 191         }
 192 }
 193
 194 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 195 {
 196         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 197
 198         /* keep sdram in self-refresh */
 199         writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
 200                 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 201         __udelay(130);
 202
 203         /*
 204          * Set invert_clkout (if activated)--DDR_PHYCTRL_1
 205          * Invert clock adds an additional half cycle delay on the
 206          * command interface.  The additional half cycle, is usually
 207          * meant to enable leveling in the situation that DQS is later
 208          * than CK on the board.It also helps provide some additional
 209          * margin for leveling.
 210          */
 211         writel(regs->emif_ddr_phy_ctlr_1,
 212                &emif->emif_ddr_phy_ctrl_1);
 213
 214         writel(regs->emif_ddr_phy_ctlr_1,
 215                &emif->emif_ddr_phy_ctrl_1_shdw);
 216         __udelay(130);
 217
 218         writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
 219                & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 220
 221         /* Launch Full leveling */
 222         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 223
 224         /* Wait till full leveling is complete */
 225         readl(&emif->emif_rd_wr_lvl_ctl);
 226               __udelay(130);
 227
 228         /* Read data eye leveling no of samples */
 229         config_data_eye_leveling_samples(base);
 230
 231         /*
 232          * Launch 8 incremental WR_LVL- to compensate for
 233          * PHY limitation.
 234          */
 235         writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
 236                &emif->emif_rd_wr_lvl_ctl);
 237
 238         __udelay(130);
 239
 240         /* Launch Incremental leveling */
 241         writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
 242                __udelay(130);
 243 }
 244
 245 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 246 {
 247         if (is_omap54xx())
 248                 omap5_ddr3_leveling(base, regs);
 249 }
 250
 251 static void ddr3_init(u32 base, const struct emif_regs *regs)
 252 {
 253         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 254
 255         /*
 256          * Set SDRAM_CONFIG and PHY control registers to locked frequency
 257          * and RL =7. As the default values of the Mode Registers are not
 258          * defined, contents of mode Registers must be fully initialized.
 259          * H/W takes care of this initialization
 260          */
 261         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 262
 263         /* Update timing registers */
 264         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 265         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 266         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 267
 268         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 269         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 270
 271         /*
 272          * The same sequence should work on OMAP5432 as well. But strange that
 273          * it is not working
 274          */
 275         if (is_dra7xx()) {
 276                 do_ext_phy_settings(base, regs);
 277                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 278                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 279         } else {
 280                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 281                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 282                 do_ext_phy_settings(base, regs);
 283         }
 284
 285         /* enable leveling */
 286         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 287
 288         ddr3_leveling(base, regs);
 289 }
 290
 291 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 292 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 293
 294 /*
 295  * Organization and refresh requirements for LPDDR2 devices of different
 296  * types and densities. Derived from JESD209-2 section 2.4
 297  */
 298 const struct lpddr2_addressing addressing_table[] = {
 299         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16  density */
 300         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
 301         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
 302         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
 303         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
 304         {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
 305         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
 306         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
 307         {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
 308         {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
 309         {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
 310 };
 311
 312 static const u32 lpddr2_density_2_size_in_mbytes[] = {
 313         8,                      /* 64Mb */
 314         16,                     /* 128Mb */
 315         32,                     /* 256Mb */
 316         64,                     /* 512Mb */
 317         128,                    /* 1Gb   */
 318         256,                    /* 2Gb   */
 319         512,                    /* 4Gb   */
 320         1024,                   /* 8Gb   */
 321         2048,                   /* 16Gb  */
 322         4096                    /* 32Gb  */
 323 };
 324
 325 /*
 326  * Calculate the period of DDR clock from frequency value and set the
 327  * denominator and numerator in global variables for easy access later
 328  */
 329 static void set_ddr_clk_period(u32 freq)
 330 {
 331         /*
 332          * period = 1/freq
 333          * period_in_ns = 10^9/freq
 334          */
 335         *T_num = 1000000000;
 336         *T_den = freq;
 337         cancel_out(T_num, T_den, 200);
 338
 339 }
 340
 341 /*
 342  * Convert time in nano seconds to number of cycles of DDR clock
 343  */
 344 static inline u32 ns_2_cycles(u32 ns)
 345 {
 346         return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
 347 }
 348
 349 /*
 350  * ns_2_cycles with the difference that the time passed is 2 times the actual
 351  * value(to avoid fractions). The cycles returned is for the original value of
 352  * the timing parameter
 353  */
 354 static inline u32 ns_x2_2_cycles(u32 ns)
 355 {
 356         return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
 357 }
 358
 359 /*
 360  * Find addressing table index based on the device's type(S2 or S4) and
 361  * density
 362  */
 363 s8 addressing_table_index(u8 type, u8 density, u8 width)
 364 {
 365         u8 index;
 366         if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
 367                 return -1;
 368
 369         /*
 370          * Look at the way ADDR_TABLE_INDEX* values have been defined
 371          * in emif.h compared to LPDDR2_DENSITY_* values
 372          * The table is layed out in the increasing order of density
 373          * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
 374          * at the end
 375          */
 376         if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
 377                 index = ADDR_TABLE_INDEX1GS2;
 378         else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
 379                 index = ADDR_TABLE_INDEX2GS2;
 380         else
 381                 index = density;
 382
 383         debug("emif: addressing table index %d\n", index);
 384
 385         return index;
 386 }
 387
 388 /*
 389  * Find the the right timing table from the array of timing
 390  * tables of the device using DDR clock frequency
 391  */
 392 static const struct lpddr2_ac_timings *get_timings_table(const struct
 393                         lpddr2_ac_timings const *const *device_timings,
 394                         u32 freq)
 395 {
 396         u32 i, temp, freq_nearest;
 397         const struct lpddr2_ac_timings *timings = 0;
 398
 399         emif_assert(freq <= MAX_LPDDR2_FREQ);
 400         emif_assert(device_timings);
 401
 402         /*
 403          * Start with the maximum allowed frequency - that is always safe
 404          */
 405         freq_nearest = MAX_LPDDR2_FREQ;
 406         /*
 407          * Find the timings table that has the max frequency value:
 408          *   i.  Above or equal to the DDR frequency - safe
 409          *   ii. The lowest that satisfies condition (i) - optimal
 410          */
 411         for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
 412                 temp = device_timings[i]->max_freq;
 413                 if ((temp >= freq) && (temp <= freq_nearest)) {
 414                         freq_nearest = temp;
 415                         timings = device_timings[i];
 416                 }
 417         }
 418         debug("emif: timings table: %d\n", freq_nearest);
 419         return timings;
 420 }
 421
 422 /*
 423  * Finds the value of emif_sdram_config_reg
 424  * All parameters are programmed based on the device on CS0.
 425  * If there is a device on CS1, it will be same as that on CS0 or
 426  * it will be NVM. We don't support NVM yet.
 427  * If cs1_device pointer is NULL it is assumed that there is no device
 428  * on CS1
 429  */
 430 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
 431                                 const struct lpddr2_device_details *cs1_device,
 432                                 const struct lpddr2_addressing *addressing,
 433                                 u8 RL)
 434 {
 435         u32 config_reg = 0;
 436
 437         config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
 438         config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
 439                         EMIF_REG_IBANK_POS_SHIFT;
 440
 441         config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
 442
 443         config_reg |= RL << EMIF_REG_CL_SHIFT;
 444
 445         config_reg |= addressing->row_sz[cs0_device->io_width] <<
 446                         EMIF_REG_ROWSIZE_SHIFT;
 447
 448         config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
 449
 450         config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
 451                         EMIF_REG_EBANK_SHIFT;
 452
 453         config_reg |= addressing->col_sz[cs0_device->io_width] <<
 454                         EMIF_REG_PAGESIZE_SHIFT;
 455
 456         return config_reg;
 457 }
 458
 459 static u32 get_sdram_ref_ctrl(u32 freq,
 460                               const struct lpddr2_addressing *addressing)
 461 {
 462         u32 ref_ctrl = 0, val = 0, freq_khz;
 463         freq_khz = freq / 1000;
 464         /*
 465          * refresh rate to be set is 'tREFI * freq in MHz
 466          * division by 10000 to account for khz and x10 in t_REFI_us_x10
 467          */
 468         val = addressing->t_REFI_us_x10 * freq_khz / 10000;
 469         ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
 470
 471         return ref_ctrl;
 472 }
 473
 474 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
 475                                const struct lpddr2_min_tck *min_tck,
 476                                const struct lpddr2_addressing *addressing)
 477 {
 478         u32 tim1 = 0, val = 0;
 479         val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
 480         tim1 |= val << EMIF_REG_T_WTR_SHIFT;
 481
 482         if (addressing->num_banks == BANKS8)
 483                 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
 484                                                         (4 * (*T_num)) - 1;
 485         else
 486                 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
 487
 488         tim1 |= val << EMIF_REG_T_RRD_SHIFT;
 489
 490         val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
 491         tim1 |= val << EMIF_REG_T_RC_SHIFT;
 492
 493         val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
 494         tim1 |= val << EMIF_REG_T_RAS_SHIFT;
 495
 496         val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
 497         tim1 |= val << EMIF_REG_T_WR_SHIFT;
 498
 499         val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
 500         tim1 |= val << EMIF_REG_T_RCD_SHIFT;
 501
 502         val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
 503         tim1 |= val << EMIF_REG_T_RP_SHIFT;
 504
 505         return tim1;
 506 }
 507
 508 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
 509                                const struct lpddr2_min_tck *min_tck)
 510 {
 511         u32 tim2 = 0, val = 0;
 512         val = max(min_tck->tCKE, timings->tCKE) - 1;
 513         tim2 |= val << EMIF_REG_T_CKE_SHIFT;
 514
 515         val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
 516         tim2 |= val << EMIF_REG_T_RTP_SHIFT;
 517
 518         /*
 519          * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
 520          * same value
 521          */
 522         val = ns_2_cycles(timings->tXSR) - 1;
 523         tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
 524         tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
 525
 526         val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
 527         tim2 |= val << EMIF_REG_T_XP_SHIFT;
 528
 529         return tim2;
 530 }
 531
 532 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
 533                                const struct lpddr2_min_tck *min_tck,
 534                                const struct lpddr2_addressing *addressing)
 535 {
 536         u32 tim3 = 0, val = 0;
 537         val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
 538         tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
 539
 540         val = ns_2_cycles(timings->tRFCab) - 1;
 541         tim3 |= val << EMIF_REG_T_RFC_SHIFT;
 542
 543         val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
 544         tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
 545
 546         val = ns_2_cycles(timings->tZQCS) - 1;
 547         tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
 548
 549         val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
 550         tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
 551
 552         return tim3;
 553 }
 554
 555 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
 556                              const struct lpddr2_addressing *addressing,
 557                              u8 volt_ramp)
 558 {
 559         u32 zq = 0, val = 0;
 560         if (volt_ramp)
 561                 val =
 562                     EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
 563                     addressing->t_REFI_us_x10;
 564         else
 565                 val =
 566                     EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
 567                     addressing->t_REFI_us_x10;
 568         zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
 569
 570         zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
 571
 572         zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
 573
 574         zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
 575
 576         /*
 577          * Assuming that two chipselects have a single calibration resistor
 578          * If there are indeed two calibration resistors, then this flag should
 579          * be enabled to take advantage of dual calibration feature.
 580          * This data should ideally come from board files. But considering
 581          * that none of the boards today have calibration resistors per CS,
 582          * it would be an unnecessary overhead.
 583          */
 584         zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
 585
 586         zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
 587
 588         zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
 589
 590         return zq;
 591 }
 592
 593 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
 594                                  const struct lpddr2_addressing *addressing,
 595                                  u8 is_derated)
 596 {
 597         u32 alert = 0, interval;
 598         interval =
 599             TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
 600         if (is_derated)
 601                 interval *= 4;
 602         alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
 603
 604         alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
 605
 606         alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
 607
 608         alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
 609
 610         alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
 611
 612         alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
 613
 614         return alert;
 615 }
 616
 617 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 618 {
 619         u32 idle = 0, val = 0;
 620         if (volt_ramp)
 621                 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 622         else
 623                 /*Maximum value in normal conditions - suggested by hw team */
 624                 val = 0x1FF;
 625         idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
 626
 627         idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
 628
 629         return idle;
 630 }
 631
 632 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
 633 {
 634         u32 phy = 0, val = 0;
 635
 636         phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
 637
 638         if (freq <= 100000000)
 639                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
 640         else if (freq <= 200000000)
 641                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
 642         else
 643                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
 644         phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
 645
 646         /* Other fields are constant magic values. Hardcode them together */
 647         phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
 648                 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
 649
 650         return phy;
 651 }
 652
 653 static u32 get_emif_mem_size(u32 base)
 654 {
 655         u32 size_mbytes = 0, temp;
 656         struct emif_device_details dev_details;
 657         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
 658         u32 emif_nr = emif_num(base);
 659
 660         emif_reset_phy(base);
 661         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
 662                                                 &cs0_dev_details);
 663         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
 664                                                 &cs1_dev_details);
 665         emif_reset_phy(base);
 666
 667         if (dev_details.cs0_device_details) {
 668                 temp = dev_details.cs0_device_details->density;
 669                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 670         }
 671
 672         if (dev_details.cs1_device_details) {
 673                 temp = dev_details.cs1_device_details->density;
 674                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 675         }
 676         /* convert to bytes */
 677         return size_mbytes << 20;
 678 }
 679
 680 /* Gets the encoding corresponding to a given DMM section size */
 681 u32 get_dmm_section_size_map(u32 section_size)
 682 {
 683         /*
 684          * Section size mapping:
 685          * 0x0: 16-MiB section
 686          * 0x1: 32-MiB section
 687          * 0x2: 64-MiB section
 688          * 0x3: 128-MiB section
 689          * 0x4: 256-MiB section
 690          * 0x5: 512-MiB section
 691          * 0x6: 1-GiB section
 692          * 0x7: 2-GiB section
 693          */
 694         section_size >>= 24; /* divide by 16 MB */
 695         return log_2_n_round_down(section_size);
 696 }
 697
 698 static void emif_calculate_regs(
 699                 const struct emif_device_details *emif_dev_details,
 700                 u32 freq, struct emif_regs *regs)
 701 {
 702         u32 temp, sys_freq;
 703         const struct lpddr2_addressing *addressing;
 704         const struct lpddr2_ac_timings *timings;
 705         const struct lpddr2_min_tck *min_tck;
 706         const struct lpddr2_device_details *cs0_dev_details =
 707                                         emif_dev_details->cs0_device_details;
 708         const struct lpddr2_device_details *cs1_dev_details =
 709                                         emif_dev_details->cs1_device_details;
 710         const struct lpddr2_device_timings *cs0_dev_timings =
 711                                         emif_dev_details->cs0_device_timings;
 712
 713         emif_assert(emif_dev_details);
 714         emif_assert(regs);
 715         /*
 716          * You can not have a device on CS1 without one on CS0
 717          * So configuring EMIF without a device on CS0 doesn't
 718          * make sense
 719          */
 720         emif_assert(cs0_dev_details);
 721         emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
 722         /*
 723          * If there is a device on CS1 it should be same type as CS0
 724          * (or NVM. But NVM is not supported in this driver yet)
 725          */
 726         emif_assert((cs1_dev_details == NULL) ||
 727                     (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
 728                     (cs0_dev_details->type == cs1_dev_details->type));
 729         emif_assert(freq <= MAX_LPDDR2_FREQ);
 730
 731         set_ddr_clk_period(freq);
 732
 733         /*
 734          * The device on CS0 is used for all timing calculations
 735          * There is only one set of registers for timings per EMIF. So, if the
 736          * second CS(CS1) has a device, it should have the same timings as the
 737          * device on CS0
 738          */
 739         timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
 740         emif_assert(timings);
 741         min_tck = cs0_dev_timings->min_tck;
 742
 743         temp = addressing_table_index(cs0_dev_details->type,
 744                                       cs0_dev_details->density,
 745                                       cs0_dev_details->io_width);
 746
 747         emif_assert((temp >= 0));
 748         addressing = &(addressing_table[temp]);
 749         emif_assert(addressing);
 750
 751         sys_freq = get_sys_clk_freq();
 752
 753         regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
 754                                                         cs1_dev_details,
 755                                                         addressing, RL_BOOT);
 756
 757         regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
 758                                                 cs1_dev_details,
 759                                                 addressing, RL_FINAL);
 760
 761         regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
 762
 763         regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
 764
 765         regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
 766
 767         regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
 768
 769         regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
 770
 771         regs->temp_alert_config =
 772             get_temp_alert_config(cs1_dev_details, addressing, 0);
 773
 774         regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
 775                                             LPDDR2_VOLTAGE_STABLE);
 776
 777         regs->emif_ddr_phy_ctlr_1_init =
 778                         get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
 779
 780         regs->emif_ddr_phy_ctlr_1 =
 781                         get_ddr_phy_ctrl_1(freq, RL_FINAL);
 782
 783         regs->freq = freq;
 784
 785         print_timing_reg(regs->sdram_config_init);
 786         print_timing_reg(regs->sdram_config);
 787         print_timing_reg(regs->ref_ctrl);
 788         print_timing_reg(regs->sdram_tim1);
 789         print_timing_reg(regs->sdram_tim2);
 790         print_timing_reg(regs->sdram_tim3);
 791         print_timing_reg(regs->read_idle_ctrl);
 792         print_timing_reg(regs->temp_alert_config);
 793         print_timing_reg(regs->zq_config);
 794         print_timing_reg(regs->emif_ddr_phy_ctlr_1);
 795         print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
 796 }
 797 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 798
 799 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 800 const char *get_lpddr2_type(u8 type_id)
 801 {
 802         switch (type_id) {
 803         case LPDDR2_TYPE_S4:
 804                 return "LPDDR2-S4";
 805         case LPDDR2_TYPE_S2:
 806                 return "LPDDR2-S2";
 807         default:
 808                 return NULL;
 809         }
 810 }
 811
 812 const char *get_lpddr2_io_width(u8 width_id)
 813 {
 814         switch (width_id) {
 815         case LPDDR2_IO_WIDTH_8:
 816                 return "x8";
 817         case LPDDR2_IO_WIDTH_16:
 818                 return "x16";
 819         case LPDDR2_IO_WIDTH_32:
 820                 return "x32";
 821         default:
 822                 return NULL;
 823         }
 824 }
 825
 826 const char *get_lpddr2_manufacturer(u32 manufacturer)
 827 {
 828         switch (manufacturer) {
 829         case LPDDR2_MANUFACTURER_SAMSUNG:
 830                 return "Samsung";
 831         case LPDDR2_MANUFACTURER_QIMONDA:
 832                 return "Qimonda";
 833         case LPDDR2_MANUFACTURER_ELPIDA:
 834                 return "Elpida";
 835         case LPDDR2_MANUFACTURER_ETRON:
 836                 return "Etron";
 837         case LPDDR2_MANUFACTURER_NANYA:
 838                 return "Nanya";
 839         case LPDDR2_MANUFACTURER_HYNIX:
 840                 return "Hynix";
 841         case LPDDR2_MANUFACTURER_MOSEL:
 842                 return "Mosel";
 843         case LPDDR2_MANUFACTURER_WINBOND:
 844                 return "Winbond";
 845         case LPDDR2_MANUFACTURER_ESMT:
 846                 return "ESMT";
 847         case LPDDR2_MANUFACTURER_SPANSION:
 848                 return "Spansion";
 849         case LPDDR2_MANUFACTURER_SST:
 850                 return "SST";
 851         case LPDDR2_MANUFACTURER_ZMOS:
 852                 return "ZMOS";
 853         case LPDDR2_MANUFACTURER_INTEL:
 854                 return "Intel";
 855         case LPDDR2_MANUFACTURER_NUMONYX:
 856                 return "Numonyx";
 857         case LPDDR2_MANUFACTURER_MICRON:
 858                 return "Micron";
 859         default:
 860                 return NULL;
 861         }
 862 }
 863
 864 static void display_sdram_details(u32 emif_nr, u32 cs,
 865                                   struct lpddr2_device_details *device)
 866 {
 867         const char *mfg_str;
 868         const char *type_str;
 869         char density_str[10];
 870         u32 density;
 871
 872         debug("EMIF%d CS%d\t", emif_nr, cs);
 873
 874         if (!device) {
 875                 debug("None\n");
 876                 return;
 877         }
 878
 879         mfg_str = get_lpddr2_manufacturer(device->manufacturer);
 880         type_str = get_lpddr2_type(device->type);
 881
 882         density = lpddr2_density_2_size_in_mbytes[device->density];
 883         if ((density / 1024 * 1024) == density) {
 884                 density /= 1024;
 885                 sprintf(density_str, "%d GB", density);
 886         } else
 887                 sprintf(density_str, "%d MB", density);
 888         if (mfg_str && type_str)
 889                 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
 890 }
 891
 892 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
 893                                   struct lpddr2_device_details *lpddr2_device)
 894 {
 895         u32 mr = 0, temp;
 896
 897         mr = get_mr(base, cs, LPDDR2_MR0);
 898         if (mr > 0xFF) {
 899                 /* Mode register value bigger than 8 bit */
 900                 return 0;
 901         }
 902
 903         temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
 904         if (temp) {
 905                 /* Not SDRAM */
 906                 return 0;
 907         }
 908         temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
 909
 910         if (temp) {
 911                 /* DNV supported - But DNV is only supported for NVM */
 912                 return 0;
 913         }
 914
 915         mr = get_mr(base, cs, LPDDR2_MR4);
 916         if (mr > 0xFF) {
 917                 /* Mode register value bigger than 8 bit */
 918                 return 0;
 919         }
 920
 921         mr = get_mr(base, cs, LPDDR2_MR5);
 922         if (mr > 0xFF) {
 923                 /* Mode register value bigger than 8 bit */
 924                 return 0;
 925         }
 926
 927         if (!get_lpddr2_manufacturer(mr)) {
 928                 /* Manufacturer not identified */
 929                 return 0;
 930         }
 931         lpddr2_device->manufacturer = mr;
 932
 933         mr = get_mr(base, cs, LPDDR2_MR6);
 934         if (mr >= 0xFF) {
 935                 /* Mode register value bigger than 8 bit */
 936                 return 0;
 937         }
 938
 939         mr = get_mr(base, cs, LPDDR2_MR7);
 940         if (mr >= 0xFF) {
 941                 /* Mode register value bigger than 8 bit */
 942                 return 0;
 943         }
 944
 945         mr = get_mr(base, cs, LPDDR2_MR8);
 946         if (mr >= 0xFF) {
 947                 /* Mode register value bigger than 8 bit */
 948                 return 0;
 949         }
 950
 951         temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
 952         if (!get_lpddr2_type(temp)) {
 953                 /* Not SDRAM */
 954                 return 0;
 955         }
 956         lpddr2_device->type = temp;
 957
 958         temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
 959         if (temp > LPDDR2_DENSITY_32Gb) {
 960                 /* Density not supported */
 961                 return 0;
 962         }
 963         lpddr2_device->density = temp;
 964
 965         temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
 966         if (!get_lpddr2_io_width(temp)) {
 967                 /* IO width unsupported value */
 968                 return 0;
 969         }
 970         lpddr2_device->io_width = temp;
 971
 972         /*
 973          * If all the above tests pass we should
 974          * have a device on this chip-select
 975          */
 976         return 1;
 977 }
 978
 979 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 980                         struct lpddr2_device_details *lpddr2_dev_details)
 981 {
 982         u32 phy;
 983         u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
 984
 985         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 986
 987         if (!lpddr2_dev_details)
 988                 return NULL;
 989
 990         /* Do the minimum init for mode register accesses */
 991         if (!(running_from_sdram() || warm_reset())) {
 992                 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
 993                 writel(phy, &emif->emif_ddr_phy_ctrl_1);
 994         }
 995
 996         if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
 997                 return NULL;
 998
 999         display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1000
1001         return lpddr2_dev_details;
1002 }
1003 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1004
1005 static void do_sdram_init(u32 base)
1006 {
1007         const struct emif_regs *regs;
1008         u32 in_sdram, emif_nr;
1009
1010         debug(">>do_sdram_init() %x\n", base);
1011
1012         in_sdram = running_from_sdram();
1013         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1014
1015 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1016         emif_get_reg_dump(emif_nr, &regs);
1017         if (!regs) {
1018                 debug("EMIF: reg dump not provided\n");
1019                 return;
1020         }
1021 #else
1022         /*
1023          * The user has not provided the register values. We need to
1024          * calculate it based on the timings and the DDR frequency
1025          */
1026         struct emif_device_details dev_details;
1027         struct emif_regs calculated_regs;
1028
1029         /*
1030          * Get device details:
1031          * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1032          * - Obtained from user otherwise
1033          */
1034         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1035         emif_reset_phy(base);
1036         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1037                                                 &cs0_dev_details);
1038         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1039                                                 &cs1_dev_details);
1040         emif_reset_phy(base);
1041
1042         /* Return if no devices on this EMIF */
1043         if (!dev_details.cs0_device_details &&
1044             !dev_details.cs1_device_details) {
1045                 return;
1046         }
1047
1048         /*
1049          * Get device timings:
1050          * - Default timings specified by JESD209-2 if
1051          *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1052          * - Obtained from user otherwise
1053          */
1054         emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1055                                 &dev_details.cs1_device_timings);
1056
1057         /* Calculate the register values */
1058         emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1059         regs = &calculated_regs;
1060 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1061
1062         /*
1063          * Initializing the LPDDR2 device can not happen from SDRAM.
1064          * Changing the timing registers in EMIF can happen(going from one
1065          * OPP to another)
1066          */
1067         if (!(in_sdram || warm_reset())) {
1068                 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
1069                         lpddr2_init(base, regs);
1070                 else
1071                         ddr3_init(base, regs);
1072         }
1073         if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1074                 set_lpmode_selfrefresh(base);
1075                 emif_reset_phy(base);
1076                 ddr3_leveling(base, regs);
1077         }
1078
1079         /* Write to the shadow registers */
1080         emif_update_timings(base, regs);
1081
1082         debug("<<do_sdram_init() %x\n", base);
1083 }
1084
1085 void emif_post_init_config(u32 base)
1086 {
1087         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1088         u32 omap_rev = omap_revision();
1089
1090         /* reset phy on ES2.0 */
1091         if (omap_rev == OMAP4430_ES2_0)
1092                 emif_reset_phy(base);
1093
1094         /* Put EMIF back in smart idle on ES1.0 */
1095         if (omap_rev == OMAP4430_ES1_0)
1096                 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1097 }
1098
1099 void dmm_init(u32 base)
1100 {
1101         const struct dmm_lisa_map_regs *lisa_map_regs;
1102         u32 i, section, valid;
1103
1104 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1105         emif_get_dmm_regs(&lisa_map_regs);
1106 #else
1107         u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1108         u32 section_cnt, sys_addr;
1109         struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1110
1111         mapped_size = 0;
1112         section_cnt = 3;
1113         sys_addr = CONFIG_SYS_SDRAM_BASE;
1114         emif1_size = get_emif_mem_size(EMIF1_BASE);
1115         emif2_size = get_emif_mem_size(EMIF2_BASE);
1116         debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1117
1118         if (!emif1_size && !emif2_size)
1119                 return;
1120
1121         /* symmetric interleaved section */
1122         if (emif1_size && emif2_size) {
1123                 mapped_size = min(emif1_size, emif2_size);
1124                 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1125                 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1126                 /* only MSB */
1127                 section_map |= (sys_addr >> 24) <<
1128                                 EMIF_SYS_ADDR_SHIFT;
1129                 section_map |= get_dmm_section_size_map(mapped_size * 2)
1130                                 << EMIF_SYS_SIZE_SHIFT;
1131                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1132                 emif1_size -= mapped_size;
1133                 emif2_size -= mapped_size;
1134                 sys_addr += (mapped_size * 2);
1135                 section_cnt--;
1136         }
1137
1138         /*
1139          * Single EMIF section(we can have a maximum of 1 single EMIF
1140          * section- either EMIF1 or EMIF2 or none, but not both)
1141          */
1142         if (emif1_size) {
1143                 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1144                 section_map |= get_dmm_section_size_map(emif1_size)
1145                                 << EMIF_SYS_SIZE_SHIFT;
1146                 /* only MSB */
1147                 section_map |= (mapped_size >> 24) <<
1148                                 EMIF_SDRC_ADDR_SHIFT;
1149                 /* only MSB */
1150                 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1151                 section_cnt--;
1152         }
1153         if (emif2_size) {
1154                 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1155                 section_map |= get_dmm_section_size_map(emif2_size) <<
1156                                 EMIF_SYS_SIZE_SHIFT;
1157                 /* only MSB */
1158                 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1159                 /* only MSB */
1160                 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1161                 section_cnt--;
1162         }
1163
1164         if (section_cnt == 2) {
1165                 /* Only 1 section - either symmetric or single EMIF */
1166                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1167                 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1168                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1169         } else {
1170                 /* 2 sections - 1 symmetric, 1 single EMIF */
1171                 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1172                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1173         }
1174
1175         /* TRAP for invalid TILER mappings in section 0 */
1176         lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1177
1178         if (omap_revision() >= OMAP4460_ES1_0)
1179                 lis_map_regs_calculated.is_ma_present = 1;
1180
1181         lisa_map_regs = &lis_map_regs_calculated;
1182 #endif
1183         struct dmm_lisa_map_regs *hw_lisa_map_regs =
1184             (struct dmm_lisa_map_regs *)base;
1185
1186         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1187         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1188         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1189         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1190
1191         writel(lisa_map_regs->dmm_lisa_map_3,
1192                 &hw_lisa_map_regs->dmm_lisa_map_3);
1193         writel(lisa_map_regs->dmm_lisa_map_2,
1194                 &hw_lisa_map_regs->dmm_lisa_map_2);
1195         writel(lisa_map_regs->dmm_lisa_map_1,
1196                 &hw_lisa_map_regs->dmm_lisa_map_1);
1197         writel(lisa_map_regs->dmm_lisa_map_0,
1198                 &hw_lisa_map_regs->dmm_lisa_map_0);
1199
1200         if (lisa_map_regs->is_ma_present) {
1201                 hw_lisa_map_regs =
1202                     (struct dmm_lisa_map_regs *)MA_BASE;
1203
1204                 writel(lisa_map_regs->dmm_lisa_map_3,
1205                         &hw_lisa_map_regs->dmm_lisa_map_3);
1206                 writel(lisa_map_regs->dmm_lisa_map_2,
1207                         &hw_lisa_map_regs->dmm_lisa_map_2);
1208                 writel(lisa_map_regs->dmm_lisa_map_1,
1209                         &hw_lisa_map_regs->dmm_lisa_map_1);
1210                 writel(lisa_map_regs->dmm_lisa_map_0,
1211                         &hw_lisa_map_regs->dmm_lisa_map_0);
1212         }
1213
1214         /*
1215          * EMIF should be configured only when
1216          * memory is mapped on it. Using emif1_enabled
1217          * and emif2_enabled variables for this.
1218          */
1219         emif1_enabled = 0;
1220         emif2_enabled = 0;
1221         for (i = 0; i < 4; i++) {
1222                 section = __raw_readl(DMM_BASE + i*4);
1223                 valid = (section & EMIF_SDRC_MAP_MASK) >>
1224                         (EMIF_SDRC_MAP_SHIFT);
1225                 if (valid == 3) {
1226                         emif1_enabled = 1;
1227                         emif2_enabled = 1;
1228                         break;
1229                 } else if (valid == 1) {
1230                         emif1_enabled = 1;
1231                 } else if (valid == 2) {
1232                         emif2_enabled = 1;
1233                 }
1234         }
1235
1236 }
1237
1238 static void do_bug0039_workaround(u32 base)
1239 {
1240         u32 val, i, clkctrl;
1241         struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1242         const struct read_write_regs *bug_00339_regs;
1243         u32 iterations;
1244         u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1245         u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1246
1247         if (is_dra7xx())
1248                 phy_status_base++;
1249
1250         bug_00339_regs = get_bug_regs(&iterations);
1251
1252         /* Put EMIF in to idle */
1253         clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1254         __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1255
1256         /* Copy the phy status registers in to phy ctrl shadow registers */
1257         for (i = 0; i < iterations; i++) {
1258                 val = __raw_readl(phy_status_base +
1259                                   bug_00339_regs[i].read_reg - 1);
1260
1261                 __raw_writel(val, phy_ctrl_base +
1262                              ((bug_00339_regs[i].write_reg - 1) << 1));
1263
1264                 __raw_writel(val, phy_ctrl_base +
1265                              (bug_00339_regs[i].write_reg << 1) - 1);
1266         }
1267
1268         /* Disable leveling */
1269         writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1270
1271         __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
1272 }
1273
1274 /*
1275  * SDRAM initialization:
1276  * SDRAM initialization has two parts:
1277  * 1. Configuring the SDRAM device
1278  * 2. Update the AC timings related parameters in the EMIF module
1279  * (1) should be done only once and should not be done while we are
1280  * running from SDRAM.
1281  * (2) can and should be done more than once if OPP changes.
1282  * Particularly, this may be needed when we boot without SPL and
1283  * and using Configuration Header(CH). ROM code supports only at 50% OPP
1284  * at boot (low power boot). So u-boot has to switch to OPP100 and update
1285  * the frequency. So,
1286  * Doing (1) and (2) makes sense - first time initialization
1287  * Doing (2) and not (1) makes sense - OPP change (when using CH)
1288  * Doing (1) and not (2) doen't make sense
1289  * See do_sdram_init() for the details
1290  */
1291 void sdram_init(void)
1292 {
1293         u32 in_sdram, size_prog, size_detect;
1294         u32 sdram_type = emif_sdram_type();
1295
1296         debug(">>sdram_init()\n");
1297
1298         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1299                 return;
1300
1301         in_sdram = running_from_sdram();
1302         debug("in_sdram = %d\n", in_sdram);
1303
1304         if (!in_sdram) {
1305                 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1306                         bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1307                 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1308                         writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1309         }
1310
1311         if (!in_sdram)
1312                 dmm_init(DMM_BASE);
1313
1314         if (emif1_enabled)
1315                 do_sdram_init(EMIF1_BASE);
1316
1317         if (emif2_enabled)
1318                 do_sdram_init(EMIF2_BASE);
1319
1320         if (!(in_sdram || warm_reset())) {
1321                 if (emif1_enabled)
1322                         emif_post_init_config(EMIF1_BASE);
1323                 if (emif2_enabled)
1324                         emif_post_init_config(EMIF2_BASE);
1325         }
1326
1327         /* for the shadow registers to take effect */
1328         if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1329                 freq_update_core();
1330
1331         /* Do some testing after the init */
1332         if (!in_sdram) {
1333                 size_prog = omap_sdram_size();
1334                 size_prog = log_2_n_round_down(size_prog);
1335                 size_prog = (1 << size_prog);
1336
1337                 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1338                                                 size_prog);
1339                 /* Compare with the size programmed */
1340                 if (size_detect != size_prog) {
1341                         printf("SDRAM: identified size not same as expected"
1342                                 " size identified: %x expected: %x\n",
1343                                 size_detect,
1344                                 size_prog);
1345                 } else
1346                         debug("get_ram_size() successful");
1347         }
1348
1349         if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1350             (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
1351                 if (emif1_enabled)
1352                         do_bug0039_workaround(EMIF1_BASE);
1353                 if (emif2_enabled)
1354                         do_bug0039_workaround(EMIF2_BASE);
1355         }
1356
1357         debug("<<sdram_init()\n");
1358 }