arch/arm/cpu/armv7/omap-common/hwinit-common.c

   1 /*
   2  *
   3  * Common functions for OMAP4/5 based boards
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14 #include <common.h>
  15 #include <spl.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <linux/sizes.h>
  18 #include <asm/emif.h>
  19 #include <asm/omap_common.h>
  20 #include <linux/compiler.h>
  21 #include <asm/system.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
  26 {
  27         int i;
  28         struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
  29
  30         for (i = 0; i < size; i++, pad++)
  31                 writew(pad->val, base + pad->offset);
  32 }
  33
  34 static void set_mux_conf_regs(void)
  35 {
  36         switch (omap_hw_init_context()) {
  37         case OMAP_INIT_CONTEXT_SPL:
  38                 set_muxconf_regs_essential();
  39                 break;
  40         case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
  41                 break;
  42         case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  43         case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  44                 set_muxconf_regs_essential();
  45                 break;
  46         }
  47 }
  48
  49 u32 cortex_rev(void)
  50 {
  51
  52         unsigned int rev;
  53
  54         /* Read Main ID Register (MIDR) */
  55         asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
  56
  57         return rev;
  58 }
  59
  60 static void omap_rev_string(void)
  61 {
  62         u32 omap_rev = omap_revision();
  63         u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
  64         u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
  65         u32 major_rev = (omap_rev & 0x00000F00) >> 8;
  66         u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
  67
  68         if (soc_variant)
  69                 printf("OMAP");
  70         else
  71                 printf("DRA");
  72         printf("%x ES%x.%x\n", omap_variant, major_rev,
  73                minor_rev);
  74 }
  75
  76 #ifdef CONFIG_SPL_BUILD
  77 void spl_display_print(void)
  78 {
  79         omap_rev_string();
  80 }
  81 #endif
  82
  83 void __weak srcomp_enable(void)
  84 {
  85 }
  86
  87 #ifdef CONFIG_ARCH_CPU_INIT
  88 /*
  89  * SOC specific cpu init
  90  */
  91 int arch_cpu_init(void)
  92 {
  93 #ifdef CONFIG_SPL
  94         save_omap_boot_params();
  95 #endif
  96         return 0;
  97 }
  98 #endif /* CONFIG_ARCH_CPU_INIT */
  99
 100 /*
 101  * Routine: s_init
 102  * Description: Does early system init of watchdog, muxing,  andclocks
 103  * Watchdog disable is done always. For the rest what gets done
 104  * depends on the boot mode in which this function is executed
 105  *   1. s_init of SPL running from SRAM
 106  *   2. s_init of U-Boot running from FLASH
 107  *   3. s_init of U-Boot loaded to SDRAM by SPL
 108  *   4. s_init of U-Boot loaded to SDRAM by ROM code using the
 109  *      Configuration Header feature
 110  * Please have a look at the respective functions to see what gets
 111  * done in each of these cases
 112  * This function is called with SRAM stack.
 113  */
 114 void s_init(void)
 115 {
 116         init_omap_revision();
 117         hw_data_init();
 118
 119 #ifdef CONFIG_SPL_BUILD
 120         if (warm_reset() &&
 121             (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
 122                 force_emif_self_refresh();
 123 #endif
 124         watchdog_init();
 125         set_mux_conf_regs();
 126 #ifdef CONFIG_SPL_BUILD
 127         srcomp_enable();
 128         setup_clocks_for_console();
 129
 130         do_io_settings();
 131 #endif
 132         prcm_init();
 133 }
 134
 135 #ifdef CONFIG_SPL_BUILD
 136 void board_init_f(ulong dummy)
 137 {
 138 #ifdef CONFIG_BOARD_EARLY_INIT_F
 139         board_early_init_f();
 140 #endif
 141         /* For regular u-boot sdram_init() is called from dram_init() */
 142         sdram_init();
 143 }
 144 #endif
 145
 146 /*
 147  * Routine: wait_for_command_complete
 148  * Description: Wait for posting to finish on watchdog
 149  */
 150 void wait_for_command_complete(struct watchdog *wd_base)
 151 {
 152         int pending = 1;
 153         do {
 154                 pending = readl(&wd_base->wwps);
 155         } while (pending);
 156 }
 157
 158 /*
 159  * Routine: watchdog_init
 160  * Description: Shut down watch dogs
 161  */
 162 void watchdog_init(void)
 163 {
 164         struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
 165
 166         writel(WD_UNLOCK1, &wd2_base->wspr);
 167         wait_for_command_complete(wd2_base);
 168         writel(WD_UNLOCK2, &wd2_base->wspr);
 169 }
 170
 171
 172 /*
 173  * This function finds the SDRAM size available in the system
 174  * based on DMM section configurations
 175  * This is needed because the size of memory installed may be
 176  * different on different versions of the board
 177  */
 178 u32 omap_sdram_size(void)
 179 {
 180         u32 section, i, valid;
 181         u64 sdram_start = 0, sdram_end = 0, addr,
 182             size, total_size = 0, trap_size = 0, trap_start = 0;
 183
 184         for (i = 0; i < 4; i++) {
 185                 section = __raw_readl(DMM_BASE + i*4);
 186                 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
 187                         (EMIF_SDRC_ADDRSPC_SHIFT);
 188                 addr = section & EMIF_SYS_ADDR_MASK;
 189
 190                 /* See if the address is valid */
 191                 if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
 192                     (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
 193                         size = ((section & EMIF_SYS_SIZE_MASK) >>
 194                                    EMIF_SYS_SIZE_SHIFT);
 195                         size = 1 << size;
 196                         size *= SZ_16M;
 197
 198                         if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
 199                                 if (!sdram_start || (addr < sdram_start))
 200                                         sdram_start = addr;
 201                                 if (!sdram_end || ((addr + size) > sdram_end))
 202                                         sdram_end = addr + size;
 203                         } else {
 204                                 trap_size = size;
 205                                 trap_start = addr;
 206                         }
 207                 }
 208         }
 209
 210         if ((trap_start >= sdram_start) && (trap_start < sdram_end))
 211                 total_size = (sdram_end - sdram_start) - (trap_size);
 212         else
 213                 total_size = sdram_end - sdram_start;
 214
 215         return total_size;
 216 }
 217
 218
 219 /*
 220  * Routine: dram_init
 221  * Description: sets uboots idea of sdram size
 222  */
 223 int dram_init(void)
 224 {
 225         sdram_init();
 226         gd->ram_size = omap_sdram_size();
 227         return 0;
 228 }
 229
 230 /*
 231  * Print board information
 232  */
 233 int checkboard(void)
 234 {
 235         puts(sysinfo.board_string);
 236         return 0;
 237 }
 238
 239 /*
 240  *  get_device_type(): tell if GP/HS/EMU/TST
 241  */
 242 u32 get_device_type(void)
 243 {
 244         return (readl((*ctrl)->control_status) &
 245                                       (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
 246 }
 247
 248 #if defined(CONFIG_DISPLAY_CPUINFO)
 249 /*
 250  * Print CPU information
 251  */
 252 int print_cpuinfo(void)
 253 {
 254         puts("CPU  : ");
 255         omap_rev_string();
 256
 257         return 0;
 258 }
 259 #endif