arch/arm/cpu/armv7/omap3/sys_info.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *      Manikandan Pillai <mani.pillai@ti.com>
   7  *
   8  * Derived from Beagle Board and 3430 SDP code by
   9  *      Richard Woodruff <r-woodruff2@ti.com>
  10  *      Syed Mohammed Khasim <khasim@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/mem.h>       /* get mem tables */
  31 #include <asm/arch/sys_proto.h>
  32 #include <i2c.h>
  33 #include <linux/compiler.h>
  34
  35 extern omap3_sysinfo sysinfo;
  36 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  37
  38 #ifdef CONFIG_DISPLAY_CPUINFO
  39 static char *rev_s[CPU_3XX_MAX_REV] = {
  40                                 "1.0",
  41                                 "2.0",
  42                                 "2.1",
  43                                 "3.0",
  44                                 "3.1",
  45                                 "UNKNOWN",
  46                                 "UNKNOWN",
  47                                 "3.1.2"};
  48
  49 /* this is the revision table for 37xx CPUs */
  50 static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
  51                                 "1.0",
  52                                 "1.1",
  53                                 "1.2"};
  54 #endif /* CONFIG_DISPLAY_CPUINFO */
  55
  56 /*****************************************************************
  57  * dieid_num_r(void) - read and set die ID
  58  *****************************************************************/
  59 void dieid_num_r(void)
  60 {
  61         struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
  62         char *uid_s, die_id[34];
  63         u32 id[4];
  64
  65         memset(die_id, 0, sizeof(die_id));
  66
  67         uid_s = getenv("dieid#");
  68
  69         if (uid_s == NULL) {
  70                 id[3] = readl(&id_base->die_id_0);
  71                 id[2] = readl(&id_base->die_id_1);
  72                 id[1] = readl(&id_base->die_id_2);
  73                 id[0] = readl(&id_base->die_id_3);
  74                 sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
  75                 setenv("dieid#", die_id);
  76                 uid_s = die_id;
  77         }
  78
  79         printf("Die ID #%s\n", uid_s);
  80 }
  81
  82 /******************************************
  83  * get_cpu_type(void) - extract cpu info
  84  ******************************************/
  85 u32 get_cpu_type(void)
  86 {
  87         return readl(&ctrl_base->ctrl_omap_stat);
  88 }
  89
  90 /******************************************
  91  * get_cpu_id(void) - extract cpu id
  92  * returns 0 for ES1.0, cpuid otherwise
  93  ******************************************/
  94 u32 get_cpu_id(void)
  95 {
  96         struct ctrl_id *id_base;
  97         u32 cpuid = 0;
  98
  99         /*
 100          * On ES1.0 the IDCODE register is not exposed on L4
 101          * so using CPU ID to differentiate between ES1.0 and > ES1.0.
 102          */
 103         __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
 104         if ((cpuid & 0xf) == 0x0) {
 105                 return 0;
 106         } else {
 107                 /* Decode the IDs on > ES1.0 */
 108                 id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
 109
 110                 cpuid = readl(&id_base->idcode);
 111         }
 112
 113         return cpuid;
 114 }
 115
 116 /******************************************
 117  * get_cpu_family(void) - extract cpu info
 118  ******************************************/
 119 u32 get_cpu_family(void)
 120 {
 121         u16 hawkeye;
 122         u32 cpu_family;
 123         u32 cpuid = get_cpu_id();
 124
 125         if (cpuid == 0)
 126                 return CPU_OMAP34XX;
 127
 128         hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
 129         switch (hawkeye) {
 130         case HAWKEYE_OMAP34XX:
 131                 cpu_family = CPU_OMAP34XX;
 132                 break;
 133         case HAWKEYE_AM35XX:
 134                 cpu_family = CPU_AM35XX;
 135                 break;
 136         case HAWKEYE_OMAP36XX:
 137                 cpu_family = CPU_OMAP36XX;
 138                 break;
 139         default:
 140                 cpu_family = CPU_OMAP34XX;
 141         }
 142
 143         return cpu_family;
 144 }
 145
 146 /******************************************
 147  * get_cpu_rev(void) - extract version info
 148  ******************************************/
 149 u32 get_cpu_rev(void)
 150 {
 151         u32 cpuid = get_cpu_id();
 152
 153         if (cpuid == 0)
 154                 return CPU_3XX_ES10;
 155         else
 156                 return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
 157 }
 158
 159 /*****************************************************************
 160  * get_sku_id(void) - read sku_id to get info on max clock rate
 161  *****************************************************************/
 162 u32 get_sku_id(void)
 163 {
 164         struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
 165         return readl(&id_base->sku_id) & SKUID_CLK_MASK;
 166 }
 167
 168 /***************************************************************************
 169  *  get_gpmc0_base() - Return current address hardware will be
 170  *     fetching from. The below effectively gives what is correct, its a bit
 171  *   mis-leading compared to the TRM.  For the most general case the mask
 172  *   needs to be also taken into account this does work in practice.
 173  *   - for u-boot we currently map:
 174  *       -- 0 to nothing,
 175  *       -- 4 to flash
 176  *       -- 8 to enent
 177  *       -- c to wifi
 178  ****************************************************************************/
 179 u32 get_gpmc0_base(void)
 180 {
 181         u32 b;
 182
 183         b = readl(&gpmc_cfg->cs[0].config7);
 184         b &= 0x1F;              /* keep base [5:0] */
 185         b = b << 24;            /* ret 0x0b000000 */
 186         return b;
 187 }
 188
 189 /*******************************************************************
 190  * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
 191  *******************************************************************/
 192 u32 get_gpmc0_width(void)
 193 {
 194         return WIDTH_16BIT;
 195 }
 196
 197 /*************************************************************************
 198  * get_board_rev() - setup to pass kernel board revision information
 199  * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
 200  *************************************************************************/
 201 u32 __weak get_board_rev(void)
 202 {
 203         return 0x20;
 204 }
 205
 206 /********************************************************
 207  *  get_base(); get upper addr of current execution
 208  *******************************************************/
 209 u32 get_base(void)
 210 {
 211         u32 val;
 212
 213         __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
 214         val &= 0xF0000000;
 215         val >>= 28;
 216         return val;
 217 }
 218
 219 /********************************************************
 220  *  is_running_in_flash() - tell if currently running in
 221  *  FLASH.
 222  *******************************************************/
 223 u32 is_running_in_flash(void)
 224 {
 225         if (get_base() < 4)
 226                 return 1;       /* in FLASH */
 227
 228         return 0;               /* running in SRAM or SDRAM */
 229 }
 230
 231 /********************************************************
 232  *  is_running_in_sram() - tell if currently running in
 233  *  SRAM.
 234  *******************************************************/
 235 u32 is_running_in_sram(void)
 236 {
 237         if (get_base() == 4)
 238                 return 1;       /* in SRAM */
 239
 240         return 0;               /* running in FLASH or SDRAM */
 241 }
 242
 243 /********************************************************
 244  *  is_running_in_sdram() - tell if currently running in
 245  *  SDRAM.
 246  *******************************************************/
 247 u32 is_running_in_sdram(void)
 248 {
 249         if (get_base() > 4)
 250                 return 1;       /* in SDRAM */
 251
 252         return 0;               /* running in SRAM or FLASH */
 253 }
 254
 255 /***************************************************************
 256  *  get_boot_type() - Is this an XIP type device or a stream one
 257  *  bits 4-0 specify type. Bit 5 says mem/perif
 258  ***************************************************************/
 259 u32 get_boot_type(void)
 260 {
 261         return (readl(&ctrl_base->status) & SYSBOOT_MASK);
 262 }
 263
 264 /*************************************************************
 265  *  get_device_type(): tell if GP/HS/EMU/TST
 266  *************************************************************/
 267 u32 get_device_type(void)
 268 {
 269         return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
 270 }
 271
 272 #ifdef CONFIG_DISPLAY_CPUINFO
 273 /**
 274  * Print CPU information
 275  */
 276 int print_cpuinfo (void)
 277 {
 278         char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
 279
 280         switch (get_cpu_family()) {
 281         case CPU_OMAP34XX:
 282                 cpu_family_s = "OMAP";
 283                 switch (get_cpu_type()) {
 284                 case OMAP3503:
 285                         cpu_s = "3503";
 286                         break;
 287                 case OMAP3515:
 288                         cpu_s = "3515";
 289                         break;
 290                 case OMAP3525:
 291                         cpu_s = "3525";
 292                         break;
 293                 case OMAP3530:
 294                         cpu_s = "3530";
 295                         break;
 296                 default:
 297                         cpu_s = "35XX";
 298                         break;
 299                 }
 300                 if ((get_cpu_rev() >= CPU_3XX_ES31) &&
 301                     (get_sku_id() == SKUID_CLK_720MHZ))
 302                         max_clk = "720 MHz";
 303                 else
 304                         max_clk = "600 MHz";
 305
 306                 break;
 307         case CPU_AM35XX:
 308                 cpu_family_s = "AM";
 309                 switch (get_cpu_type()) {
 310                 case AM3505:
 311                         cpu_s = "3505";
 312                         break;
 313                 case AM3517:
 314                         cpu_s = "3517";
 315                         break;
 316                 default:
 317                         cpu_s = "35XX";
 318                         break;
 319                 }
 320                 max_clk = "600 Mhz";
 321                 break;
 322         case CPU_OMAP36XX:
 323                 cpu_family_s = "OMAP";
 324                 switch (get_cpu_type()) {
 325                 case OMAP3730:
 326                         cpu_s = "3630/3730";
 327                         break;
 328                 default:
 329                         cpu_s = "36XX/37XX";
 330                         break;
 331                 }
 332                 max_clk = "1 Ghz";
 333                 break;
 334         default:
 335                 cpu_family_s = "OMAP";
 336                 cpu_s = "35XX";
 337                 max_clk = "600 Mhz";
 338         }
 339
 340         switch (get_device_type()) {
 341         case TST_DEVICE:
 342                 sec_s = "TST";
 343                 break;
 344         case EMU_DEVICE:
 345                 sec_s = "EMU";
 346                 break;
 347         case HS_DEVICE:
 348                 sec_s = "HS";
 349                 break;
 350         case GP_DEVICE:
 351                 sec_s = "GP";
 352                 break;
 353         default:
 354                 sec_s = "?";
 355         }
 356
 357         if (CPU_OMAP36XX == get_cpu_family())
 358                 printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
 359                         cpu_family_s, cpu_s, sec_s,
 360                         rev_s_37xx[get_cpu_rev()], max_clk);
 361         else
 362                 printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
 363                         cpu_family_s, cpu_s, sec_s,
 364                         rev_s[get_cpu_rev()], max_clk);
 365
 366         return 0;
 367 }
 368 #endif  /* CONFIG_DISPLAY_CPUINFO */