arch/arm/cpu/armv7/omap5/hwinit.c

   1 /*
   2  *
   3  * Functions for omap5 based boards.
   4  *
   5  * (C) Copyright 2011
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *      Sricharan       <r.sricharan@ti.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31 #include <common.h>
  32 #include <asm/armv7.h>
  33 #include <asm/arch/cpu.h>
  34 #include <asm/arch/sys_proto.h>
  35 #include <asm/arch/clocks.h>
  36 #include <asm/sizes.h>
  37 #include <asm/utils.h>
  38 #include <asm/arch/gpio.h>
  39 #include <asm/emif.h>
  40 #include <asm/omap_common.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  45
  46 static struct gpio_bank gpio_bank_54xx[6] = {
  47         { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
  48         { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
  49         { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
  50         { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
  51         { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
  52         { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
  53 };
  54
  55 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  56
  57 #ifdef CONFIG_SPL_BUILD
  58 /* LPDDR2 specific IO settings */
  59 static void io_settings_lpddr2(void)
  60 {
  61         const struct ctrl_ioregs *ioregs;
  62
  63         get_ioregs(&ioregs);
  64         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  65         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  66         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  67         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  68         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  69         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  70         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  71         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  72         writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  73 }
  74
  75 /* DDR3 specific IO settings */
  76 static void io_settings_ddr3(void)
  77 {
  78         u32 io_settings = 0;
  79         const struct ctrl_ioregs *ioregs;
  80
  81         get_ioregs(&ioregs);
  82         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  83         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  84         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  85
  86         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  87         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  88         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  89
  90         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  91         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  92         writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  93
  94         /* omap5432 does not use lpddr2 */
  95         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  96         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  97
  98         writel(ioregs->ctrl_emif_sdram_config_ext,
  99                (*ctrl)->control_emif1_sdram_config_ext);
 100         writel(ioregs->ctrl_emif_sdram_config_ext,
 101                (*ctrl)->control_emif2_sdram_config_ext);
 102
 103         /* Disable DLL select */
 104         io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
 105                                                         & 0xFFEFFFFF);
 106         writel(io_settings,
 107                 (*ctrl)->control_port_emif1_sdram_config);
 108
 109         io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
 110                                                         & 0xFFEFFFFF);
 111         writel(io_settings,
 112                 (*ctrl)->control_port_emif2_sdram_config);
 113 }
 114
 115 /*
 116  * Some tuning of IOs for optimal power and performance
 117  */
 118 void do_io_settings(void)
 119 {
 120         u32 io_settings = 0, mask = 0;
 121
 122         /* Impedance settings EMMC, C2C 1,2, hsi2 */
 123         mask = (ds_mask << 2) | (ds_mask << 8) |
 124                 (ds_mask << 16) | (ds_mask << 18);
 125         io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
 126                                 (~mask);
 127         io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 128                         (ds_45_ohm << 18) | (ds_60_ohm << 2);
 129         writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
 130
 131         /* Impedance settings Mcspi2 */
 132         mask = (ds_mask << 30);
 133         io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
 134                         (~mask);
 135         io_settings |= (ds_60_ohm << 30);
 136         writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
 137
 138         /* Impedance settings C2C 3,4 */
 139         mask = (ds_mask << 14) | (ds_mask << 16);
 140         io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
 141                         (~mask);
 142         io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 143         writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
 144
 145         /* Slew rate settings EMMC, C2C 1,2 */
 146         mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 147         io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
 148                         (~mask);
 149         io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 150         writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
 151
 152         /* Slew rate settings hsi2, Mcspi2 */
 153         mask = (sc_mask << 24) | (sc_mask << 28);
 154         io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
 155                         (~mask);
 156         io_settings |= (sc_fast << 28) | (sc_fast << 24);
 157         writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
 158
 159         /* Slew rate settings C2C 3,4 */
 160         mask = (sc_mask << 16) | (sc_mask << 18);
 161         io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
 162                         (~mask);
 163         io_settings |= (sc_na << 16) | (sc_na << 18);
 164         writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
 165
 166         /* impedance and slew rate settings for usb */
 167         mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 168                 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 169         io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
 170                         (~mask);
 171         io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 172                        (ds_60_ohm << 23) | (sc_fast << 20) |
 173                        (sc_fast << 17) | (sc_fast << 14);
 174         writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 175
 176         if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
 177                 io_settings_lpddr2();
 178         else
 179                 io_settings_ddr3();
 180
 181         /* Efuse settings */
 182         writel(EFUSE_1, (*ctrl)->control_efuse_1);
 183         writel(EFUSE_2, (*ctrl)->control_efuse_2);
 184         writel(EFUSE_3, (*ctrl)->control_efuse_3);
 185         writel(EFUSE_4, (*ctrl)->control_efuse_4);
 186 }
 187
 188 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
 189         {0x45, 0x1},    /* 12 MHz   */
 190         {-1, -1},       /* 13 MHz   */
 191         {0x63, 0x2},    /* 16.8 MHz */
 192         {0x57, 0x2},    /* 19.2 MHz */
 193         {0x20, 0x1},    /* 26 MHz   */
 194         {-1, -1},       /* 27 MHz   */
 195         {0x41, 0x3}     /* 38.4 MHz */
 196 };
 197
 198 void srcomp_enable(void)
 199 {
 200         u32 srcomp_value, mul_factor, div_factor, clk_val, i;
 201         u32 sysclk_ind  = get_sys_clk_index();
 202         u32 omap_rev    = omap_revision();
 203
 204         mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
 205         div_factor = srcomp_parameters[sysclk_ind].divide_factor;
 206
 207         for (i = 0; i < 4; i++) {
 208                 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
 209                 srcomp_value &=
 210                         ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
 211                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 212                         (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 213                 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
 214         }
 215
 216         if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
 217                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 218                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 219                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 220
 221                 for (i = 0; i < 4; i++) {
 222                         srcomp_value =
 223                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 224                         srcomp_value &= ~PWRDWN_XS_MASK;
 225                         writel(srcomp_value,
 226                                (*ctrl)->control_srcomp_north_side + i*4);
 227
 228                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 229                                 & SRCODE_READ_XS_MASK) >>
 230                                 SRCODE_READ_XS_SHIFT) == 0)
 231                                 ;
 232
 233                         srcomp_value =
 234                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 235                         srcomp_value &= ~OVERRIDE_XS_MASK;
 236                         writel(srcomp_value,
 237                                (*ctrl)->control_srcomp_north_side + i*4);
 238                 }
 239         } else {
 240                 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
 241                 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
 242                                   DIVIDE_FACTOR_XS_MASK);
 243                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 244                                 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 245                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 246
 247                 for (i = 0; i < 4; i++) {
 248                         srcomp_value =
 249                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 250                         srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 251                         writel(srcomp_value,
 252                                (*ctrl)->control_srcomp_north_side + i*4);
 253
 254                         srcomp_value =
 255                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 256                         srcomp_value &= ~OVERRIDE_XS_MASK;
 257                         writel(srcomp_value,
 258                                (*ctrl)->control_srcomp_north_side + i*4);
 259                 }
 260
 261                 srcomp_value =
 262                         readl((*ctrl)->control_srcomp_east_side_wkup);
 263                 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 264                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 265
 266                 srcomp_value =
 267                         readl((*ctrl)->control_srcomp_east_side_wkup);
 268                 srcomp_value &= ~OVERRIDE_XS_MASK;
 269                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 270
 271                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 272                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 273                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 274
 275                 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 276                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 277                 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 278
 279                 for (i = 0; i < 4; i++) {
 280                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 281                                 & SRCODE_READ_XS_MASK) >>
 282                                 SRCODE_READ_XS_SHIFT) == 0)
 283                                 ;
 284
 285                         srcomp_value =
 286                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 287                         srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 288                         writel(srcomp_value,
 289                                (*ctrl)->control_srcomp_north_side + i*4);
 290                 }
 291
 292                 while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
 293                         SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
 294                         ;
 295
 296                 srcomp_value =
 297                         readl((*ctrl)->control_srcomp_east_side_wkup);
 298                 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 299                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 300         }
 301 }
 302 #endif
 303
 304 void config_data_eye_leveling_samples(u32 emif_base)
 305 {
 306         /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 307         if (emif_base == EMIF1_BASE)
 308                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 309                         (*ctrl)->control_emif1_sdram_config_ext);
 310         else if (emif_base == EMIF2_BASE)
 311                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 312                         (*ctrl)->control_emif2_sdram_config_ext);
 313 }
 314
 315 void init_omap_revision(void)
 316 {
 317         /*
 318          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 319          * Also, ES1 and ES2 have different ARM revisions
 320          * So use ARM revision for identification
 321          */
 322         unsigned int rev = cortex_rev();
 323
 324         switch (readl(CONTROL_ID_CODE)) {
 325         case OMAP5430_CONTROL_ID_CODE_ES1_0:
 326                 *omap_si_rev = OMAP5430_ES1_0;
 327                 if (rev == MIDR_CORTEX_A15_R2P2)
 328                         *omap_si_rev = OMAP5430_ES2_0;
 329                 break;
 330         case OMAP5432_CONTROL_ID_CODE_ES1_0:
 331                 *omap_si_rev = OMAP5432_ES1_0;
 332                 if (rev == MIDR_CORTEX_A15_R2P2)
 333                         *omap_si_rev = OMAP5432_ES2_0;
 334                 break;
 335         case OMAP5430_CONTROL_ID_CODE_ES2_0:
 336                 *omap_si_rev = OMAP5430_ES2_0;
 337                 break;
 338         case OMAP5432_CONTROL_ID_CODE_ES2_0:
 339                 *omap_si_rev = OMAP5432_ES2_0;
 340                 break;
 341         case DRA752_CONTROL_ID_CODE_ES1_0:
 342                 *omap_si_rev = DRA752_ES1_0;
 343                 break;
 344         default:
 345                 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 346         }
 347 }
 348
 349 void reset_cpu(ulong ignored)
 350 {
 351         u32 omap_rev = omap_revision();
 352
 353         /*
 354          * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 355          * So use cold reset in case instead.
 356          */
 357         if (omap_rev == OMAP5430_ES1_0)
 358                 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
 359         else
 360                 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
 361 }
 362
 363 u32 warm_reset(void)
 364 {
 365         return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 366 }
 367
 368 void setup_warmreset_time(void)
 369 {
 370         u32 rst_time, rst_val;
 371
 372 #ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
 373         rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
 374 #else
 375         rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
 376 #endif
 377         rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
 378
 379         if (rst_time > RSTTIME1_MASK)
 380                 rst_time = RSTTIME1_MASK;
 381
 382         rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
 383         rst_val |= rst_time;
 384         writel(rst_val, (*prcm)->prm_rsttime);
 385 }