arch/arm/cpu/armv7/omap5/hwinit.c

   1 /*
   2  *
   3  * Functions for omap5 based boards.
   4  *
   5  * (C) Copyright 2011
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *      Sricharan       <r.sricharan@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15 #include <common.h>
  16 #include <asm/armv7.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/clock.h>
  20 #include <linux/sizes.h>
  21 #include <asm/utils.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/emif.h>
  24 #include <asm/omap_common.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  29
  30 static struct gpio_bank gpio_bank_54xx[8] = {
  31         { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
  32         { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
  33         { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
  34         { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
  35         { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
  36         { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
  37         { (void *)OMAP54XX_GPIO7_BASE, METHOD_GPIO_24XX },
  38         { (void *)OMAP54XX_GPIO8_BASE, METHOD_GPIO_24XX },
  39 };
  40
  41 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  42
  43 #ifdef CONFIG_SPL_BUILD
  44 /* LPDDR2 specific IO settings */
  45 static void io_settings_lpddr2(void)
  46 {
  47         const struct ctrl_ioregs *ioregs;
  48
  49         get_ioregs(&ioregs);
  50         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  51         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  52         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  53         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  54         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  55         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  56         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  57         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  58         writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  59 }
  60
  61 /* DDR3 specific IO settings */
  62 static void io_settings_ddr3(void)
  63 {
  64         u32 io_settings = 0;
  65         const struct ctrl_ioregs *ioregs;
  66
  67         get_ioregs(&ioregs);
  68         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  69         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  70         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  71
  72         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  73         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  74         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  75
  76         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  77         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  78
  79         if (!is_dra7xx()) {
  80                 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  81                 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  82         }
  83
  84         /* omap5432 does not use lpddr2 */
  85         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  86
  87         writel(ioregs->ctrl_emif_sdram_config_ext,
  88                (*ctrl)->control_emif1_sdram_config_ext);
  89         if (!is_dra72x())
  90                 writel(ioregs->ctrl_emif_sdram_config_ext,
  91                        (*ctrl)->control_emif2_sdram_config_ext);
  92
  93         if (is_omap54xx()) {
  94                 /* Disable DLL select */
  95                 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
  96                                                         & 0xFFEFFFFF);
  97                 writel(io_settings,
  98                         (*ctrl)->control_port_emif1_sdram_config);
  99
 100                 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
 101                                                         & 0xFFEFFFFF);
 102                 writel(io_settings,
 103                         (*ctrl)->control_port_emif2_sdram_config);
 104         } else {
 105                 writel(ioregs->ctrl_ddr_ctrl_ext_0,
 106                                 (*ctrl)->control_ddr_control_ext_0);
 107         }
 108 }
 109
 110 /*
 111  * Some tuning of IOs for optimal power and performance
 112  */
 113 void do_io_settings(void)
 114 {
 115         u32 io_settings = 0, mask = 0;
 116
 117         /* Impedance settings EMMC, C2C 1,2, hsi2 */
 118         mask = (ds_mask << 2) | (ds_mask << 8) |
 119                 (ds_mask << 16) | (ds_mask << 18);
 120         io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
 121                                 (~mask);
 122         io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 123                         (ds_45_ohm << 18) | (ds_60_ohm << 2);
 124         writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
 125
 126         /* Impedance settings Mcspi2 */
 127         mask = (ds_mask << 30);
 128         io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
 129                         (~mask);
 130         io_settings |= (ds_60_ohm << 30);
 131         writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
 132
 133         /* Impedance settings C2C 3,4 */
 134         mask = (ds_mask << 14) | (ds_mask << 16);
 135         io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
 136                         (~mask);
 137         io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 138         writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
 139
 140         /* Slew rate settings EMMC, C2C 1,2 */
 141         mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 142         io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
 143                         (~mask);
 144         io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 145         writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
 146
 147         /* Slew rate settings hsi2, Mcspi2 */
 148         mask = (sc_mask << 24) | (sc_mask << 28);
 149         io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
 150                         (~mask);
 151         io_settings |= (sc_fast << 28) | (sc_fast << 24);
 152         writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
 153
 154         /* Slew rate settings C2C 3,4 */
 155         mask = (sc_mask << 16) | (sc_mask << 18);
 156         io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
 157                         (~mask);
 158         io_settings |= (sc_na << 16) | (sc_na << 18);
 159         writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
 160
 161         /* impedance and slew rate settings for usb */
 162         mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 163                 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 164         io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
 165                         (~mask);
 166         io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 167                        (ds_60_ohm << 23) | (sc_fast << 20) |
 168                        (sc_fast << 17) | (sc_fast << 14);
 169         writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 170
 171         if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
 172                 io_settings_lpddr2();
 173         else
 174                 io_settings_ddr3();
 175 }
 176
 177 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
 178         {0x45, 0x1},    /* 12 MHz   */
 179         {-1, -1},       /* 13 MHz   */
 180         {0x63, 0x2},    /* 16.8 MHz */
 181         {0x57, 0x2},    /* 19.2 MHz */
 182         {0x20, 0x1},    /* 26 MHz   */
 183         {-1, -1},       /* 27 MHz   */
 184         {0x41, 0x3}     /* 38.4 MHz */
 185 };
 186
 187 void srcomp_enable(void)
 188 {
 189         u32 srcomp_value, mul_factor, div_factor, clk_val, i;
 190         u32 sysclk_ind  = get_sys_clk_index();
 191         u32 omap_rev    = omap_revision();
 192
 193         if (!is_omap54xx())
 194                 return;
 195
 196         mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
 197         div_factor = srcomp_parameters[sysclk_ind].divide_factor;
 198
 199         for (i = 0; i < 4; i++) {
 200                 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
 201                 srcomp_value &=
 202                         ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
 203                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 204                         (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 205                 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
 206         }
 207
 208         if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
 209                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 210                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 211                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 212
 213                 for (i = 0; i < 4; i++) {
 214                         srcomp_value =
 215                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 216                         srcomp_value &= ~PWRDWN_XS_MASK;
 217                         writel(srcomp_value,
 218                                (*ctrl)->control_srcomp_north_side + i*4);
 219
 220                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 221                                 & SRCODE_READ_XS_MASK) >>
 222                                 SRCODE_READ_XS_SHIFT) == 0)
 223                                 ;
 224
 225                         srcomp_value =
 226                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 227                         srcomp_value &= ~OVERRIDE_XS_MASK;
 228                         writel(srcomp_value,
 229                                (*ctrl)->control_srcomp_north_side + i*4);
 230                 }
 231         } else {
 232                 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
 233                 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
 234                                   DIVIDE_FACTOR_XS_MASK);
 235                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 236                                 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 237                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 238
 239                 for (i = 0; i < 4; i++) {
 240                         srcomp_value =
 241                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 242                         srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 243                         writel(srcomp_value,
 244                                (*ctrl)->control_srcomp_north_side + i*4);
 245
 246                         srcomp_value =
 247                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 248                         srcomp_value &= ~OVERRIDE_XS_MASK;
 249                         writel(srcomp_value,
 250                                (*ctrl)->control_srcomp_north_side + i*4);
 251                 }
 252
 253                 srcomp_value =
 254                         readl((*ctrl)->control_srcomp_east_side_wkup);
 255                 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 256                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 257
 258                 srcomp_value =
 259                         readl((*ctrl)->control_srcomp_east_side_wkup);
 260                 srcomp_value &= ~OVERRIDE_XS_MASK;
 261                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 262
 263                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 264                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 265                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 266
 267                 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 268                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 269                 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 270
 271                 for (i = 0; i < 4; i++) {
 272                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 273                                 & SRCODE_READ_XS_MASK) >>
 274                                 SRCODE_READ_XS_SHIFT) == 0)
 275                                 ;
 276
 277                         srcomp_value =
 278                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 279                         srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 280                         writel(srcomp_value,
 281                                (*ctrl)->control_srcomp_north_side + i*4);
 282                 }
 283
 284                 while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
 285                         SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
 286                         ;
 287
 288                 srcomp_value =
 289                         readl((*ctrl)->control_srcomp_east_side_wkup);
 290                 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 291                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 292         }
 293 }
 294 #endif
 295
 296 void config_data_eye_leveling_samples(u32 emif_base)
 297 {
 298         const struct ctrl_ioregs *ioregs;
 299
 300         get_ioregs(&ioregs);
 301
 302         /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 303         if (emif_base == EMIF1_BASE)
 304                 writel(ioregs->ctrl_emif_sdram_config_ext_final,
 305                        (*ctrl)->control_emif1_sdram_config_ext);
 306         else if (emif_base == EMIF2_BASE)
 307                 writel(ioregs->ctrl_emif_sdram_config_ext_final,
 308                        (*ctrl)->control_emif2_sdram_config_ext);
 309 }
 310
 311 void init_cpu_configuration(void)
 312 {
 313         u32 l2actlr;
 314
 315         asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
 316         /*
 317          * L2ACTLR: Ensure to enable the following:
 318          * 3: Disable clean/evict push to external
 319          * 4: Disable WriteUnique and WriteLineUnique transactions from master
 320          * 8: Disable DVM/CMO message broadcast
 321          */
 322         l2actlr |= 0x118;
 323         omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
 324 }
 325
 326 void init_omap_revision(void)
 327 {
 328         /*
 329          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 330          * Also, ES1 and ES2 have different ARM revisions
 331          * So use ARM revision for identification
 332          */
 333         unsigned int rev = cortex_rev();
 334
 335         switch (readl(CONTROL_ID_CODE)) {
 336         case OMAP5430_CONTROL_ID_CODE_ES1_0:
 337                 *omap_si_rev = OMAP5430_ES1_0;
 338                 if (rev == MIDR_CORTEX_A15_R2P2)
 339                         *omap_si_rev = OMAP5430_ES2_0;
 340                 break;
 341         case OMAP5432_CONTROL_ID_CODE_ES1_0:
 342                 *omap_si_rev = OMAP5432_ES1_0;
 343                 if (rev == MIDR_CORTEX_A15_R2P2)
 344                         *omap_si_rev = OMAP5432_ES2_0;
 345                 break;
 346         case OMAP5430_CONTROL_ID_CODE_ES2_0:
 347                 *omap_si_rev = OMAP5430_ES2_0;
 348                 break;
 349         case OMAP5432_CONTROL_ID_CODE_ES2_0:
 350                 *omap_si_rev = OMAP5432_ES2_0;
 351                 break;
 352         case DRA752_CONTROL_ID_CODE_ES1_0:
 353                 *omap_si_rev = DRA752_ES1_0;
 354                 break;
 355         case DRA752_CONTROL_ID_CODE_ES1_1:
 356                 *omap_si_rev = DRA752_ES1_1;
 357                 break;
 358         case DRA722_CONTROL_ID_CODE_ES1_0:
 359                 *omap_si_rev = DRA722_ES1_0;
 360                 break;
 361         default:
 362                 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 363         }
 364         init_cpu_configuration();
 365 }
 366
 367 void reset_cpu(ulong ignored)
 368 {
 369         u32 omap_rev = omap_revision();
 370
 371         /*
 372          * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 373          * So use cold reset in case instead.
 374          */
 375         if (omap_rev == OMAP5430_ES1_0)
 376                 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
 377         else
 378                 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
 379 }
 380
 381 u32 warm_reset(void)
 382 {
 383         return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 384 }
 385
 386 void setup_warmreset_time(void)
 387 {
 388         u32 rst_time, rst_val;
 389
 390 #ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
 391         rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
 392 #else
 393         rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
 394 #endif
 395         rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
 396
 397         if (rst_time > RSTTIME1_MASK)
 398                 rst_time = RSTTIME1_MASK;
 399
 400         rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
 401         rst_val |= rst_time;
 402         writel(rst_val, (*prcm)->prm_rsttime);
 403 }
 404
 405 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 406                                  u32 cpu_rev_comb, u32 cpu_variant,
 407                                  u32 cpu_rev)
 408 {
 409         omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
 410 }