arch/arm/cpu/armv7/omap5/hwinit.c

   1 /*
   2  *
   3  * Functions for omap5 based boards.
   4  *
   5  * (C) Copyright 2011
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *      Sricharan       <r.sricharan@ti.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31 #include <common.h>
  32 #include <asm/armv7.h>
  33 #include <asm/arch/cpu.h>
  34 #include <asm/arch/sys_proto.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/sizes.h>
  37 #include <asm/utils.h>
  38 #include <asm/arch/gpio.h>
  39 #include <asm/emif.h>
  40 #include <asm/omap_common.h>
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  45
  46 static struct gpio_bank gpio_bank_54xx[6] = {
  47         { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
  48         { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
  49         { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
  50         { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
  51         { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
  52         { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
  53 };
  54
  55 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  56
  57 #ifdef CONFIG_SPL_BUILD
  58 /* LPDDR2 specific IO settings */
  59 static void io_settings_lpddr2(void)
  60 {
  61         const struct ctrl_ioregs *ioregs;
  62
  63         get_ioregs(&ioregs);
  64         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  65         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  66         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  67         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  68         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  69         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  70         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  71         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  72         writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  73 }
  74
  75 /* DDR3 specific IO settings */
  76 static void io_settings_ddr3(void)
  77 {
  78         u32 io_settings = 0;
  79         const struct ctrl_ioregs *ioregs;
  80
  81         get_ioregs(&ioregs);
  82         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  83         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  84         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  85
  86         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  87         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  88         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  89
  90         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  91         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  92         writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  93
  94         /* omap5432 does not use lpddr2 */
  95         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  96         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  97
  98         writel(ioregs->ctrl_emif_sdram_config_ext,
  99                (*ctrl)->control_emif1_sdram_config_ext);
 100         writel(ioregs->ctrl_emif_sdram_config_ext,
 101                (*ctrl)->control_emif2_sdram_config_ext);
 102
 103         if (is_omap54xx()) {
 104                 /* Disable DLL select */
 105                 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
 106                                                         & 0xFFEFFFFF);
 107                 writel(io_settings,
 108                         (*ctrl)->control_port_emif1_sdram_config);
 109
 110                 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
 111                                                         & 0xFFEFFFFF);
 112                 writel(io_settings,
 113                         (*ctrl)->control_port_emif2_sdram_config);
 114         } else {
 115                 writel(ioregs->ctrl_ddr_ctrl_ext_0,
 116                                 (*ctrl)->control_ddr_control_ext_0);
 117         }
 118 }
 119
 120 /*
 121  * Some tuning of IOs for optimal power and performance
 122  */
 123 void do_io_settings(void)
 124 {
 125         u32 io_settings = 0, mask = 0;
 126
 127         /* Impedance settings EMMC, C2C 1,2, hsi2 */
 128         mask = (ds_mask << 2) | (ds_mask << 8) |
 129                 (ds_mask << 16) | (ds_mask << 18);
 130         io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
 131                                 (~mask);
 132         io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 133                         (ds_45_ohm << 18) | (ds_60_ohm << 2);
 134         writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
 135
 136         /* Impedance settings Mcspi2 */
 137         mask = (ds_mask << 30);
 138         io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
 139                         (~mask);
 140         io_settings |= (ds_60_ohm << 30);
 141         writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
 142
 143         /* Impedance settings C2C 3,4 */
 144         mask = (ds_mask << 14) | (ds_mask << 16);
 145         io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
 146                         (~mask);
 147         io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 148         writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
 149
 150         /* Slew rate settings EMMC, C2C 1,2 */
 151         mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 152         io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
 153                         (~mask);
 154         io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 155         writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
 156
 157         /* Slew rate settings hsi2, Mcspi2 */
 158         mask = (sc_mask << 24) | (sc_mask << 28);
 159         io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
 160                         (~mask);
 161         io_settings |= (sc_fast << 28) | (sc_fast << 24);
 162         writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
 163
 164         /* Slew rate settings C2C 3,4 */
 165         mask = (sc_mask << 16) | (sc_mask << 18);
 166         io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
 167                         (~mask);
 168         io_settings |= (sc_na << 16) | (sc_na << 18);
 169         writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
 170
 171         /* impedance and slew rate settings for usb */
 172         mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 173                 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 174         io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
 175                         (~mask);
 176         io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 177                        (ds_60_ohm << 23) | (sc_fast << 20) |
 178                        (sc_fast << 17) | (sc_fast << 14);
 179         writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 180
 181         if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
 182                 io_settings_lpddr2();
 183         else
 184                 io_settings_ddr3();
 185
 186         /* Efuse settings */
 187         writel(EFUSE_1, (*ctrl)->control_efuse_1);
 188         writel(EFUSE_2, (*ctrl)->control_efuse_2);
 189         writel(EFUSE_3, (*ctrl)->control_efuse_3);
 190         writel(EFUSE_4, (*ctrl)->control_efuse_4);
 191 }
 192
 193 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
 194         {0x45, 0x1},    /* 12 MHz   */
 195         {-1, -1},       /* 13 MHz   */
 196         {0x63, 0x2},    /* 16.8 MHz */
 197         {0x57, 0x2},    /* 19.2 MHz */
 198         {0x20, 0x1},    /* 26 MHz   */
 199         {-1, -1},       /* 27 MHz   */
 200         {0x41, 0x3}     /* 38.4 MHz */
 201 };
 202
 203 void srcomp_enable(void)
 204 {
 205         u32 srcomp_value, mul_factor, div_factor, clk_val, i;
 206         u32 sysclk_ind  = get_sys_clk_index();
 207         u32 omap_rev    = omap_revision();
 208
 209         if (!is_omap54xx())
 210                 return;
 211
 212         mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
 213         div_factor = srcomp_parameters[sysclk_ind].divide_factor;
 214
 215         for (i = 0; i < 4; i++) {
 216                 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
 217                 srcomp_value &=
 218                         ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
 219                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 220                         (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 221                 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
 222         }
 223
 224         if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
 225                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 226                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 227                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 228
 229                 for (i = 0; i < 4; i++) {
 230                         srcomp_value =
 231                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 232                         srcomp_value &= ~PWRDWN_XS_MASK;
 233                         writel(srcomp_value,
 234                                (*ctrl)->control_srcomp_north_side + i*4);
 235
 236                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 237                                 & SRCODE_READ_XS_MASK) >>
 238                                 SRCODE_READ_XS_SHIFT) == 0)
 239                                 ;
 240
 241                         srcomp_value =
 242                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 243                         srcomp_value &= ~OVERRIDE_XS_MASK;
 244                         writel(srcomp_value,
 245                                (*ctrl)->control_srcomp_north_side + i*4);
 246                 }
 247         } else {
 248                 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
 249                 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
 250                                   DIVIDE_FACTOR_XS_MASK);
 251                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 252                                 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 253                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 254
 255                 for (i = 0; i < 4; i++) {
 256                         srcomp_value =
 257                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 258                         srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 259                         writel(srcomp_value,
 260                                (*ctrl)->control_srcomp_north_side + i*4);
 261
 262                         srcomp_value =
 263                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 264                         srcomp_value &= ~OVERRIDE_XS_MASK;
 265                         writel(srcomp_value,
 266                                (*ctrl)->control_srcomp_north_side + i*4);
 267                 }
 268
 269                 srcomp_value =
 270                         readl((*ctrl)->control_srcomp_east_side_wkup);
 271                 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 272                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 273
 274                 srcomp_value =
 275                         readl((*ctrl)->control_srcomp_east_side_wkup);
 276                 srcomp_value &= ~OVERRIDE_XS_MASK;
 277                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 278
 279                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 280                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 281                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 282
 283                 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 284                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 285                 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 286
 287                 for (i = 0; i < 4; i++) {
 288                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 289                                 & SRCODE_READ_XS_MASK) >>
 290                                 SRCODE_READ_XS_SHIFT) == 0)
 291                                 ;
 292
 293                         srcomp_value =
 294                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 295                         srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 296                         writel(srcomp_value,
 297                                (*ctrl)->control_srcomp_north_side + i*4);
 298                 }
 299
 300                 while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
 301                         SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
 302                         ;
 303
 304                 srcomp_value =
 305                         readl((*ctrl)->control_srcomp_east_side_wkup);
 306                 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 307                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 308         }
 309 }
 310 #endif
 311
 312 void config_data_eye_leveling_samples(u32 emif_base)
 313 {
 314         /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 315         if (emif_base == EMIF1_BASE)
 316                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 317                         (*ctrl)->control_emif1_sdram_config_ext);
 318         else if (emif_base == EMIF2_BASE)
 319                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 320                         (*ctrl)->control_emif2_sdram_config_ext);
 321 }
 322
 323 void init_omap_revision(void)
 324 {
 325         /*
 326          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 327          * Also, ES1 and ES2 have different ARM revisions
 328          * So use ARM revision for identification
 329          */
 330         unsigned int rev = cortex_rev();
 331
 332         switch (readl(CONTROL_ID_CODE)) {
 333         case OMAP5430_CONTROL_ID_CODE_ES1_0:
 334                 *omap_si_rev = OMAP5430_ES1_0;
 335                 if (rev == MIDR_CORTEX_A15_R2P2)
 336                         *omap_si_rev = OMAP5430_ES2_0;
 337                 break;
 338         case OMAP5432_CONTROL_ID_CODE_ES1_0:
 339                 *omap_si_rev = OMAP5432_ES1_0;
 340                 if (rev == MIDR_CORTEX_A15_R2P2)
 341                         *omap_si_rev = OMAP5432_ES2_0;
 342                 break;
 343         case OMAP5430_CONTROL_ID_CODE_ES2_0:
 344                 *omap_si_rev = OMAP5430_ES2_0;
 345                 break;
 346         case OMAP5432_CONTROL_ID_CODE_ES2_0:
 347                 *omap_si_rev = OMAP5432_ES2_0;
 348                 break;
 349         case DRA752_CONTROL_ID_CODE_ES1_0:
 350                 *omap_si_rev = DRA752_ES1_0;
 351                 break;
 352         default:
 353                 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 354         }
 355 }
 356
 357 void reset_cpu(ulong ignored)
 358 {
 359         u32 omap_rev = omap_revision();
 360
 361         /*
 362          * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 363          * So use cold reset in case instead.
 364          */
 365         if (omap_rev == OMAP5430_ES1_0)
 366                 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
 367         else
 368                 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
 369 }
 370
 371 u32 warm_reset(void)
 372 {
 373         return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 374 }
 375
 376 void setup_warmreset_time(void)
 377 {
 378         u32 rst_time, rst_val;
 379
 380 #ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
 381         rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
 382 #else
 383         rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
 384 #endif
 385         rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
 386
 387         if (rst_time > RSTTIME1_MASK)
 388                 rst_time = RSTTIME1_MASK;
 389
 390         rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
 391         rst_val |= rst_time;
 392         writel(rst_val, (*prcm)->prm_rsttime);
 393 }