arch/arm/cpu/armv7/omap5/hwinit.c

   1 /*
   2  *
   3  * Functions for omap5 based boards.
   4  *
   5  * (C) Copyright 2011
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *      Sricharan       <r.sricharan@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15 #include <common.h>
  16 #include <asm/armv7.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/clock.h>
  20 #include <linux/sizes.h>
  21 #include <asm/utils.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/emif.h>
  24 #include <asm/omap_common.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  29
  30 #ifndef CONFIG_DM_GPIO
  31 static struct gpio_bank gpio_bank_54xx[8] = {
  32         { (void *)OMAP54XX_GPIO1_BASE },
  33         { (void *)OMAP54XX_GPIO2_BASE },
  34         { (void *)OMAP54XX_GPIO3_BASE },
  35         { (void *)OMAP54XX_GPIO4_BASE },
  36         { (void *)OMAP54XX_GPIO5_BASE },
  37         { (void *)OMAP54XX_GPIO6_BASE },
  38         { (void *)OMAP54XX_GPIO7_BASE },
  39         { (void *)OMAP54XX_GPIO8_BASE },
  40 };
  41
  42 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  43 #endif
  44
  45 void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
  46 {
  47         int i;
  48         struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
  49
  50         for (i = 0; i < size; i++, pad++)
  51                 writel(pad->val, base + pad->offset);
  52 }
  53
  54 #ifdef CONFIG_SPL_BUILD
  55 /* LPDDR2 specific IO settings */
  56 static void io_settings_lpddr2(void)
  57 {
  58         const struct ctrl_ioregs *ioregs;
  59
  60         get_ioregs(&ioregs);
  61         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  62         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  63         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  64         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  65         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  66         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  67         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  68         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  69         writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  70 }
  71
  72 /* DDR3 specific IO settings */
  73 static void io_settings_ddr3(void)
  74 {
  75         u32 io_settings = 0;
  76         const struct ctrl_ioregs *ioregs;
  77
  78         get_ioregs(&ioregs);
  79         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  80         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  81         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  82
  83         writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  84         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  85         writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  86
  87         writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  88         writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  89
  90         if (!is_dra7xx()) {
  91                 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  92                 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  93         }
  94
  95         /* omap5432 does not use lpddr2 */
  96         writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  97
  98         writel(ioregs->ctrl_emif_sdram_config_ext,
  99                (*ctrl)->control_emif1_sdram_config_ext);
 100         if (!is_dra72x())
 101                 writel(ioregs->ctrl_emif_sdram_config_ext,
 102                        (*ctrl)->control_emif2_sdram_config_ext);
 103
 104         if (is_omap54xx()) {
 105                 /* Disable DLL select */
 106                 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
 107                                                         & 0xFFEFFFFF);
 108                 writel(io_settings,
 109                         (*ctrl)->control_port_emif1_sdram_config);
 110
 111                 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
 112                                                         & 0xFFEFFFFF);
 113                 writel(io_settings,
 114                         (*ctrl)->control_port_emif2_sdram_config);
 115         } else {
 116                 writel(ioregs->ctrl_ddr_ctrl_ext_0,
 117                                 (*ctrl)->control_ddr_control_ext_0);
 118         }
 119 }
 120
 121 /*
 122  * Some tuning of IOs for optimal power and performance
 123  */
 124 void do_io_settings(void)
 125 {
 126         u32 io_settings = 0, mask = 0;
 127         struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
 128
 129         /* Impedance settings EMMC, C2C 1,2, hsi2 */
 130         mask = (ds_mask << 2) | (ds_mask << 8) |
 131                 (ds_mask << 16) | (ds_mask << 18);
 132         io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
 133                                 (~mask);
 134         io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 135                         (ds_45_ohm << 18) | (ds_60_ohm << 2);
 136         writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
 137
 138         /* Impedance settings Mcspi2 */
 139         mask = (ds_mask << 30);
 140         io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
 141                         (~mask);
 142         io_settings |= (ds_60_ohm << 30);
 143         writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
 144
 145         /* Impedance settings C2C 3,4 */
 146         mask = (ds_mask << 14) | (ds_mask << 16);
 147         io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
 148                         (~mask);
 149         io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 150         writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
 151
 152         /* Slew rate settings EMMC, C2C 1,2 */
 153         mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 154         io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
 155                         (~mask);
 156         io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 157         writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
 158
 159         /* Slew rate settings hsi2, Mcspi2 */
 160         mask = (sc_mask << 24) | (sc_mask << 28);
 161         io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
 162                         (~mask);
 163         io_settings |= (sc_fast << 28) | (sc_fast << 24);
 164         writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
 165
 166         /* Slew rate settings C2C 3,4 */
 167         mask = (sc_mask << 16) | (sc_mask << 18);
 168         io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
 169                         (~mask);
 170         io_settings |= (sc_na << 16) | (sc_na << 18);
 171         writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
 172
 173         /* impedance and slew rate settings for usb */
 174         mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 175                 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 176         io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
 177                         (~mask);
 178         io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 179                        (ds_60_ohm << 23) | (sc_fast << 20) |
 180                        (sc_fast << 17) | (sc_fast << 14);
 181         writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
 182
 183         if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
 184                 io_settings_lpddr2();
 185         else
 186                 io_settings_ddr3();
 187 }
 188
 189 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
 190         {0x45, 0x1},    /* 12 MHz   */
 191         {-1, -1},       /* 13 MHz   */
 192         {0x63, 0x2},    /* 16.8 MHz */
 193         {0x57, 0x2},    /* 19.2 MHz */
 194         {0x20, 0x1},    /* 26 MHz   */
 195         {-1, -1},       /* 27 MHz   */
 196         {0x41, 0x3}     /* 38.4 MHz */
 197 };
 198
 199 void srcomp_enable(void)
 200 {
 201         u32 srcomp_value, mul_factor, div_factor, clk_val, i;
 202         u32 sysclk_ind  = get_sys_clk_index();
 203         u32 omap_rev    = omap_revision();
 204
 205         if (!is_omap54xx())
 206                 return;
 207
 208         mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
 209         div_factor = srcomp_parameters[sysclk_ind].divide_factor;
 210
 211         for (i = 0; i < 4; i++) {
 212                 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
 213                 srcomp_value &=
 214                         ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
 215                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 216                         (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 217                 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
 218         }
 219
 220         if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
 221                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 222                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 223                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 224
 225                 for (i = 0; i < 4; i++) {
 226                         srcomp_value =
 227                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 228                         srcomp_value &= ~PWRDWN_XS_MASK;
 229                         writel(srcomp_value,
 230                                (*ctrl)->control_srcomp_north_side + i*4);
 231
 232                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 233                                 & SRCODE_READ_XS_MASK) >>
 234                                 SRCODE_READ_XS_SHIFT) == 0)
 235                                 ;
 236
 237                         srcomp_value =
 238                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 239                         srcomp_value &= ~OVERRIDE_XS_MASK;
 240                         writel(srcomp_value,
 241                                (*ctrl)->control_srcomp_north_side + i*4);
 242                 }
 243         } else {
 244                 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
 245                 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
 246                                   DIVIDE_FACTOR_XS_MASK);
 247                 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
 248                                 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
 249                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 250
 251                 for (i = 0; i < 4; i++) {
 252                         srcomp_value =
 253                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 254                         srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 255                         writel(srcomp_value,
 256                                (*ctrl)->control_srcomp_north_side + i*4);
 257
 258                         srcomp_value =
 259                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 260                         srcomp_value &= ~OVERRIDE_XS_MASK;
 261                         writel(srcomp_value,
 262                                (*ctrl)->control_srcomp_north_side + i*4);
 263                 }
 264
 265                 srcomp_value =
 266                         readl((*ctrl)->control_srcomp_east_side_wkup);
 267                 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
 268                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 269
 270                 srcomp_value =
 271                         readl((*ctrl)->control_srcomp_east_side_wkup);
 272                 srcomp_value &= ~OVERRIDE_XS_MASK;
 273                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 274
 275                 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
 276                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 277                 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
 278
 279                 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 280                 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
 281                 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
 282
 283                 for (i = 0; i < 4; i++) {
 284                         while (((readl((*ctrl)->control_srcomp_north_side + i*4)
 285                                 & SRCODE_READ_XS_MASK) >>
 286                                 SRCODE_READ_XS_SHIFT) == 0)
 287                                 ;
 288
 289                         srcomp_value =
 290                                 readl((*ctrl)->control_srcomp_north_side + i*4);
 291                         srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 292                         writel(srcomp_value,
 293                                (*ctrl)->control_srcomp_north_side + i*4);
 294                 }
 295
 296                 while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
 297                         SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
 298                         ;
 299
 300                 srcomp_value =
 301                         readl((*ctrl)->control_srcomp_east_side_wkup);
 302                 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
 303                 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
 304         }
 305 }
 306 #endif
 307
 308 void config_data_eye_leveling_samples(u32 emif_base)
 309 {
 310         const struct ctrl_ioregs *ioregs;
 311
 312         get_ioregs(&ioregs);
 313
 314         /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 315         if (emif_base == EMIF1_BASE)
 316                 writel(ioregs->ctrl_emif_sdram_config_ext_final,
 317                        (*ctrl)->control_emif1_sdram_config_ext);
 318         else if (emif_base == EMIF2_BASE)
 319                 writel(ioregs->ctrl_emif_sdram_config_ext_final,
 320                        (*ctrl)->control_emif2_sdram_config_ext);
 321 }
 322
 323 void init_cpu_configuration(void)
 324 {
 325         u32 l2actlr;
 326
 327         asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
 328         /*
 329          * L2ACTLR: Ensure to enable the following:
 330          * 3: Disable clean/evict push to external
 331          * 4: Disable WriteUnique and WriteLineUnique transactions from master
 332          * 8: Disable DVM/CMO message broadcast
 333          */
 334         l2actlr |= 0x118;
 335         omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
 336 }
 337
 338 void init_omap_revision(void)
 339 {
 340         /*
 341          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 342          * Also, ES1 and ES2 have different ARM revisions
 343          * So use ARM revision for identification
 344          */
 345         unsigned int rev = cortex_rev();
 346
 347         switch (readl(CONTROL_ID_CODE)) {
 348         case OMAP5430_CONTROL_ID_CODE_ES1_0:
 349                 *omap_si_rev = OMAP5430_ES1_0;
 350                 if (rev == MIDR_CORTEX_A15_R2P2)
 351                         *omap_si_rev = OMAP5430_ES2_0;
 352                 break;
 353         case OMAP5432_CONTROL_ID_CODE_ES1_0:
 354                 *omap_si_rev = OMAP5432_ES1_0;
 355                 if (rev == MIDR_CORTEX_A15_R2P2)
 356                         *omap_si_rev = OMAP5432_ES2_0;
 357                 break;
 358         case OMAP5430_CONTROL_ID_CODE_ES2_0:
 359                 *omap_si_rev = OMAP5430_ES2_0;
 360                 break;
 361         case OMAP5432_CONTROL_ID_CODE_ES2_0:
 362                 *omap_si_rev = OMAP5432_ES2_0;
 363                 break;
 364         case DRA752_CONTROL_ID_CODE_ES1_0:
 365                 *omap_si_rev = DRA752_ES1_0;
 366                 break;
 367         case DRA752_CONTROL_ID_CODE_ES1_1:
 368                 *omap_si_rev = DRA752_ES1_1;
 369                 break;
 370         case DRA752_CONTROL_ID_CODE_ES2_0:
 371                 *omap_si_rev = DRA752_ES2_0;
 372                 break;
 373         case DRA722_CONTROL_ID_CODE_ES1_0:
 374                 *omap_si_rev = DRA722_ES1_0;
 375                 break;
 376         default:
 377                 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 378         }
 379         init_cpu_configuration();
 380 }
 381
 382 void reset_cpu(ulong ignored)
 383 {
 384         u32 omap_rev = omap_revision();
 385
 386         /*
 387          * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 388          * So use cold reset in case instead.
 389          */
 390         if (omap_rev == OMAP5430_ES1_0)
 391                 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
 392         else
 393                 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
 394 }
 395
 396 u32 warm_reset(void)
 397 {
 398         return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 399 }
 400
 401 void setup_warmreset_time(void)
 402 {
 403         u32 rst_time, rst_val;
 404
 405 #ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
 406         rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
 407 #else
 408         rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
 409 #endif
 410         rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
 411
 412         if (rst_time > RSTTIME1_MASK)
 413                 rst_time = RSTTIME1_MASK;
 414
 415         rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
 416         rst_val |= rst_time;
 417         writel(rst_val, (*prcm)->prm_rsttime);
 418 }
 419
 420 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 421                                  u32 cpu_rev_comb, u32 cpu_variant,
 422                                  u32 cpu_rev)
 423 {
 424         omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
 425 }
 426
 427 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
 428                           u32 cpu_variant, u32 cpu_rev)
 429 {
 430
 431 #ifdef CONFIG_ARM_ERRATA_801819
 432         /*
 433          * DRA72x processors are uniprocessors and DONOT have
 434          * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
 435          * Extensions) Hence the erratum workaround is not applicable for
 436          * DRA72x processors.
 437          */
 438         if (is_dra72x())
 439                 acr &= ~((0x3 << 23) | (0x3 << 25));
 440 #endif
 441         omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
 442 }