arch/arm/cpu/armv7/omap5/hwinit.c

   1 /*
   2  *
   3  * Functions for omap5 based boards.
   4  *
   5  * (C) Copyright 2011
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author :
   9  *      Aneesh V        <aneesh@ti.com>
  10  *      Steve Sakoman   <steve@sakoman.com>
  11  *      Sricharan       <r.sricharan@ti.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31 #include <common.h>
  32 #include <asm/armv7.h>
  33 #include <asm/arch/cpu.h>
  34 #include <asm/arch/sys_proto.h>
  35 #include <asm/sizes.h>
  36 #include <asm/utils.h>
  37 #include <asm/arch/gpio.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
  42
  43 static struct gpio_bank gpio_bank_54xx[6] = {
  44         { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
  45         { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
  46         { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
  47         { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
  48         { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
  49         { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
  50 };
  51
  52 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  53
  54 #ifdef CONFIG_SPL_BUILD
  55 /* LPDDR2 specific IO settings */
  56 static void io_settings_lpddr2(void)
  57 {
  58         struct omap_sys_ctrl_regs *ioregs_base =
  59                       (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
  60
  61         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  62                                 &(ioregs_base->control_ddrch1_0));
  63         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  64                                 &(ioregs_base->control_ddrch1_1));
  65         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  66                                 &(ioregs_base->control_ddrch2_0));
  67         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  68                                 &(ioregs_base->control_ddrch2_1));
  69         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
  70                                 &(ioregs_base->control_lpddr2ch1_0));
  71         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
  72                                 &(ioregs_base->control_lpddr2ch1_1));
  73         writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
  74                                 &(ioregs_base->control_ddrio_0));
  75         writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
  76                                 &(ioregs_base->control_ddrio_1));
  77         writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
  78                                 &(ioregs_base->control_ddrio_2));
  79 }
  80
  81 /* DDR3 specific IO settings */
  82 static void io_settings_ddr3(void)
  83 {
  84         u32 io_settings = 0;
  85         struct omap_sys_ctrl_regs *ioregs_base =
  86                       (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
  87
  88         writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
  89                                 &(ioregs_base->control_ddr3ch1_0));
  90         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
  91                                 &(ioregs_base->control_ddrch1_0));
  92         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
  93                                 &(ioregs_base->control_ddrch1_1));
  94
  95         writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
  96                                 &(ioregs_base->control_ddr3ch2_0));
  97         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
  98                                 &(ioregs_base->control_ddrch2_0));
  99         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
 100                                 &(ioregs_base->control_ddrch2_1));
 101
 102         writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
 103                                 &(ioregs_base->control_ddrio_0));
 104         writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
 105                                 &(ioregs_base->control_ddrio_1));
 106         writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
 107                                 &(ioregs_base->control_ddrio_2));
 108
 109         /* omap5432 does not use lpddr2 */
 110         writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
 111         writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
 112
 113         writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 114                         &(ioregs_base->control_emif1_sdram_config_ext));
 115         writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
 116                         &(ioregs_base->control_emif2_sdram_config_ext));
 117
 118         /* Disable DLL select */
 119         io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
 120                                                         & 0xFFEFFFFF);
 121         writel(io_settings,
 122                 &(ioregs_base->control_port_emif1_sdram_config));
 123
 124         io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
 125                                                         & 0xFFEFFFFF);
 126         writel(io_settings,
 127                 &(ioregs_base->control_port_emif2_sdram_config));
 128 }
 129
 130 /*
 131  * Some tuning of IOs for optimal power and performance
 132  */
 133 void do_io_settings(void)
 134 {
 135         u32 io_settings = 0, mask = 0;
 136         struct omap_sys_ctrl_regs *ioregs_base =
 137                       (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
 138
 139         /* Impedance settings EMMC, C2C 1,2, hsi2 */
 140         mask = (ds_mask << 2) | (ds_mask << 8) |
 141                 (ds_mask << 16) | (ds_mask << 18);
 142         io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) &
 143                                 (~mask);
 144         io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
 145                         (ds_45_ohm << 18) | (ds_60_ohm << 2);
 146         writel(io_settings, &(ioregs_base->control_smart1io_padconf_0));
 147
 148         /* Impedance settings Mcspi2 */
 149         mask = (ds_mask << 30);
 150         io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) &
 151                         (~mask);
 152         io_settings |= (ds_60_ohm << 30);
 153         writel(io_settings, &(ioregs_base->control_smart1io_padconf_1));
 154
 155         /* Impedance settings C2C 3,4 */
 156         mask = (ds_mask << 14) | (ds_mask << 16);
 157         io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) &
 158                         (~mask);
 159         io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
 160         writel(io_settings, &(ioregs_base->control_smart1io_padconf_2));
 161
 162         /* Slew rate settings EMMC, C2C 1,2 */
 163         mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
 164         io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) &
 165                         (~mask);
 166         io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
 167         writel(io_settings, &(ioregs_base->control_smart2io_padconf_0));
 168
 169         /* Slew rate settings hsi2, Mcspi2 */
 170         mask = (sc_mask << 24) | (sc_mask << 28);
 171         io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) &
 172                         (~mask);
 173         io_settings |= (sc_fast << 28) | (sc_fast << 24);
 174         writel(io_settings, &(ioregs_base->control_smart2io_padconf_1));
 175
 176         /* Slew rate settings C2C 3,4 */
 177         mask = (sc_mask << 16) | (sc_mask << 18);
 178         io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) &
 179                         (~mask);
 180         io_settings |= (sc_na << 16) | (sc_na << 18);
 181         writel(io_settings, &(ioregs_base->control_smart2io_padconf_2));
 182
 183         /* impedance and slew rate settings for usb */
 184         mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
 185                 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
 186         io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) &
 187                         (~mask);
 188         io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
 189                        (ds_60_ohm << 23) | (sc_fast << 20) |
 190                        (sc_fast << 17) | (sc_fast << 14);
 191         writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
 192
 193         if (omap_revision() <= OMAP5430_ES1_0)
 194                 io_settings_lpddr2();
 195         else
 196                 io_settings_ddr3();
 197
 198         /* Efuse settings */
 199         writel(EFUSE_1, &(ioregs_base->control_efuse_1));
 200         writel(EFUSE_2, &(ioregs_base->control_efuse_2));
 201         writel(EFUSE_3, &(ioregs_base->control_efuse_3));
 202         writel(EFUSE_4, &(ioregs_base->control_efuse_4));
 203 }
 204 #endif
 205
 206 void init_omap_revision(void)
 207 {
 208         /*
 209          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 210          * Also, ES1 and ES2 have different ARM revisions
 211          * So use ARM revision for identification
 212          */
 213         unsigned int rev = cortex_rev();
 214
 215         switch (rev) {
 216         case MIDR_CORTEX_A15_R0P0:
 217                 switch (readl(CONTROL_ID_CODE)) {
 218                 case OMAP5430_CONTROL_ID_CODE_ES1_0:
 219                         *omap_si_rev = OMAP5430_ES1_0;
 220                         break;
 221                 case OMAP5432_CONTROL_ID_CODE_ES1_0:
 222                 default:
 223                         *omap_si_rev = OMAP5432_ES1_0;
 224                         break;
 225                 }
 226                 break;
 227         default:
 228                 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 229         }
 230 }
 231
 232 void reset_cpu(ulong ignored)
 233 {
 234         u32 omap_rev = omap_revision();
 235
 236         /*
 237          * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
 238          * So use cold reset in case instead.
 239          */
 240         if (omap_rev == OMAP5430_ES1_0)
 241                 writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
 242         else
 243                 writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
 244 }