arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm/emif.h>
  31 #include <asm/arch/sys_proto.h>
  32
  33 /*
  34  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  35  * EVM. Since the parts used and geometry are identical for
  36  * evm for a given OMAP5 revision, this information is kept
  37  * here instead of being in board directory. However the key functions
  38  * exported are weakly linked so that they can be over-ridden in the board
  39  * directory if there is a OMAP5 board in the future that uses a different
  40  * memory device or geometry.
  41  *
  42  * For any new board with different memory devices over-ride one or more
  43  * of the following functions as per the CONFIG flags you intend to enable:
  44  * - emif_get_reg_dump()
  45  * - emif_get_dmm_regs()
  46  * - emif_get_device_details()
  47  * - emif_get_device_timings()
  48  */
  49
  50 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  51 const struct emif_regs emif_regs_532_mhz_2cs = {
  52         .sdram_config_init              = 0x80800EBA,
  53         .sdram_config                   = 0x808022BA,
  54         .ref_ctrl                       = 0x0000081A,
  55         .sdram_tim1                     = 0x772F6873,
  56         .sdram_tim2                     = 0x304a129a,
  57         .sdram_tim3                     = 0x02f7e45f,
  58         .read_idle_ctrl                 = 0x00050000,
  59         .zq_config                      = 0x000b3215,
  60         .temp_alert_config              = 0x08000a05,
  61         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  62         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  63         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  64         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  65         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  66         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  67         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  68 };
  69
  70 const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  71         .sdram_config_init              = 0x80800EBA,
  72         .sdram_config                   = 0x808022BA,
  73         .ref_ctrl                       = 0x0000081A,
  74         .sdram_tim1                     = 0x772F6873,
  75         .sdram_tim2                     = 0x304a129a,
  76         .sdram_tim3                     = 0x02f7e45f,
  77         .read_idle_ctrl                 = 0x00050000,
  78         .zq_config                      = 0x100b3215,
  79         .temp_alert_config              = 0x08000a05,
  80         .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
  81         .emif_ddr_phy_ctlr_1            = 0x0E30400d,
  82         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  83         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  84         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  85         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  86         .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
  87 };
  88
  89 const struct emif_regs emif_regs_266_mhz_2cs = {
  90         .sdram_config_init              = 0x80800EBA,
  91         .sdram_config                   = 0x808022BA,
  92         .ref_ctrl                       = 0x0000040D,
  93         .sdram_tim1                     = 0x2A86B419,
  94         .sdram_tim2                     = 0x1025094A,
  95         .sdram_tim3                     = 0x026BA22F,
  96         .read_idle_ctrl                 = 0x00050000,
  97         .zq_config                      = 0x000b3215,
  98         .temp_alert_config              = 0x08000a05,
  99         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
 100         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
 101         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
 102         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
 103         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
 104         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
 105         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
 106 };
 107
 108 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
 109         .sdram_config_init              = 0x61851B32,
 110         .sdram_config                   = 0x61851B32,
 111         .ref_ctrl                       = 0x00001035,
 112         .sdram_tim1                     = 0xCCCF36B3,
 113         .sdram_tim2                     = 0x308F7FDA,
 114         .sdram_tim3                     = 0x027F88A8,
 115         .read_idle_ctrl                 = 0x00050000,
 116         .zq_config                      = 0x0007190B,
 117         .temp_alert_config              = 0x00000000,
 118         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 119         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 120         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 121         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 122         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 123         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 124         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 125         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 126         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 127         .emif_rd_wr_lvl_ctl             = 0x00000000,
 128         .emif_rd_wr_exec_thresh         = 0x00000305
 129 };
 130
 131 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 132         .sdram_config_init              = 0x61851B32,
 133         .sdram_config                   = 0x61851B32,
 134         .ref_ctrl                       = 0x00001035,
 135         .sdram_tim1                     = 0xCCCF36B3,
 136         .sdram_tim2                     = 0x308F7FDA,
 137         .sdram_tim3                     = 0x027F88A8,
 138         .read_idle_ctrl                 = 0x00050000,
 139         .zq_config                      = 0x1007190B,
 140         .temp_alert_config              = 0x00000000,
 141         .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
 142         .emif_ddr_phy_ctlr_1            = 0x0034400A,
 143         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 144         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 145         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 146         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 147         .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
 148         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 149         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 150         .emif_rd_wr_lvl_ctl             = 0x00000000,
 151         .emif_rd_wr_exec_thresh         = 0x40000305
 152 };
 153
 154 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 155         .dmm_lisa_map_0 = 0x0,
 156         .dmm_lisa_map_1 = 0x0,
 157         .dmm_lisa_map_2 = 0x80740300,
 158         .dmm_lisa_map_3 = 0xFF020100,
 159         .is_ma_present  = 0x1
 160 };
 161
 162 const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
 163         .dmm_lisa_map_0 = 0x0,
 164         .dmm_lisa_map_1 = 0x0,
 165         .dmm_lisa_map_2 = 0x0,
 166         .dmm_lisa_map_3 = 0x80500100,
 167         .is_ma_present  = 0x1
 168 };
 169
 170 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 171 {
 172         switch (omap_revision()) {
 173         case OMAP5430_ES1_0:
 174                 *regs = &emif_regs_532_mhz_2cs;
 175                 break;
 176         case OMAP5432_ES1_0:
 177                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 178                 break;
 179         case OMAP5430_ES2_0:
 180                 *regs = &emif_regs_532_mhz_2cs_es2;
 181                 break;
 182         case OMAP5432_ES2_0:
 183         case DRA752_ES1_0:
 184         default:
 185                 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 186         }
 187 }
 188
 189 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 190         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 191
 192 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 193                                                 **dmm_lisa_regs)
 194 {
 195         switch (omap_revision()) {
 196         case OMAP5430_ES1_0:
 197         case OMAP5430_ES2_0:
 198         case OMAP5432_ES1_0:
 199         case OMAP5432_ES2_0:
 200                 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 201                 break;
 202         case DRA752_ES1_0:
 203         default:
 204                 *dmm_lisa_regs = &lisa_map_512M_x_1;
 205         }
 206
 207 }
 208
 209 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 210         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 211 #else
 212
 213 static const struct lpddr2_device_details dev_4G_S4_details = {
 214         .type           = LPDDR2_TYPE_S4,
 215         .density        = LPDDR2_DENSITY_4Gb,
 216         .io_width       = LPDDR2_IO_WIDTH_32,
 217         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 218 };
 219
 220 static void emif_get_device_details_sdp(u32 emif_nr,
 221                 struct lpddr2_device_details *cs0_device_details,
 222                 struct lpddr2_device_details *cs1_device_details)
 223 {
 224         /* EMIF1 & EMIF2 have identical configuration */
 225         *cs0_device_details = dev_4G_S4_details;
 226         *cs1_device_details = dev_4G_S4_details;
 227 }
 228
 229 void emif_get_device_details(u32 emif_nr,
 230                 struct lpddr2_device_details *cs0_device_details,
 231                 struct lpddr2_device_details *cs1_device_details)
 232         __attribute__((weak, alias("emif_get_device_details_sdp")));
 233
 234 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 235
 236 const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 237         0x01004010,
 238         0x00001004,
 239         0x04010040,
 240         0x01004010,
 241         0x00001004,
 242         0x00000000,
 243         0x00000000,
 244         0x00000000,
 245         0x80080080,
 246         0x00800800,
 247         0x08102040,
 248         0x00000001,
 249         0x540A8150,
 250         0xA81502a0,
 251         0x002A0540,
 252         0x00000000,
 253         0x00000000,
 254         0x00000000,
 255         0x00000077
 256 };
 257
 258 const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 259         0x01004010,
 260         0x00001004,
 261         0x04010040,
 262         0x01004010,
 263         0x00001004,
 264         0x00000000,
 265         0x00000000,
 266         0x00000000,
 267         0x80080080,
 268         0x00800800,
 269         0x08102040,
 270         0x00000002,
 271         0x0,
 272         0x0,
 273         0x0,
 274         0x00000000,
 275         0x00000000,
 276         0x00000000,
 277         0x00000057
 278 };
 279
 280 const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 281         0x50D4350D,
 282         0x00000D43,
 283         0x04010040,
 284         0x01004010,
 285         0x00001004,
 286         0x00000000,
 287         0x00000000,
 288         0x00000000,
 289         0x80080080,
 290         0x00800800,
 291         0x08102040,
 292         0x00000002,
 293         0x00000000,
 294         0x00000000,
 295         0x00000000,
 296         0x00000000,
 297         0x00000000,
 298         0x00000000,
 299         0x00000057
 300 };
 301
 302 const struct lpddr2_mr_regs mr_regs = {
 303         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 304         .mr2    = 0x6,
 305         .mr3    = 0x1,
 306         .mr10   = MR10_ZQ_ZQINIT,
 307         .mr16   = MR16_REF_FULL_ARRAY
 308 };
 309
 310 static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
 311 {
 312         switch (omap_revision()) {
 313         case OMAP5430_ES1_0:
 314         case OMAP5430_ES2_0:
 315                 *regs = ext_phy_ctrl_const_base;
 316                 break;
 317         case OMAP5432_ES1_0:
 318                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 319                 break;
 320         case OMAP5432_ES2_0:
 321         case DRA752_ES1_0:
 322         default:
 323                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 324
 325         }
 326 }
 327
 328 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 329 {
 330         *regs = &mr_regs;
 331 }
 332
 333 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 334 {
 335         u32 *ext_phy_ctrl_base = 0;
 336         u32 *emif_ext_phy_ctrl_base = 0;
 337         const u32 *ext_phy_ctrl_const_regs;
 338         u32 i = 0;
 339
 340         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 341
 342         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 343         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 344
 345         /* Configure external phy control timing registers */
 346         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 347                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 348                 /* Update shadow registers */
 349                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 350         }
 351
 352         /*
 353          * external phy 6-24 registers do not change with
 354          * ddr frequency
 355          */
 356         emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
 357         for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
 358                 writel(ext_phy_ctrl_const_regs[i],
 359                        emif_ext_phy_ctrl_base++);
 360                 /* Update shadow registers */
 361                 writel(ext_phy_ctrl_const_regs[i],
 362                        emif_ext_phy_ctrl_base++);
 363         }
 364 }
 365
 366 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 367 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 368         .max_freq       = 532000000,
 369         .RL             = 8,
 370         .tRPab          = 21,
 371         .tRCD           = 18,
 372         .tWR            = 15,
 373         .tRASmin        = 42,
 374         .tRRD           = 10,
 375         .tWTRx2         = 15,
 376         .tXSR           = 140,
 377         .tXPx2          = 15,
 378         .tRFCab         = 130,
 379         .tRTPx2         = 15,
 380         .tCKE           = 3,
 381         .tCKESR         = 15,
 382         .tZQCS          = 90,
 383         .tZQCL          = 360,
 384         .tZQINIT        = 1000,
 385         .tDQSCKMAXx2    = 11,
 386         .tRASmax        = 70,
 387         .tFAW           = 50
 388 };
 389
 390 static const struct lpddr2_min_tck min_tck = {
 391         .tRL            = 3,
 392         .tRP_AB         = 3,
 393         .tRCD           = 3,
 394         .tWR            = 3,
 395         .tRAS_MIN       = 3,
 396         .tRRD           = 2,
 397         .tWTR           = 2,
 398         .tXP            = 2,
 399         .tRTP           = 2,
 400         .tCKE           = 3,
 401         .tCKESR         = 3,
 402         .tFAW           = 8
 403 };
 404
 405 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 406         &timings_jedec_532_mhz
 407 };
 408
 409 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 410         .ac_timings     = ac_timings,
 411         .min_tck        = &min_tck,
 412 };
 413
 414 void emif_get_device_timings_sdp(u32 emif_nr,
 415                 const struct lpddr2_device_timings **cs0_device_timings,
 416                 const struct lpddr2_device_timings **cs1_device_timings)
 417 {
 418         /* Identical devices on EMIF1 & EMIF2 */
 419         *cs0_device_timings = &dev_4G_S4_timings;
 420         *cs1_device_timings = &dev_4G_S4_timings;
 421 }
 422
 423 void emif_get_device_timings(u32 emif_nr,
 424                 const struct lpddr2_device_timings **cs0_device_timings,
 425                 const struct lpddr2_device_timings **cs1_device_timings)
 426         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 427
 428 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */