arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <asm/emif.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 /*
  18  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  19  * EVM. Since the parts used and geometry are identical for
  20  * evm for a given OMAP5 revision, this information is kept
  21  * here instead of being in board directory. However the key functions
  22  * exported are weakly linked so that they can be over-ridden in the board
  23  * directory if there is a OMAP5 board in the future that uses a different
  24  * memory device or geometry.
  25  *
  26  * For any new board with different memory devices over-ride one or more
  27  * of the following functions as per the CONFIG flags you intend to enable:
  28  * - emif_get_reg_dump()
  29  * - emif_get_dmm_regs()
  30  * - emif_get_device_details()
  31  * - emif_get_device_timings()
  32  */
  33
  34 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  35 const struct emif_regs emif_regs_532_mhz_2cs = {
  36         .sdram_config_init              = 0x80800EBA,
  37         .sdram_config                   = 0x808022BA,
  38         .ref_ctrl                       = 0x0000081A,
  39         .sdram_tim1                     = 0x772F6873,
  40         .sdram_tim2                     = 0x304a129a,
  41         .sdram_tim3                     = 0x02f7e45f,
  42         .read_idle_ctrl                 = 0x00050000,
  43         .zq_config                      = 0x000b3215,
  44         .temp_alert_config              = 0x08000a05,
  45         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  46         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  47         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  48         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  49         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  50         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  51         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  52 };
  53
  54 const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  55         .sdram_config_init              = 0x80800EBA,
  56         .sdram_config                   = 0x808022BA,
  57         .ref_ctrl                       = 0x0000081A,
  58         .sdram_tim1                     = 0x772F6873,
  59         .sdram_tim2                     = 0x304a129a,
  60         .sdram_tim3                     = 0x02f7e45f,
  61         .read_idle_ctrl                 = 0x00050000,
  62         .zq_config                      = 0x100b3215,
  63         .temp_alert_config              = 0x08000a05,
  64         .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
  65         .emif_ddr_phy_ctlr_1            = 0x0E30400d,
  66         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  67         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  68         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  69         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  70         .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
  71 };
  72
  73 const struct emif_regs emif_regs_266_mhz_2cs = {
  74         .sdram_config_init              = 0x80800EBA,
  75         .sdram_config                   = 0x808022BA,
  76         .ref_ctrl                       = 0x0000040D,
  77         .sdram_tim1                     = 0x2A86B419,
  78         .sdram_tim2                     = 0x1025094A,
  79         .sdram_tim3                     = 0x026BA22F,
  80         .read_idle_ctrl                 = 0x00050000,
  81         .zq_config                      = 0x000b3215,
  82         .temp_alert_config              = 0x08000a05,
  83         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  84         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  85         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  86         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
  87         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
  88         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
  89         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  90 };
  91
  92 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  93         .sdram_config_init              = 0x61851B32,
  94         .sdram_config                   = 0x61851B32,
  95         .sdram_config2                  = 0x0,
  96         .ref_ctrl                       = 0x00001035,
  97         .sdram_tim1                     = 0xCCCF36B3,
  98         .sdram_tim2                     = 0x308F7FDA,
  99         .sdram_tim3                     = 0x027F88A8,
 100         .read_idle_ctrl                 = 0x00050000,
 101         .zq_config                      = 0x0007190B,
 102         .temp_alert_config              = 0x00000000,
 103         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 104         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 105         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 106         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 107         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 108         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 109         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 110         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 111         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 112         .emif_rd_wr_lvl_ctl             = 0x00000000,
 113         .emif_rd_wr_exec_thresh         = 0x00000305
 114 };
 115
 116 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 117         .sdram_config_init              = 0x61851B32,
 118         .sdram_config                   = 0x61851B32,
 119         .sdram_config2                  = 0x0,
 120         .ref_ctrl                       = 0x00001035,
 121         .sdram_tim1                     = 0xCCCF36B3,
 122         .sdram_tim2                     = 0x308F7FDA,
 123         .sdram_tim3                     = 0x027F88A8,
 124         .read_idle_ctrl                 = 0x00050000,
 125         .zq_config                      = 0x1007190B,
 126         .temp_alert_config              = 0x00000000,
 127         .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
 128         .emif_ddr_phy_ctlr_1            = 0x0034400A,
 129         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 130         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 131         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 132         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 133         .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
 134         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 135         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 136         .emif_rd_wr_lvl_ctl             = 0x00000000,
 137         .emif_rd_wr_exec_thresh         = 0x40000305
 138 };
 139
 140 const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 141         .sdram_config_init              = 0x61851ab2,
 142         .sdram_config                   = 0x61851ab2,
 143         .sdram_config2                  = 0x08000000,
 144         .ref_ctrl                       = 0x000040F1,
 145         .ref_ctrl_final                 = 0x00001035,
 146         .sdram_tim1                     = 0xCCCF36B3,
 147         .sdram_tim2                     = 0x308F7FDA,
 148         .sdram_tim3                     = 0x027F88A8,
 149         .read_idle_ctrl                 = 0x00050000,
 150         .zq_config                      = 0x0007190B,
 151         .temp_alert_config              = 0x00000000,
 152         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 153         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 154         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 155         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 156         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 157         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 158         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 159         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 160         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 161         .emif_rd_wr_lvl_ctl             = 0x00000000,
 162         .emif_rd_wr_exec_thresh         = 0x00000305
 163 };
 164
 165 const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 166         .sdram_config_init              = 0x61851B32,
 167         .sdram_config                   = 0x61851B32,
 168         .sdram_config2                  = 0x08000000,
 169         .ref_ctrl                       = 0x000040F1,
 170         .ref_ctrl_final                 = 0x00001035,
 171         .sdram_tim1                     = 0xCCCF36B3,
 172         .sdram_tim2                     = 0x308F7FDA,
 173         .sdram_tim3                     = 0x027F88A8,
 174         .read_idle_ctrl                 = 0x00050000,
 175         .zq_config                      = 0x0007190B,
 176         .temp_alert_config              = 0x00000000,
 177         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 178         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 179         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 180         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 181         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 182         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 183         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 184         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 185         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 186         .emif_rd_wr_lvl_ctl             = 0x00000000,
 187         .emif_rd_wr_exec_thresh         = 0x00000305
 188 };
 189
 190 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 191         .sdram_config_init              = 0x61862B32,
 192         .sdram_config                   = 0x61862B32,
 193         .sdram_config2                  = 0x08000000,
 194         .ref_ctrl                       = 0x0000514C,
 195         .ref_ctrl_final                 = 0x0000144A,
 196         .sdram_tim1                     = 0xD113781C,
 197         .sdram_tim2                     = 0x305A7FDA,
 198         .sdram_tim3                     = 0x409F86A8,
 199         .read_idle_ctrl                 = 0x00050000,
 200         .zq_config                      = 0x5007190B,
 201         .temp_alert_config              = 0x00000000,
 202         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 203         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 204         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 205         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 206         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 207         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 208         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 209         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 210         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 211         .emif_rd_wr_lvl_ctl             = 0x00000000,
 212         .emif_rd_wr_exec_thresh         = 0x00000305
 213 };
 214
 215 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 216         .dmm_lisa_map_0 = 0x0,
 217         .dmm_lisa_map_1 = 0x0,
 218         .dmm_lisa_map_2 = 0x80740300,
 219         .dmm_lisa_map_3 = 0xFF020100,
 220         .is_ma_present  = 0x1
 221 };
 222
 223 /*
 224  * DRA752 EVM board has 1.5 GB of memory
 225  * EMIF1 --> 2Gb * 2 =  512MB
 226  * EMIF2 --> 2Gb * 4 =  1GB
 227  * so mapping 1GB interleaved and 512MB non-interleaved
 228  */
 229 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
 230         .dmm_lisa_map_0 = 0x0,
 231         .dmm_lisa_map_1 = 0x80640300,
 232         .dmm_lisa_map_2 = 0xC0500220,
 233         .dmm_lisa_map_3 = 0xFF020100,
 234         .is_ma_present  = 0x1
 235 };
 236
 237 /*
 238  * DRA752 EVM EMIF1 ONLY CONFIGURATION
 239  */
 240 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 241         .dmm_lisa_map_0 = 0x0,
 242         .dmm_lisa_map_1 = 0x0,
 243         .dmm_lisa_map_2 = 0x80500100,
 244         .dmm_lisa_map_3 = 0xFF020100,
 245         .is_ma_present  = 0x1
 246 };
 247
 248 /*
 249  * DRA752 EVM EMIF2 ONLY CONFIGURATION
 250  */
 251 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 252         .dmm_lisa_map_0 = 0x0,
 253         .dmm_lisa_map_1 = 0x0,
 254         .dmm_lisa_map_2 = 0x80600200,
 255         .dmm_lisa_map_3 = 0xFF020100,
 256         .is_ma_present  = 0x1
 257 };
 258
 259 /*
 260  * DRA722 EVM EMIF1 CONFIGURATION
 261  */
 262 const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 263         .dmm_lisa_map_0 = 0x0,
 264         .dmm_lisa_map_1 = 0x0,
 265         .dmm_lisa_map_2 = 0x80600100,
 266         .dmm_lisa_map_3 = 0xFF020100,
 267         .is_ma_present  = 0x1
 268 };
 269
 270 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 271 {
 272         switch (omap_revision()) {
 273         case OMAP5430_ES1_0:
 274                 *regs = &emif_regs_532_mhz_2cs;
 275                 break;
 276         case OMAP5432_ES1_0:
 277                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 278                 break;
 279         case OMAP5430_ES2_0:
 280                 *regs = &emif_regs_532_mhz_2cs_es2;
 281                 break;
 282         case OMAP5432_ES2_0:
 283                 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 284                 break;
 285         case DRA752_ES1_0:
 286         case DRA752_ES1_1:
 287         case DRA752_ES2_0:
 288                 switch (emif_nr) {
 289                 case 1:
 290                         *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 291                         break;
 292                 case 2:
 293                         *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
 294                         break;
 295                 }
 296                 break;
 297         case DRA722_ES1_0:
 298                 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 299                 break;
 300         default:
 301                 *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 302         }
 303 }
 304
 305 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 306         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 307
 308 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 309                                                 **dmm_lisa_regs)
 310 {
 311         switch (omap_revision()) {
 312         case OMAP5430_ES1_0:
 313         case OMAP5430_ES2_0:
 314         case OMAP5432_ES1_0:
 315         case OMAP5432_ES2_0:
 316                 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 317                 break;
 318         case DRA752_ES1_0:
 319         case DRA752_ES1_1:
 320         case DRA752_ES2_0:
 321                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 322                 break;
 323         case DRA722_ES1_0:
 324         default:
 325                 *dmm_lisa_regs = &lisa_map_2G_x_2;
 326         }
 327
 328 }
 329
 330 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 331         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 332 #else
 333
 334 static const struct lpddr2_device_details dev_4G_S4_details = {
 335         .type           = LPDDR2_TYPE_S4,
 336         .density        = LPDDR2_DENSITY_4Gb,
 337         .io_width       = LPDDR2_IO_WIDTH_32,
 338         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 339 };
 340
 341 static void emif_get_device_details_sdp(u32 emif_nr,
 342                 struct lpddr2_device_details *cs0_device_details,
 343                 struct lpddr2_device_details *cs1_device_details)
 344 {
 345         /* EMIF1 & EMIF2 have identical configuration */
 346         *cs0_device_details = dev_4G_S4_details;
 347         *cs1_device_details = dev_4G_S4_details;
 348 }
 349
 350 void emif_get_device_details(u32 emif_nr,
 351                 struct lpddr2_device_details *cs0_device_details,
 352                 struct lpddr2_device_details *cs1_device_details)
 353         __attribute__((weak, alias("emif_get_device_details_sdp")));
 354
 355 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 356
 357 const u32 ext_phy_ctrl_const_base[] = {
 358         0x01004010,
 359         0x00001004,
 360         0x04010040,
 361         0x01004010,
 362         0x00001004,
 363         0x00000000,
 364         0x00000000,
 365         0x00000000,
 366         0x80080080,
 367         0x00800800,
 368         0x08102040,
 369         0x00000001,
 370         0x540A8150,
 371         0xA81502a0,
 372         0x002A0540,
 373         0x00000000,
 374         0x00000000,
 375         0x00000000,
 376         0x00000077,
 377         0x0
 378 };
 379
 380 const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
 381         0x01004010,
 382         0x00001004,
 383         0x04010040,
 384         0x01004010,
 385         0x00001004,
 386         0x00000000,
 387         0x00000000,
 388         0x00000000,
 389         0x80080080,
 390         0x00800800,
 391         0x08102040,
 392         0x00000002,
 393         0x0,
 394         0x0,
 395         0x0,
 396         0x00000000,
 397         0x00000000,
 398         0x00000000,
 399         0x00000057,
 400         0x0
 401 };
 402
 403 const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 404         0x50D4350D,
 405         0x00000D43,
 406         0x04010040,
 407         0x01004010,
 408         0x00001004,
 409         0x00000000,
 410         0x00000000,
 411         0x00000000,
 412         0x80080080,
 413         0x00800800,
 414         0x08102040,
 415         0x00000002,
 416         0x00000000,
 417         0x00000000,
 418         0x00000000,
 419         0x00000000,
 420         0x00000000,
 421         0x00000000,
 422         0x00000057,
 423         0x0
 424 };
 425
 426 /* Ext phy ctrl 1-35 regs */
 427 const u32
 428 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 429         0x10040100,
 430         0x00910091,
 431         0x00950095,
 432         0x009B009B,
 433         0x009E009E,
 434         0x00980098,
 435         0x00340034,
 436         0x00350035,
 437         0x00340034,
 438         0x00310031,
 439         0x00340034,
 440         0x007F007F,
 441         0x007F007F,
 442         0x007F007F,
 443         0x007F007F,
 444         0x007F007F,
 445         0x00480048,
 446         0x004A004A,
 447         0x00520052,
 448         0x00550055,
 449         0x00500050,
 450         0x00000000,
 451         0x00600020,
 452         0x40011080,
 453         0x08102040,
 454         0x0,
 455         0x0,
 456         0x0,
 457         0x0,
 458         0x0,
 459         0x0,
 460         0x0,
 461         0x0,
 462         0x0,
 463         0x0
 464 };
 465
 466 /* Ext phy ctrl 1-35 regs */
 467 const u32
 468 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
 469         0x10040100,
 470         0x00910091,
 471         0x00950095,
 472         0x009B009B,
 473         0x009E009E,
 474         0x00980098,
 475         0x00330033,
 476         0x00330033,
 477         0x002F002F,
 478         0x00320032,
 479         0x00310031,
 480         0x007F007F,
 481         0x007F007F,
 482         0x007F007F,
 483         0x007F007F,
 484         0x007F007F,
 485         0x00520052,
 486         0x00520052,
 487         0x00470047,
 488         0x00490049,
 489         0x00500050,
 490         0x00000000,
 491         0x00600020,
 492         0x40011080,
 493         0x08102040,
 494         0x0,
 495         0x0,
 496         0x0,
 497         0x0,
 498         0x0,
 499         0x0,
 500         0x0,
 501         0x0,
 502         0x0,
 503         0x0
 504 };
 505
 506 /* Ext phy ctrl 1-35 regs */
 507 const u32
 508 dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
 509         0x10040100,
 510         0x00A400A4,
 511         0x00A900A9,
 512         0x00B000B0,
 513         0x00B000B0,
 514         0x00A400A4,
 515         0x00390039,
 516         0x00320032,
 517         0x00320032,
 518         0x00320032,
 519         0x00440044,
 520         0x00550055,
 521         0x00550055,
 522         0x00550055,
 523         0x00550055,
 524         0x007F007F,
 525         0x004D004D,
 526         0x00430043,
 527         0x00560056,
 528         0x00540054,
 529         0x00600060,
 530         0x0,
 531         0x00600020,
 532         0x40010080,
 533         0x08102040,
 534         0x0,
 535         0x0,
 536         0x0,
 537         0x0,
 538         0x0,
 539         0x0,
 540         0x0,
 541         0x0,
 542         0x0,
 543         0x0
 544 };
 545
 546 const struct lpddr2_mr_regs mr_regs = {
 547         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 548         .mr2    = 0x6,
 549         .mr3    = 0x1,
 550         .mr10   = MR10_ZQ_ZQINIT,
 551         .mr16   = MR16_REF_FULL_ARRAY
 552 };
 553
 554 void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 555                                              const u32 **regs,
 556                                              u32 *size)
 557 {
 558         switch (omap_revision()) {
 559         case OMAP5430_ES1_0:
 560         case OMAP5430_ES2_0:
 561                 *regs = ext_phy_ctrl_const_base;
 562                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
 563                 break;
 564         case OMAP5432_ES1_0:
 565                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 566                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
 567                 break;
 568         case OMAP5432_ES2_0:
 569                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 570                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 571                 break;
 572         case DRA752_ES1_0:
 573         case DRA752_ES1_1:
 574         case DRA752_ES2_0:
 575                 if (emif_nr == 1) {
 576                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 577                         *size =
 578                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
 579                 } else {
 580                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
 581                         *size =
 582                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
 583                 }
 584                 break;
 585         case DRA722_ES1_0:
 586                 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
 587                 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 588                 break;
 589         default:
 590                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 591                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 592
 593         }
 594 }
 595
 596 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 597 {
 598         *regs = &mr_regs;
 599 }
 600
 601 static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
 602 {
 603         u32 *ext_phy_ctrl_base = 0;
 604         u32 *emif_ext_phy_ctrl_base = 0;
 605         u32 emif_nr;
 606         const u32 *ext_phy_ctrl_const_regs;
 607         u32 i = 0;
 608         u32 size;
 609
 610         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 611
 612         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 613
 614         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 615         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 616
 617         /* Configure external phy control timing registers */
 618         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 619                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 620                 /* Update shadow registers */
 621                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 622         }
 623
 624         /*
 625          * external phy 6-24 registers do not change with
 626          * ddr frequency
 627          */
 628         emif_get_ext_phy_ctrl_const_regs(emif_nr,
 629                                          &ext_phy_ctrl_const_regs, &size);
 630
 631         for (i = 0; i < size; i++) {
 632                 writel(ext_phy_ctrl_const_regs[i],
 633                        emif_ext_phy_ctrl_base++);
 634                 /* Update shadow registers */
 635                 writel(ext_phy_ctrl_const_regs[i],
 636                        emif_ext_phy_ctrl_base++);
 637         }
 638 }
 639
 640 static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
 641 {
 642         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 643         u32 *emif_ext_phy_ctrl_base = 0;
 644         u32 emif_nr;
 645         const u32 *ext_phy_ctrl_const_regs;
 646         u32 i, hw_leveling, size;
 647
 648         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 649
 650         hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
 651
 652         emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
 653
 654         emif_get_ext_phy_ctrl_const_regs(emif_nr,
 655                                          &ext_phy_ctrl_const_regs, &size);
 656
 657         writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
 658         writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
 659
 660         if (!hw_leveling) {
 661                 /*
 662                  * Copy the predefined PHY register values
 663                  * in case of sw leveling
 664                  */
 665                 for (i = 1; i < 25; i++) {
 666                         writel(ext_phy_ctrl_const_regs[i],
 667                                &emif_ext_phy_ctrl_base[i * 2]);
 668                         writel(ext_phy_ctrl_const_regs[i],
 669                                &emif_ext_phy_ctrl_base[i * 2 + 1]);
 670                 }
 671         } else {
 672                 /*
 673                  * Write the init value for HW levling to occur
 674                  */
 675                 for (i = 21; i < 35; i++) {
 676                         writel(ext_phy_ctrl_const_regs[i],
 677                                &emif_ext_phy_ctrl_base[i * 2]);
 678                         writel(ext_phy_ctrl_const_regs[i],
 679                                &emif_ext_phy_ctrl_base[i * 2 + 1]);
 680                 }
 681         }
 682 }
 683
 684 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 685 {
 686         if (is_omap54xx())
 687                 do_ext_phy_settings_omap5(base, regs);
 688         else
 689                 do_ext_phy_settings_dra7(base, regs);
 690 }
 691
 692 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 693 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 694         .max_freq       = 532000000,
 695         .RL             = 8,
 696         .tRPab          = 21,
 697         .tRCD           = 18,
 698         .tWR            = 15,
 699         .tRASmin        = 42,
 700         .tRRD           = 10,
 701         .tWTRx2         = 15,
 702         .tXSR           = 140,
 703         .tXPx2          = 15,
 704         .tRFCab         = 130,
 705         .tRTPx2         = 15,
 706         .tCKE           = 3,
 707         .tCKESR         = 15,
 708         .tZQCS          = 90,
 709         .tZQCL          = 360,
 710         .tZQINIT        = 1000,
 711         .tDQSCKMAXx2    = 11,
 712         .tRASmax        = 70,
 713         .tFAW           = 50
 714 };
 715
 716 static const struct lpddr2_min_tck min_tck = {
 717         .tRL            = 3,
 718         .tRP_AB         = 3,
 719         .tRCD           = 3,
 720         .tWR            = 3,
 721         .tRAS_MIN       = 3,
 722         .tRRD           = 2,
 723         .tWTR           = 2,
 724         .tXP            = 2,
 725         .tRTP           = 2,
 726         .tCKE           = 3,
 727         .tCKESR         = 3,
 728         .tFAW           = 8
 729 };
 730
 731 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 732         &timings_jedec_532_mhz
 733 };
 734
 735 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 736         .ac_timings     = ac_timings,
 737         .min_tck        = &min_tck,
 738 };
 739
 740 /*
 741  * List of status registers to be controlled back to control registers
 742  * after initial leveling
 743  * readreg, writereg
 744  */
 745 const struct read_write_regs omap5_bug_00339_regs[] = {
 746         { 8,  5 },
 747         { 9,  6 },
 748         { 10, 7 },
 749         { 14, 8 },
 750         { 15, 9 },
 751         { 16, 10 },
 752         { 11, 2 },
 753         { 12, 3 },
 754         { 13, 4 },
 755         { 17, 11 },
 756         { 18, 12 },
 757         { 19, 13 },
 758 };
 759
 760 const struct read_write_regs dra_bug_00339_regs[] = {
 761         { 7,  7 },
 762         { 8,  8 },
 763         { 9,  9 },
 764         { 10, 10 },
 765         { 11, 11 },
 766         { 12, 2 },
 767         { 13, 3 },
 768         { 14, 4 },
 769         { 15, 5 },
 770         { 16, 6 },
 771         { 17, 12 },
 772         { 18, 13 },
 773         { 19, 14 },
 774         { 20, 15 },
 775         { 21, 16 },
 776         { 22, 17 },
 777         { 23, 18 },
 778         { 24, 19 },
 779         { 25, 20 },
 780         { 26, 21}
 781 };
 782
 783 const struct read_write_regs *get_bug_regs(u32 *iterations)
 784 {
 785         const struct read_write_regs *bug_00339_regs_ptr = NULL;
 786
 787         switch (omap_revision()) {
 788         case OMAP5430_ES1_0:
 789         case OMAP5430_ES2_0:
 790         case OMAP5432_ES1_0:
 791         case OMAP5432_ES2_0:
 792                 bug_00339_regs_ptr = omap5_bug_00339_regs;
 793                 *iterations = sizeof(omap5_bug_00339_regs)/
 794                              sizeof(omap5_bug_00339_regs[0]);
 795                 break;
 796         case DRA752_ES1_0:
 797         case DRA752_ES1_1:
 798         case DRA752_ES2_0:
 799         case DRA722_ES1_0:
 800                 bug_00339_regs_ptr = dra_bug_00339_regs;
 801                 *iterations = sizeof(dra_bug_00339_regs)/
 802                              sizeof(dra_bug_00339_regs[0]);
 803                 break;
 804         default:
 805                 printf("\n Error: UnKnown SOC");
 806         }
 807
 808         return bug_00339_regs_ptr;
 809 }
 810
 811 void emif_get_device_timings_sdp(u32 emif_nr,
 812                 const struct lpddr2_device_timings **cs0_device_timings,
 813                 const struct lpddr2_device_timings **cs1_device_timings)
 814 {
 815         /* Identical devices on EMIF1 & EMIF2 */
 816         *cs0_device_timings = &dev_4G_S4_timings;
 817         *cs1_device_timings = &dev_4G_S4_timings;
 818 }
 819
 820 void emif_get_device_timings(u32 emif_nr,
 821                 const struct lpddr2_device_timings **cs0_device_timings,
 822                 const struct lpddr2_device_timings **cs1_device_timings)
 823         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 824
 825 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */