arch/arm/cpu/armv7/socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/u-boot.h>
  10 #include <asm/utils.h>
  11 #include <version.h>
  12 #include <image.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <spl.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/freeze_controller.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 u32 spl_boot_device(void)
  23 {
  24         return BOOT_DEVICE_RAM;
  25 }
  26
  27 /*
  28  * Board initialization after bss clearance
  29  */
  30 void spl_board_init(void)
  31 {
  32 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  33         cm_config_t cm_default_cfg = {
  34                 /* main group */
  35                 MAIN_VCO_BASE,
  36                 CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
  37                         CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
  38                 CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
  39                         CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
  40                 CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
  41                         CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
  42                 CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
  43                         CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
  44                 CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
  45                         CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
  46                 CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
  47                         CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
  48                 CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
  49                         CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
  50                 CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
  51                         CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
  52                 CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
  53                         CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
  54                 CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
  55                         CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
  56                 CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
  57                         CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
  58                 CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
  59                         CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
  60                 CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
  61                         CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
  62                 CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
  63                         CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
  64                 CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
  65                         CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
  66
  67                 /* peripheral group */
  68                 PERI_VCO_BASE,
  69                 CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
  70                         CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
  71                 CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
  72                         CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
  73                 CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
  74                         CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
  75                 CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
  76                         CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
  77                 CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
  78                         CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
  79                 CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
  80                         CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
  81                 CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
  82                         CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
  83                 CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
  84                         CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
  85                 CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
  86                         CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
  87                 CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
  88                         CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
  89                 CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
  90                         CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
  91                 CLKMGR_PERPLLGRP_SRC_QSPI_SET(
  92                         CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
  93                 CLKMGR_PERPLLGRP_SRC_NAND_SET(
  94                         CONFIG_HPS_PERPLLGRP_SRC_NAND) |
  95                 CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
  96                         CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
  97
  98                 /* sdram pll group */
  99                 SDR_VCO_BASE,
 100                 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
 101                         CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
 102                 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
 103                         CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
 104                 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
 105                         CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
 106                 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
 107                         CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
 108                 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
 109                         CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
 110                 CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
 111                         CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
 112                 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
 113                         CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
 114                 CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
 115                         CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
 116         };
 117
 118         debug("Freezing all I/O banks\n");
 119         /* freeze all IO banks */
 120         sys_mgr_frzctrl_freeze_req();
 121
 122         debug("Reconfigure Clock Manager\n");
 123         /* reconfigure the PLLs */
 124         cm_basic_init(&cm_default_cfg);
 125
 126         /* configure the IOCSR / IO buffer settings */
 127         if (scan_mgr_configure_iocsr())
 128                 hang();
 129
 130         /* configure the pin muxing through system manager */
 131         sysmgr_pinmux_init();
 132 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 133
 134         /* de-assert reset for peripherals and bridges based on handoff */
 135         reset_deassert_peripherals_handoff();
 136
 137         debug("Unfreezing/Thaw all I/O banks\n");
 138         /* unfreeze / thaw all IO banks */
 139         sys_mgr_frzctrl_thaw_req();
 140
 141         /* enable console uart printing */
 142         preloader_console_init();
 143 }