2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
35 #include <asm/system.h>
36 #include <linux/linkage.h>
40 ldr pc, _undefined_instruction
41 ldr pc, _software_interrupt
42 ldr pc, _prefetch_abort
47 #ifdef CONFIG_SPL_BUILD
48 _undefined_instruction: .word _undefined_instruction
49 _software_interrupt: .word _software_interrupt
50 _prefetch_abort: .word _prefetch_abort
51 _data_abort: .word _data_abort
52 _not_used: .word _not_used
55 _pad: .word 0x12345678 /* now 16*4=64 */
57 _undefined_instruction: .word undefined_instruction
58 _software_interrupt: .word software_interrupt
59 _prefetch_abort: .word prefetch_abort
60 _data_abort: .word data_abort
61 _not_used: .word not_used
64 _pad: .word 0x12345678 /* now 16*4=64 */
65 #endif /* CONFIG_SPL_BUILD */
70 .balignl 16,0xdeadbeef
71 /*************************************************************************
73 * Startup Code (reset vector)
75 * do important init only if we don't start from memory!
76 * setup Memory and board specific bits prior to relocation.
77 * relocate armboot to ram
80 *************************************************************************/
84 #ifndef CONFIG_SPL_BUILD
85 .word CONFIG_SYS_TEXT_BASE
87 .word CONFIG_SPL_TEXT_BASE
91 * These are defined in the board-specific linker script.
95 .word __bss_start - _start
97 .global _image_copy_end_ofs
99 .word __image_copy_end - _start
103 .word __bss_end__ - _start
109 #ifdef CONFIG_USE_IRQ
110 /* IRQ stack memory (calculated at run-time) */
111 .globl IRQ_STACK_START
115 /* IRQ stack memory (calculated at run-time) */
116 .globl FIQ_STACK_START
121 /* IRQ stack memory (calculated at run-time) + 8 bytes */
122 .globl IRQ_STACK_START_IN
127 * the actual reset code
133 * set the cpu to SVC32 mode
140 #if !defined(CONFIG_TEGRA2)
143 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
144 * Continue to use ROM code vector only in OMAP4 spl)
146 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
147 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
148 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
149 bic r0, #CR_V @ V = 0
150 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
152 /* Set vector address in CP15 VBAR register */
154 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
158 /* the mask ROM code should have PLL and others stable */
159 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
164 /* Set stackpointer in internal RAM to call board_init_f */
166 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
167 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
171 /*------------------------------------------------------------------------------*/
174 * void relocate_code (addr_sp, gd, addr_moni)
176 * This "function" does not return, instead it continues in RAM
177 * after relocating the monitor code.
181 mov r4, r0 /* save addr_sp */
182 mov r5, r1 /* save addr of gd */
183 mov r6, r2 /* save addr of destination */
185 /* Set up the stack */
191 beq clear_bss /* skip relocation */
192 mov r1, r6 /* r1 <- scratch for copy_loop */
193 ldr r3, _image_copy_end_ofs
194 add r2, r0, r3 /* r2 <- source end address */
197 ldmia r0!, {r9-r10} /* copy from source address [r0] */
198 stmia r1!, {r9-r10} /* copy to target address [r1] */
199 cmp r0, r2 /* until source end address [r2] */
202 #ifndef CONFIG_SPL_BUILD
204 * fix .rel.dyn relocations
206 adr r0, _start /* r0 <- beginning of code */
207 sub r9, r6, r0 /* r9 <- relocation offset */
208 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
209 add r10, r10, r0 /* r10 <- sym table in FLASH */
210 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
211 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
212 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
213 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
215 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
216 add r0, r0, r9 /* r0 <- location to fix up in RAM */
219 cmp r7, #23 /* relative fixup? */
221 cmp r7, #2 /* absolute fixup? */
223 /* ignore unknown type of fixup */
226 /* absolute fix: set location to (offset) symbol value */
227 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
228 add r1, r10, r1 /* r1 <- address of symbol in table */
229 ldr r1, [r1, #4] /* r1 <- symbol value */
230 add r1, r1, r9 /* r1 <- relocated sym addr */
233 /* relative fix: increase location by offset */
238 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
243 .word __rel_dyn_start - _start
245 .word __rel_dyn_end - _start
247 .word __dynsym_start - _start
249 #endif /* #ifndef CONFIG_SPL_BUILD */
252 #ifdef CONFIG_SPL_BUILD
253 /* No relocation for SPL */
257 ldr r0, _bss_start_ofs
259 mov r4, r6 /* reloc addr */
263 mov r2, #0x00000000 /* clear */
266 cmp r0, r1 /* clear loop... */
267 bhs clbss_e /* if reached end of bss, exit */
274 * We are done. Do not return, instead branch to second part of board
275 * initialization, now running from RAM.
279 * If I-cache is enabled invalidate it
281 #ifndef CONFIG_SYS_ICACHE_OFF
282 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
283 mcr p15, 0, r0, c7, c10, 4 @ DSB
284 mcr p15, 0, r0, c7, c5, 4 @ ISB
286 ldr r0, _board_init_r_ofs
290 /* setup parameters for board_init_r */
291 mov r0, r5 /* gd_t */
292 mov r1, r6 /* dest_addr */
297 .word board_init_r - _start
298 ENDPROC(relocate_code)
300 /*************************************************************************
304 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
305 * CONFIG_SYS_ICACHE_OFF is defined.
307 *************************************************************************/
312 mov r0, #0 @ set up for MCR
313 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
314 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
315 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
316 mcr p15, 0, r0, c7, c10, 4 @ DSB
317 mcr p15, 0, r0, c7, c5, 4 @ ISB
320 * disable MMU stuff and caches
322 mrc p15, 0, r0, c1, c0, 0
323 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
324 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
325 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
326 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
327 #ifdef CONFIG_SYS_ICACHE_OFF
328 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
330 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
332 mcr p15, 0, r0, c1, c0, 0
333 mov pc, lr @ back to my caller
334 ENDPROC(cpu_init_cp15)
336 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
337 /*************************************************************************
339 * CPU_init_critical registers
341 * setup important registers
342 * setup memory timing
344 *************************************************************************/
347 * Jump to board specific initialization...
348 * The Mask ROM will have already initialized
349 * basic memory. Go here to bump up clock rate and handle
350 * wake up conditions.
352 mov ip, lr @ preserve link reg across call
353 bl lowlevel_init @ go setup pll,mux,memory
354 mov lr, ip @ restore link
355 mov pc, lr @ back to my caller
356 ENDPROC(cpu_init_crit)
359 #ifndef CONFIG_SPL_BUILD
361 *************************************************************************
365 *************************************************************************
370 #define S_FRAME_SIZE 72
392 #define MODE_SVC 0x13
396 * use bad_save_user_regs for abort/prefetch/undef/swi ...
397 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
400 .macro bad_save_user_regs
401 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
403 stmia sp, {r0 - r12} @ Save user registers (now in
405 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
407 ldmia r2, {r2 - r3} @ get values for "aborted" pc
408 @ and cpsr (into parm regs)
409 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
413 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
414 mov r0, sp @ save current stack into r0
418 .macro irq_save_user_regs
419 sub sp, sp, #S_FRAME_SIZE
420 stmia sp, {r0 - r12} @ Calling r0-r12
421 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
422 @ a reserved stack spot would
424 stmdb r8, {sp, lr}^ @ Calling SP, LR
425 str lr, [r8, #0] @ Save calling PC
427 str r6, [r8, #4] @ Save CPSR
428 str r0, [r8, #8] @ Save OLD_R0
432 .macro irq_restore_user_regs
433 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
435 ldr lr, [sp, #S_PC] @ Get PC
436 add sp, sp, #S_FRAME_SIZE
437 subs pc, lr, #4 @ return & move spsr_svc into
442 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
445 str lr, [r13] @ save caller lr in position 0
447 mrs lr, spsr @ get the spsr
448 str lr, [r13, #4] @ save spsr in position 1 of
451 mov r13, #MODE_SVC @ prepare SVC-Mode
453 msr spsr, r13 @ switch modes, make sure
455 mov lr, pc @ capture return pc
456 movs pc, lr @ jump to next instruction &
460 .macro get_bad_stack_swi
461 sub r13, r13, #4 @ space on current stack for
463 str r0, [r13] @ save R0's value.
464 ldr r0, IRQ_STACK_START_IN @ get data regions start
465 @ spots for abort stack
466 str lr, [r0] @ save caller lr in position 0
468 mrs r0, spsr @ get the spsr
469 str lr, [r0, #4] @ save spsr in position 1 of
471 ldr r0, [r13] @ restore r0
472 add r13, r13, #4 @ pop stack entry
475 .macro get_irq_stack @ setup IRQ stack
476 ldr sp, IRQ_STACK_START
479 .macro get_fiq_stack @ setup FIQ stack
480 ldr sp, FIQ_STACK_START
487 undefined_instruction:
490 bl do_undefined_instruction
496 bl do_software_interrupt
516 #ifdef CONFIG_USE_IRQ
523 irq_restore_user_regs
528 /* someone ought to write a more effective fiq_save_user_regs */
531 irq_restore_user_regs
547 #endif /* CONFIG_USE_IRQ */
548 #endif /* CONFIG_SPL_BUILD */