arch/arm/cpu/armv7/stv0991/clock.c

   1 /*
   2  * (C) Copyright 2014
   3  * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/io.h>
   9 #include <asm/arch/hardware.h>
  10 #include <asm/arch/stv0991_cgu.h>
  11 #include<asm/arch/stv0991_periph.h>
  12
  13 static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
  14                                 (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
  15
  16 void enable_pll1(void)
  17 {
  18         /* pll1 already configured for 1000Mhz, just need to enable it */
  19         writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
  20                         &stv0991_cgu_regs->pll1_ctrl);
  21 }
  22
  23 void clock_setup(int peripheral)
  24 {
  25         switch (peripheral) {
  26         case UART_CLOCK_CFG:
  27                 writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
  28                 break;
  29         case ETH_CLOCK_CFG:
  30                 enable_pll1();
  31                 writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
  32
  33                 /* Clock selection for ethernet tx_clk & rx_clk*/
  34                 writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
  35                                 | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
  36                 break;
  37         case QSPI_CLOCK_CFG:
  38                 writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq);
  39                 break;
  40         default:
  41                 break;
  42         }
  43 }