2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/sbc-regs.h>
11 #include <asm/arch/sg-regs.h>
15 #if !defined(CONFIG_SPL_BUILD)
17 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
18 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
19 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
20 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
22 /* XECS1 : boot memory (always boot swap = on) */
23 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
24 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
25 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
26 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
28 /* XECS4 : sub memory */
29 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
30 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
31 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
32 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
34 /* XECS5 : peripherals */
35 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
36 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
37 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
38 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
40 /* base address regsiters */
41 writel(0x0000bc01, SBBASE0); /* boot memory */
42 writel(0x0900bfff, SBBASE1); /* dummy */
43 writel(0x0400bc01, SBBASE4); /* sub memory */
44 writel(0x0800bf01, SBBASE5); /* peripherals */
46 sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
47 sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
49 /* dummy read to assure write process */
50 readl(SG_PINCTRL(33));