arch/arm/cpu/armv7/zynq/clk.c

   1 /*
   2  * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
   3  * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <clk.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/hardware.h>
  12 #include <asm/arch/clk.h>
  13
  14 /* Board oscillator frequency */
  15 #ifndef CONFIG_ZYNQ_PS_CLK_FREQ
  16 # define CONFIG_ZYNQ_PS_CLK_FREQ        33333333UL
  17 #endif
  18
  19 /* Register bitfield defines */
  20 #define PLLCTRL_FBDIV_MASK      0x7f000
  21 #define PLLCTRL_FBDIV_SHIFT     12
  22 #define PLLCTRL_BPFORCE_MASK    (1 << 4)
  23 #define PLLCTRL_PWRDWN_MASK     2
  24 #define PLLCTRL_PWRDWN_SHIFT    1
  25 #define PLLCTRL_RESET_MASK      1
  26 #define PLLCTRL_RESET_SHIFT     0
  27
  28 #define ZYNQ_CLK_MAXDIV         0x3f
  29 #define CLK_CTRL_DIV1_SHIFT     20
  30 #define CLK_CTRL_DIV1_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  31 #define CLK_CTRL_DIV0_SHIFT     8
  32 #define CLK_CTRL_DIV0_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
  33 #define CLK_CTRL_SRCSEL_SHIFT   4
  34 #define CLK_CTRL_SRCSEL_MASK    (0x3 << CLK_CTRL_SRCSEL_SHIFT)
  35
  36 #define CLK_CTRL_DIV2X_SHIFT    26
  37 #define CLK_CTRL_DIV2X_MASK     (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
  38 #define CLK_CTRL_DIV3X_SHIFT    20
  39 #define CLK_CTRL_DIV3X_MASK     (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
  40
  41 #define ZYNQ_CLKMUX_SEL_0       0
  42 #define ZYNQ_CLKMUX_SEL_1       1
  43 #define ZYNQ_CLKMUX_SEL_2       2
  44 #define ZYNQ_CLKMUX_SEL_3       3
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 struct clk;
  49
  50 /**
  51  * struct clk_ops:
  52  * @set_rate:   Function pointer to set_rate() implementation
  53  * @get_rate:   Function pointer to get_rate() implementation
  54  */
  55 struct clk_ops {
  56         int (*set_rate)(struct clk *clk, unsigned long rate);
  57         unsigned long (*get_rate)(struct clk *clk);
  58 };
  59
  60 /**
  61  * struct clk:
  62  * @name:       Clock name
  63  * @frequency:  Currenct frequency
  64  * @parent:     Parent clock
  65  * @flags:      Clock flags
  66  * @reg:        Clock control register
  67  * @ops:        Clock operations
  68  */
  69 struct clk {
  70         char            *name;
  71         unsigned long   frequency;
  72         enum zynq_clk   parent;
  73         unsigned int    flags;
  74         u32             *reg;
  75         struct clk_ops  ops;
  76 };
  77 #define ZYNQ_CLK_FLAGS_HAS_2_DIVS       1
  78
  79 static struct clk clks[clk_max];
  80
  81 /**
  82  * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
  83  * @srcsel:     Mux select value
  84  * Returns the clock identifier associated with the selected mux input.
  85  */
  86 static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
  87 {
  88         unsigned int ret;
  89
  90         switch (srcsel) {
  91         case ZYNQ_CLKMUX_SEL_0:
  92         case ZYNQ_CLKMUX_SEL_1:
  93                 ret = armpll_clk;
  94                 break;
  95         case ZYNQ_CLKMUX_SEL_2:
  96                 ret = ddrpll_clk;
  97                 break;
  98         case ZYNQ_CLKMUX_SEL_3:
  99                 ret = iopll_clk;
 100                 break;
 101         default:
 102                 ret = armpll_clk;
 103                 break;
 104         }
 105
 106         return ret;
 107 }
 108
 109 /**
 110  * ddr2x_get_rate() - Get clock rate of DDR2x clock
 111  * @clk:        Clock handle
 112  * Returns the current clock rate of @clk.
 113  */
 114 static unsigned long ddr2x_get_rate(struct clk *clk)
 115 {
 116         u32 clk_ctrl = readl(clk->reg);
 117         u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
 118
 119         return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
 120 }
 121
 122 /**
 123  * ddr3x_get_rate() - Get clock rate of DDR3x clock
 124  * @clk:        Clock handle
 125  * Returns the current clock rate of @clk.
 126  */
 127 static unsigned long ddr3x_get_rate(struct clk *clk)
 128 {
 129         u32 clk_ctrl = readl(clk->reg);
 130         u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
 131
 132         return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
 133 }
 134
 135 static void init_ddr_clocks(void)
 136 {
 137         u32 div0, div1;
 138         unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
 139         u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
 140
 141         /* DDR2x */
 142         clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
 143         clks[ddr2x_clk].parent = ddrpll_clk;
 144         clks[ddr2x_clk].name = "ddr_2x";
 145         clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
 146         clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
 147
 148         /* DDR3x */
 149         clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
 150         clks[ddr3x_clk].parent = ddrpll_clk;
 151         clks[ddr3x_clk].name = "ddr_3x";
 152         clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
 153         clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
 154
 155         /* DCI */
 156         clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
 157         div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 158         div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 159         clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
 160         clks[dci_clk].parent = ddrpll_clk;
 161         clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
 162                         DIV_ROUND_CLOSEST(prate, div0), div1);
 163         clks[dci_clk].name = "dci";
 164
 165         gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
 166 }
 167
 168 static void init_cpu_clocks(void)
 169 {
 170         int clk_621;
 171         u32 reg, div, srcsel;
 172         enum zynq_clk parent;
 173
 174         reg = readl(&slcr_base->arm_clk_ctrl);
 175         clk_621 = readl(&slcr_base->clk_621_true) & 1;
 176         div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 177         srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 178         parent = __zynq_clk_cpu_get_parent(srcsel);
 179
 180         /* cpu clocks */
 181         clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
 182         clks[cpu_6or4x_clk].parent = parent;
 183         clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
 184                         zynq_clk_get_rate(parent), div);
 185         clks[cpu_6or4x_clk].name = "cpu_6or4x";
 186
 187         clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
 188         clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
 189         clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
 190         clks[cpu_3or2x_clk].name = "cpu_3or2x";
 191
 192         clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
 193         clks[cpu_2x_clk].parent = cpu_6or4x_clk;
 194         clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
 195                         (2 + clk_621);
 196         clks[cpu_2x_clk].name = "cpu_2x";
 197
 198         clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
 199         clks[cpu_1x_clk].parent = cpu_6or4x_clk;
 200         clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
 201                         (4 + 2 * clk_621);
 202         clks[cpu_1x_clk].name = "cpu_1x";
 203 }
 204
 205 /**
 206  * periph_calc_two_divs() - Calculate clock dividers
 207  * @cur_rate:   Current clock rate
 208  * @tgt_rate:   Target clock rate
 209  * @prate:      Parent clock rate
 210  * @div0:       First divider (output)
 211  * @div1:       Second divider (output)
 212  * Returns the actual clock rate possible.
 213  *
 214  * Calculates clock dividers for clocks with two 6-bit dividers.
 215  */
 216 static unsigned long periph_calc_two_divs(unsigned long cur_rate,
 217                 unsigned long tgt_rate, unsigned long prate, u32 *div0,
 218                 u32 *div1)
 219 {
 220         long err, best_err = (long)(~0UL >> 1);
 221         unsigned long rate, best_rate = 0;
 222         u32 d0, d1;
 223
 224         for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
 225                 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
 226                         rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
 227                                         d1);
 228                         err = abs(rate - tgt_rate);
 229
 230                         if (err < best_err) {
 231                                 *div0 = d0;
 232                                 *div1 = d1;
 233                                 best_err = err;
 234                                 best_rate = rate;
 235                         }
 236                 }
 237         }
 238
 239         return best_rate;
 240 }
 241
 242 /**
 243  * zynq_clk_periph_set_rate() - Set clock rate
 244  * @clk:        Handle of the peripheral clock
 245  * @rate:       New clock rate
 246  * Sets the clock frequency of @clk to @rate. Returns zero on success.
 247  */
 248 static int zynq_clk_periph_set_rate(struct clk *clk,
 249                 unsigned long rate)
 250 {
 251         u32 ctrl, div0 = 0, div1 = 0;
 252         unsigned long prate, new_rate, cur_rate = clk->frequency;
 253
 254         ctrl = readl(clk->reg);
 255         prate = zynq_clk_get_rate(clk->parent);
 256         ctrl &= ~CLK_CTRL_DIV0_MASK;
 257
 258         if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
 259                 ctrl &= ~CLK_CTRL_DIV1_MASK;
 260                 new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
 261                                 &div1);
 262                 ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
 263         } else {
 264                 div0 = DIV_ROUND_CLOSEST(prate, rate);
 265                 div0 &= ZYNQ_CLK_MAXDIV;
 266                 new_rate = DIV_ROUND_CLOSEST(rate, div0);
 267         }
 268
 269         /* write new divs to hardware */
 270         ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
 271         writel(ctrl, clk->reg);
 272
 273         /* update frequency in clk framework */
 274         clk->frequency = new_rate;
 275
 276         return 0;
 277 }
 278
 279 /**
 280  * zynq_clk_periph_get_rate() - Get clock rate
 281  * @clk:        Handle of the peripheral clock
 282  * Returns the current clock rate of @clk.
 283  */
 284 static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
 285 {
 286         u32 clk_ctrl = readl(clk->reg);
 287         u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 288         u32 div1 = 1;
 289
 290         if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
 291                 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 292
 293         /* a register value of zero == division by 1 */
 294         if (!div0)
 295                 div0 = 1;
 296         if (!div1)
 297                 div1 = 1;
 298
 299         return
 300                 DIV_ROUND_CLOSEST(
 301                         DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
 302                         div1);
 303 }
 304
 305 /**
 306  * __zynq_clk_periph_get_parent() - Decode clock multiplexer
 307  * @srcsel:     Mux select value
 308  * Returns the clock identifier associated with the selected mux input.
 309  */
 310 static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
 311 {
 312         switch (srcsel) {
 313         case ZYNQ_CLKMUX_SEL_0:
 314         case ZYNQ_CLKMUX_SEL_1:
 315                 return iopll_clk;
 316         case ZYNQ_CLKMUX_SEL_2:
 317                 return armpll_clk;
 318         case ZYNQ_CLKMUX_SEL_3:
 319                 return ddrpll_clk;
 320         default:
 321                 return 0;
 322         }
 323 }
 324
 325 /**
 326  * zynq_clk_periph_get_parent() - Decode clock multiplexer
 327  * @clk:        Clock handle
 328  * Returns the clock identifier associated with the selected mux input.
 329  */
 330 static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
 331 {
 332         u32 clk_ctrl = readl(clk->reg);
 333         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 334
 335         return __zynq_clk_periph_get_parent(srcsel);
 336 }
 337
 338 /**
 339  * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
 340  * @clk:        Pointer to struct clk for the clock
 341  * @ctrl:       Clock control register
 342  * @name:       PLL name
 343  * @two_divs:   Indicates whether the clock features one or two dividers
 344  */
 345 static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name,
 346                 bool two_divs)
 347 {
 348         clk->name = name;
 349         clk->reg = ctrl;
 350         if (two_divs)
 351                 clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
 352         clk->parent = zynq_clk_periph_get_parent(clk);
 353         clk->frequency = zynq_clk_periph_get_rate(clk);
 354         clk->ops.get_rate = zynq_clk_periph_get_rate;
 355         clk->ops.set_rate = zynq_clk_periph_set_rate;
 356
 357         return 0;
 358 }
 359
 360 static void init_periph_clocks(void)
 361 {
 362         zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl,
 363                                      "gem0", 1);
 364         zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl,
 365                                      "gem1", 1);
 366
 367         zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl,
 368                                      "smc", 0);
 369
 370         zynq_clk_register_periph_clk(&clks[lqspi_clk],
 371                                      &slcr_base->lqspi_clk_ctrl, "lqspi", 0);
 372
 373         zynq_clk_register_periph_clk(&clks[sdio0_clk],
 374                                      &slcr_base->sdio_clk_ctrl, "sdio0", 0);
 375         zynq_clk_register_periph_clk(&clks[sdio1_clk],
 376                                      &slcr_base->sdio_clk_ctrl, "sdio1", 0);
 377
 378         zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl,
 379                                      "spi0", 0);
 380         zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl,
 381                                      "spi1", 0);
 382
 383         zynq_clk_register_periph_clk(&clks[uart0_clk],
 384                                      &slcr_base->uart_clk_ctrl, "uart0", 0);
 385         zynq_clk_register_periph_clk(&clks[uart1_clk],
 386                                      &slcr_base->uart_clk_ctrl, "uart1", 0);
 387
 388         zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
 389                                      &slcr_base->dbg_clk_ctrl, "dbg_trc", 0);
 390         zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
 391                                      &slcr_base->dbg_clk_ctrl, "dbg_apb", 0);
 392
 393         zynq_clk_register_periph_clk(&clks[pcap_clk],
 394                                      &slcr_base->pcap_clk_ctrl, "pcap", 0);
 395
 396         zynq_clk_register_periph_clk(&clks[fclk0_clk],
 397                                      &slcr_base->fpga0_clk_ctrl, "fclk0", 1);
 398         zynq_clk_register_periph_clk(&clks[fclk1_clk],
 399                                      &slcr_base->fpga1_clk_ctrl, "fclk1", 1);
 400         zynq_clk_register_periph_clk(&clks[fclk2_clk],
 401                                      &slcr_base->fpga2_clk_ctrl, "fclk2", 1);
 402         zynq_clk_register_periph_clk(&clks[fclk3_clk],
 403                                      &slcr_base->fpga3_clk_ctrl, "fclk3", 1);
 404 }
 405
 406 /**
 407  * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
 408  * @clk:        Pointer to struct clk for the clock
 409  * @ctrl:       Clock control register
 410  * @name:       PLL name
 411  */
 412 static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name)
 413 {
 414         clk->name = name;
 415         clk->reg = ctrl;
 416         clk->parent = cpu_1x_clk;
 417         clk->frequency = zynq_clk_get_rate(clk->parent);
 418 }
 419
 420 static void init_aper_clocks(void)
 421 {
 422         zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
 423                                    &slcr_base->aper_clk_ctrl, "usb0_aper");
 424         zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
 425                                    &slcr_base->aper_clk_ctrl, "usb1_aper");
 426
 427         zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
 428                                    &slcr_base->aper_clk_ctrl, "gem0_aper");
 429         zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
 430                                    &slcr_base->aper_clk_ctrl, "gem1_aper");
 431
 432         zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
 433                                    &slcr_base->aper_clk_ctrl, "sdio0_aper");
 434         zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
 435                                    &slcr_base->aper_clk_ctrl, "sdio1_aper");
 436
 437         zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
 438                                    &slcr_base->aper_clk_ctrl, "spi0_aper");
 439         zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
 440                                    &slcr_base->aper_clk_ctrl, "spi1_aper");
 441
 442         zynq_clk_register_aper_clk(&clks[can0_aper_clk],
 443                                    &slcr_base->aper_clk_ctrl, "can0_aper");
 444         zynq_clk_register_aper_clk(&clks[can1_aper_clk],
 445                                    &slcr_base->aper_clk_ctrl, "can1_aper");
 446
 447         zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
 448                                    &slcr_base->aper_clk_ctrl, "i2c0_aper");
 449         zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
 450                                    &slcr_base->aper_clk_ctrl, "i2c1_aper");
 451
 452         zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
 453                                    &slcr_base->aper_clk_ctrl, "uart0_aper");
 454         zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
 455                                    &slcr_base->aper_clk_ctrl, "uart1_aper");
 456
 457         zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
 458                                    &slcr_base->aper_clk_ctrl, "gpio_aper");
 459
 460         zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
 461                                    &slcr_base->aper_clk_ctrl, "lqspi_aper");
 462
 463         zynq_clk_register_aper_clk(&clks[smc_aper_clk],
 464                                    &slcr_base->aper_clk_ctrl, "smc_aper");
 465 }
 466
 467 /**
 468  * __zynq_clk_pll_get_rate() - Get PLL rate
 469  * @addr:       Address of the PLL's control register
 470  * Returns the current PLL output rate.
 471  */
 472 static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
 473 {
 474         u32 reg, mul, bypass;
 475
 476         reg = readl(addr);
 477         bypass = reg & PLLCTRL_BPFORCE_MASK;
 478         if (bypass)
 479                 mul = 1;
 480         else
 481                 mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
 482
 483         return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
 484 }
 485
 486 /**
 487  * zynq_clk_pll_get_rate() - Get PLL rate
 488  * @pll:        Handle of the PLL
 489  * Returns the current clock rate of @pll.
 490  */
 491 static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
 492 {
 493         return __zynq_clk_pll_get_rate(pll->reg);
 494 }
 495
 496 /**
 497  * zynq_clk_register_pll() - Set up a PLL with the framework
 498  * @clk:        Pointer to struct clk for the PLL
 499  * @ctrl:       PLL control register
 500  * @name:       PLL name
 501  * @prate:      PLL input clock rate
 502  */
 503 static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name,
 504                 unsigned long prate)
 505 {
 506         clk->name = name;
 507         clk->reg = ctrl;
 508         clk->frequency = zynq_clk_pll_get_rate(clk);
 509         clk->ops.get_rate = zynq_clk_pll_get_rate;
 510 }
 511
 512 /**
 513  * clkid_2_register() - Get clock control register
 514  * @id: Clock identifier of one of the PLLs
 515  * Returns the address of the requested PLL's control register.
 516  */
 517 static u32 *clkid_2_register(enum zynq_clk id)
 518 {
 519         switch (id) {
 520         case armpll_clk:
 521                 return &slcr_base->arm_pll_ctrl;
 522         case ddrpll_clk:
 523                 return &slcr_base->ddr_pll_ctrl;
 524         case iopll_clk:
 525                 return &slcr_base->io_pll_ctrl;
 526         default:
 527                 return &slcr_base->io_pll_ctrl;
 528         }
 529 }
 530
 531 /* API */
 532 /**
 533  * zynq_clk_early_init() - Early init for the clock framework
 534  *
 535  * This function is called from before relocation and sets up the CPU clock
 536  * frequency in the global data struct.
 537  */
 538 void zynq_clk_early_init(void)
 539 {
 540         u32 reg = readl(&slcr_base->arm_clk_ctrl);
 541         u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 542         u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 543         enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
 544         u32 *pllreg = clkid_2_register(parent);
 545         unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
 546
 547         if (!div)
 548                 div = 1;
 549
 550         gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
 551 }
 552
 553 /**
 554  * get_uart_clk() - Get UART input frequency
 555  * @dev_index:  UART ID
 556  * Returns UART input clock frequency in Hz.
 557  *
 558  * Compared to zynq_clk_get_rate() this function is designed to work before
 559  * relocation and can be called when the serial UART is set up.
 560  */
 561 unsigned long get_uart_clk(int dev_index)
 562 {
 563         u32 reg = readl(&slcr_base->uart_clk_ctrl);
 564         u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 565         u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 566         enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
 567         u32 *pllreg = clkid_2_register(parent);
 568         unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
 569
 570         if (!div)
 571                 div = 1;
 572
 573         return DIV_ROUND_CLOSEST(prate, div);
 574 }
 575
 576 /**
 577  * set_cpu_clk_info() - Initialize clock framework
 578  * Always returns zero.
 579  *
 580  * This function is called from common code after relocation and sets up the
 581  * clock framework. The framework must not be used before this function had been
 582  * called.
 583  */
 584 int set_cpu_clk_info(void)
 585 {
 586         zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
 587                               "armpll", CONFIG_ZYNQ_PS_CLK_FREQ);
 588         zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
 589                               "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ);
 590         zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
 591                               "iopll", CONFIG_ZYNQ_PS_CLK_FREQ);
 592
 593         init_ddr_clocks();
 594         init_cpu_clocks();
 595         init_periph_clocks();
 596         init_aper_clocks();
 597
 598         gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
 599         gd->bd->bi_dsp_freq = 0;
 600
 601         return 0;
 602 }
 603
 604 /**
 605  * zynq_clk_get_rate() - Get clock rate
 606  * @clk:        Clock identifier
 607  * Returns the current clock rate of @clk on success or zero for an invalid
 608  * clock id.
 609  */
 610 unsigned long zynq_clk_get_rate(enum zynq_clk clk)
 611 {
 612         if (clk < 0 || clk >= clk_max)
 613                 return 0;
 614
 615         return clks[clk].frequency;
 616 }
 617
 618 /**
 619  * zynq_clk_set_rate() - Set clock rate
 620  * @clk:        Clock identifier
 621  * @rate:       Requested clock rate
 622  * Passes on the return value from the clock's set_rate() function or negative
 623  * errno.
 624  */
 625 int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
 626 {
 627         if (clk < 0 || clk >= clk_max)
 628                 return -ENODEV;
 629
 630         if (clks[clk].ops.set_rate)
 631                 return clks[clk].ops.set_rate(&clks[clk], rate);
 632
 633         return -ENXIO;
 634 }
 635
 636 /**
 637  * zynq_clk_get_name() - Get clock name
 638  * @clk:        Clock identifier
 639  * Returns the name of @clk.
 640  */
 641 const char *zynq_clk_get_name(enum zynq_clk clk)
 642 {
 643         return clks[clk].name;
 644 }
 645
 646 /**
 647  * soc_clk_dump() - Print clock frequencies
 648  * Returns zero on success
 649  *
 650  * Implementation for the clk dump command.
 651  */
 652 int soc_clk_dump(void)
 653 {
 654         int i;
 655
 656         printf("clk\t\tfrequency\n");
 657         for (i = 0; i < clk_max; i++) {
 658                 const char *name = zynq_clk_get_name(i);
 659                 if (name)
 660                         printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
 661         }
 662
 663         return 0;
 664 }