arch/arm/cpu/armv8/fsl-lsch3/cpu.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/system.h>
  10 #include <asm/armv8/mmu.h>
  11 #include <asm/io.h>
  12 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
  13 #include "cpu.h"
  14 #include "speed.h"
  15 #include <fsl_mc.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #ifndef CONFIG_SYS_DCACHE_OFF
  20 /*
  21  * To start MMU before DDR is available, we create MMU table in SRAM.
  22  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
  23  * levels of translation tables here to cover 40-bit address space.
  24  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  25  * Level 0 IA[39], table address @0
  26  * Level 1 IA[31:30], table address @01000, 0x2000
  27  * Level 2 IA[29:21], table address @0x3000
  28  */
  29
  30 #define SECTION_SHIFT_L0        39UL
  31 #define SECTION_SHIFT_L1        30UL
  32 #define SECTION_SHIFT_L2        21UL
  33 #define BLOCK_SIZE_L0           0x8000000000UL
  34 #define BLOCK_SIZE_L1           (1 << SECTION_SHIFT_L1)
  35 #define BLOCK_SIZE_L2           (1 << SECTION_SHIFT_L2)
  36 #define CONFIG_SYS_IFC_BASE     0x30000000
  37 #define CONFIG_SYS_IFC_SIZE     0x10000000
  38 #define CONFIG_SYS_IFC_BASE2    0x500000000
  39 #define CONFIG_SYS_IFC_SIZE2    0x100000000
  40 #define TCR_EL2_PS_40BIT        (2 << 16)
  41 #define LSCH3_VA_BITS           (40)
  42 #define LSCH3_TCR       (TCR_TG0_4K             | \
  43                         TCR_EL2_PS_40BIT        | \
  44                         TCR_SHARED_NON          | \
  45                         TCR_ORGN_NC             | \
  46                         TCR_IRGN_NC             | \
  47                         TCR_T0SZ(LSCH3_VA_BITS))
  48
  49 /*
  50  * Final MMU
  51  * Let's start from the same layout as early MMU and modify as needed.
  52  * IFC regions will be cache-inhibit.
  53  */
  54 #define FINAL_QBMAN_CACHED_MEM  0x818000000UL
  55 #define FINAL_QBMAN_CACHED_SIZE 0x4000000
  56
  57
  58 static inline void early_mmu_setup(void)
  59 {
  60         int el;
  61         u64 i;
  62         u64 section_l1t0, section_l1t1, section_l2;
  63         u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
  64         u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
  65         u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
  66         u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
  67
  68
  69         level0_table[0] =
  70                 (u64)level1_table_0 | PMD_TYPE_TABLE;
  71         level0_table[1] =
  72                 (u64)level1_table_1 | PMD_TYPE_TABLE;
  73
  74         /*
  75          * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
  76          * set level 1 table 1 to cache enabled, covering 512GB to 1TB
  77          * set level 2 table to cache-inhibit, covering 0 to 1GB
  78          */
  79         section_l1t0 = 0;
  80         section_l1t1 = BLOCK_SIZE_L0;
  81         section_l2 = 0;
  82         for (i = 0; i < 512; i++) {
  83                 set_pgtable_section(level1_table_0, i, section_l1t0,
  84                                     MT_DEVICE_NGNRNE);
  85                 set_pgtable_section(level1_table_1, i, section_l1t1,
  86                                     MT_NORMAL);
  87                 set_pgtable_section(level2_table, i, section_l2,
  88                                     MT_DEVICE_NGNRNE);
  89                 section_l1t0 += BLOCK_SIZE_L1;
  90                 section_l1t1 += BLOCK_SIZE_L1;
  91                 section_l2 += BLOCK_SIZE_L2;
  92         }
  93
  94         level1_table_0[0] =
  95                 (u64)level2_table | PMD_TYPE_TABLE;
  96         level1_table_0[1] =
  97                 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT |
  98                 PMD_ATTRINDX(MT_DEVICE_NGNRNE);
  99         level1_table_0[2] =
 100                 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
 101                 PMD_ATTRINDX(MT_NORMAL);
 102         level1_table_0[3] =
 103                 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
 104                 PMD_ATTRINDX(MT_NORMAL);
 105
 106         /* Rewrite table to enable cache */
 107         set_pgtable_section(level2_table,
 108                             CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
 109                             CONFIG_SYS_FSL_OCRAM_BASE,
 110                             MT_NORMAL);
 111         for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2;
 112              i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE)
 113              >> SECTION_SHIFT_L2; i++) {
 114                 section_l2 = i << SECTION_SHIFT_L2;
 115                 set_pgtable_section(level2_table, i,
 116                                     section_l2, MT_NORMAL);
 117         }
 118
 119         el = current_el();
 120         set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES);
 121         set_sctlr(get_sctlr() | CR_M);
 122 }
 123
 124 /*
 125  * This final tale looks similar to early table, but different in detail.
 126  * These tables are in regular memory. Cache on IFC is disabled. One sub table
 127  * is added to enable cache for QBMan.
 128  */
 129 static inline void final_mmu_setup(void)
 130 {
 131         int el;
 132         u64 i, tbl_base, tbl_limit, section_base;
 133         u64 section_l1t0, section_l1t1, section_l2;
 134         u64 *level0_table = (u64 *)gd->arch.tlb_addr;
 135         u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
 136         u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
 137         u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
 138         u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
 139
 140
 141         level0_table[0] =
 142                 (u64)level1_table_0 | PMD_TYPE_TABLE;
 143         level0_table[1] =
 144                 (u64)level1_table_1 | PMD_TYPE_TABLE;
 145
 146         /*
 147          * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
 148          * set level 1 table 1 to cache enabled, covering 512GB to 1TB
 149          * set level 2 table 0 to cache-inhibit, covering 0 to 1GB
 150          */
 151         section_l1t0 = 0;
 152         section_l1t1 = BLOCK_SIZE_L0;
 153         section_l2 = 0;
 154         for (i = 0; i < 512; i++) {
 155                 set_pgtable_section(level1_table_0, i, section_l1t0,
 156                                     MT_DEVICE_NGNRNE);
 157                 set_pgtable_section(level1_table_1, i, section_l1t1,
 158                                     MT_NORMAL);
 159                 set_pgtable_section(level2_table_0, i, section_l2,
 160                                     MT_DEVICE_NGNRNE);
 161                 section_l1t0 += BLOCK_SIZE_L1;
 162                 section_l1t1 += BLOCK_SIZE_L1;
 163                 section_l2 += BLOCK_SIZE_L2;
 164         }
 165
 166         level1_table_0[0] =
 167                 (u64)level2_table_0 | PMD_TYPE_TABLE;
 168         level1_table_0[2] =
 169                 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
 170                 PMD_ATTRINDX(MT_NORMAL);
 171         level1_table_0[3] =
 172                 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
 173                 PMD_ATTRINDX(MT_NORMAL);
 174
 175         /* Rewrite table to enable cache */
 176         set_pgtable_section(level2_table_0,
 177                             CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
 178                             CONFIG_SYS_FSL_OCRAM_BASE,
 179                             MT_NORMAL);
 180
 181         /*
 182          * Fill in other part of tables if cache is needed
 183          * If finer granularity than 1GB is needed, sub table
 184          * should be created.
 185          */
 186         section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1);
 187         i = section_base >> SECTION_SHIFT_L1;
 188         level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE;
 189         section_l2 = section_base;
 190         for (i = 0; i < 512; i++) {
 191                 set_pgtable_section(level2_table_1, i, section_l2,
 192                                     MT_DEVICE_NGNRNE);
 193                 section_l2 += BLOCK_SIZE_L2;
 194         }
 195         tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1);
 196         tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) &
 197                     (BLOCK_SIZE_L1 - 1);
 198         for (i = tbl_base >> SECTION_SHIFT_L2;
 199              i < tbl_limit >> SECTION_SHIFT_L2; i++) {
 200                 section_l2 = section_base + (i << SECTION_SHIFT_L2);
 201                 set_pgtable_section(level2_table_1, i,
 202                                     section_l2, MT_NORMAL);
 203         }
 204
 205         /* flush new MMU table */
 206         flush_dcache_range(gd->arch.tlb_addr,
 207                            gd->arch.tlb_addr +  gd->arch.tlb_size);
 208
 209         /* point TTBR to the new table */
 210         el = current_el();
 211         asm volatile("dsb sy");
 212         if (el == 1) {
 213                 asm volatile("msr ttbr0_el1, %0"
 214                              : : "r" ((u64)level0_table) : "memory");
 215         } else if (el == 2) {
 216                 asm volatile("msr ttbr0_el2, %0"
 217                              : : "r" ((u64)level0_table) : "memory");
 218         } else if (el == 3) {
 219                 asm volatile("msr ttbr0_el3, %0"
 220                              : : "r" ((u64)level0_table) : "memory");
 221         } else {
 222                 hang();
 223         }
 224         asm volatile("isb");
 225
 226         /*
 227          * MMU is already enabled, just need to invalidate TLB to load the
 228          * new table. The new table is compatible with the current table, if
 229          * MMU somehow walks through the new table before invalidation TLB,
 230          * it still works. So we don't need to turn off MMU here.
 231          */
 232 }
 233
 234 int arch_cpu_init(void)
 235 {
 236         icache_enable();
 237         __asm_invalidate_dcache_all();
 238         __asm_invalidate_tlb_all();
 239         early_mmu_setup();
 240         set_sctlr(get_sctlr() | CR_C);
 241         return 0;
 242 }
 243
 244 /*
 245  * flush_l3_cache
 246  * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power
 247  * state, by writing to HP-F P-state request register.
 248  * Fixme: This function should moved to a common file if other SoCs also use
 249  * the same Dickens.
 250  */
 251 #define HNF0_PSTATE_REQ 0x04200010
 252 #define HNF1_PSTATE_REQ 0x04210010
 253 #define HNF2_PSTATE_REQ 0x04220010
 254 #define HNF3_PSTATE_REQ 0x04230010
 255 #define HNF4_PSTATE_REQ 0x04240010
 256 #define HNF5_PSTATE_REQ 0x04250010
 257 #define HNF6_PSTATE_REQ 0x04260010
 258 #define HNF7_PSTATE_REQ 0x04270010
 259 #define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC)
 260 #define HNFPSTAT_FAM    0x3
 261 #define HNFPSTAT_SFONLY 0x01
 262
 263 static void hnf_pstate_req(u64 *ptr, u64 state)
 264 {
 265         int timeout = 1000;
 266         out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3));
 267         ptr++;
 268         /* checking if the transition is completed */
 269         while (timeout > 0) {
 270                 if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3))
 271                         break;
 272                 udelay(100);
 273                 timeout--;
 274         }
 275 }
 276
 277 void flush_l3_cache(void)
 278 {
 279         hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY);
 280         hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY);
 281         hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY);
 282         hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY);
 283         hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY);
 284         hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY);
 285         hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY);
 286         hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY);
 287         hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM);
 288         hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM);
 289         hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM);
 290         hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM);
 291         hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM);
 292         hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM);
 293         hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM);
 294         hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM);
 295 }
 296
 297 /*
 298  * This function is called from lib/board.c.
 299  * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
 300  * There is no need to disable d-cache for this operation.
 301  */
 302 void enable_caches(void)
 303 {
 304         final_mmu_setup();
 305         __asm_invalidate_tlb_all();
 306 }
 307 #endif
 308
 309 static inline u32 initiator_type(u32 cluster, int init_id)
 310 {
 311         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 312         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 313         u32 type = in_le32(&gur->tp_ityp[idx]);
 314
 315         if (type & TP_ITYP_AV)
 316                 return type;
 317
 318         return 0;
 319 }
 320
 321 u32 cpu_mask(void)
 322 {
 323         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 324         int i = 0, count = 0;
 325         u32 cluster, type, mask = 0;
 326
 327         do {
 328                 int j;
 329                 cluster = in_le32(&gur->tp_cluster[i].lower);
 330                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 331                         type = initiator_type(cluster, j);
 332                         if (type) {
 333                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 334                                         mask |= 1 << count;
 335                                 count++;
 336                         }
 337                 }
 338                 i++;
 339         } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 340
 341         return mask;
 342 }
 343
 344 /*
 345  * Return the number of cores on this SOC.
 346  */
 347 int cpu_numcores(void)
 348 {
 349         return hweight32(cpu_mask());
 350 }
 351
 352 int fsl_qoriq_core_to_cluster(unsigned int core)
 353 {
 354         struct ccsr_gur __iomem *gur =
 355                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 356         int i = 0, count = 0;
 357         u32 cluster;
 358
 359         do {
 360                 int j;
 361                 cluster = in_le32(&gur->tp_cluster[i].lower);
 362                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 363                         if (initiator_type(cluster, j)) {
 364                                 if (count == core)
 365                                         return i;
 366                                 count++;
 367                         }
 368                 }
 369                 i++;
 370         } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 371
 372         return -1;      /* cannot identify the cluster */
 373 }
 374
 375 u32 fsl_qoriq_core_to_type(unsigned int core)
 376 {
 377         struct ccsr_gur __iomem *gur =
 378                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 379         int i = 0, count = 0;
 380         u32 cluster, type;
 381
 382         do {
 383                 int j;
 384                 cluster = in_le32(&gur->tp_cluster[i].lower);
 385                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 386                         type = initiator_type(cluster, j);
 387                         if (type) {
 388                                 if (count == core)
 389                                         return type;
 390                                 count++;
 391                         }
 392                 }
 393                 i++;
 394         } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
 395
 396         return -1;      /* cannot identify the cluster */
 397 }
 398
 399 #ifdef CONFIG_DISPLAY_CPUINFO
 400 int print_cpuinfo(void)
 401 {
 402         struct sys_info sysinfo;
 403         char buf[32];
 404         unsigned int i, core;
 405         u32 type;
 406
 407         get_sys_info(&sysinfo);
 408         puts("Clock Configuration:");
 409         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 410                 if (!(i % 3))
 411                         puts("\n       ");
 412                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 413                 printf("CPU%d(%s):%-4s MHz  ", core,
 414                        type == TY_ITYP_VER_A7 ? "A7 " :
 415                        (type == TY_ITYP_VER_A53 ? "A53" :
 416                         (type == TY_ITYP_VER_A57 ? "A57" : "   ")),
 417                        strmhz(buf, sysinfo.freq_processor[core]));
 418         }
 419         printf("\n       Bus:      %-4s MHz  ",
 420                strmhz(buf, sysinfo.freq_systembus));
 421         printf("DDR:      %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
 422         puts("\n");
 423
 424         return 0;
 425 }
 426 #endif
 427
 428 int cpu_eth_init(bd_t *bis)
 429 {
 430         int error = 0;
 431
 432 #ifdef CONFIG_FSL_MC_ENET
 433         error = mc_init(bis);
 434 #endif
 435         return error;
 436 }