arch/arm/dts/ls1021a-twr.dts

   1 /*
   2  * Freescale ls1021a TWR board device tree source
   3  *
   4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /dts-v1/;
  10 #include "ls1021a.dtsi"
  11
  12 / {
  13         model = "LS1021A TWR Board";
  14
  15         aliases {
  16                 enet2_rgmii_phy = &rgmii_phy1;
  17                 enet0_sgmii_phy = &sgmii_phy2;
  18                 enet1_sgmii_phy = &sgmii_phy0;
  19                 spi0 = &qspi;
  20         };
  21 };
  22
  23 &qspi {
  24         bus-num = <0>;
  25         status = "okay";
  26
  27         qflash0: n25q128a13@0 {
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30                 compatible = "spi-flash";
  31                 spi-max-frequency = <20000000>;
  32                 reg = <0>;
  33         };
  34 };
  35
  36 &i2c0 {
  37         status = "okay";
  38 };
  39
  40 &i2c1 {
  41         status = "okay";
  42 };
  43
  44 &ifc {
  45         #address-cells = <2>;
  46         #size-cells = <1>;
  47         /* NOR Flash on board */
  48         ranges = <0x0 0x0 0x60000000 0x08000000>;
  49         status = "okay";
  50
  51         nor@0,0 {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 compatible = "cfi-flash";
  55                 reg = <0x0 0x0 0x8000000>;
  56                 bank-width = <2>;
  57                 device-width = <1>;
  58         };
  59 };
  60
  61 &lpuart0 {
  62         status = "okay";
  63 };
  64
  65 &mdio0 {
  66         sgmii_phy0: ethernet-phy@0 {
  67                 reg = <0x0>;
  68         };
  69         rgmii_phy1: ethernet-phy@1 {
  70                 reg = <0x1>;
  71         };
  72         sgmii_phy2: ethernet-phy@2 {
  73                 reg = <0x2>;
  74         };
  75         tbi1: tbi-phy@1f {
  76                 reg = <0x1f>;
  77                 device_type = "tbi-phy";
  78         };
  79 };
  80
  81 &uart0 {
  82         status = "okay";
  83 };
  84
  85 &uart1 {
  86         status = "okay";
  87 };