arch/arm/dts/sun9i-a80.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton64.dtsi"
  51
  52 #include <dt-bindings/interrupt-controller/arm-gic.h>
  53
  54 #include <dt-bindings/pinctrl/sun4i-a10.h>
  55
  56 / {
  57         interrupt-parent = <&gic>;
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 cpu0: cpu@0 {
  64                         compatible = "arm,cortex-a7";
  65                         device_type = "cpu";
  66                         reg = <0x0>;
  67                 };
  68
  69                 cpu1: cpu@1 {
  70                         compatible = "arm,cortex-a7";
  71                         device_type = "cpu";
  72                         reg = <0x1>;
  73                 };
  74
  75                 cpu2: cpu@2 {
  76                         compatible = "arm,cortex-a7";
  77                         device_type = "cpu";
  78                         reg = <0x2>;
  79                 };
  80
  81                 cpu3: cpu@3 {
  82                         compatible = "arm,cortex-a7";
  83                         device_type = "cpu";
  84                         reg = <0x3>;
  85                 };
  86
  87                 cpu4: cpu@100 {
  88                         compatible = "arm,cortex-a15";
  89                         device_type = "cpu";
  90                         reg = <0x100>;
  91                 };
  92
  93                 cpu5: cpu@101 {
  94                         compatible = "arm,cortex-a15";
  95                         device_type = "cpu";
  96                         reg = <0x101>;
  97                 };
  98
  99                 cpu6: cpu@102 {
 100                         compatible = "arm,cortex-a15";
 101                         device_type = "cpu";
 102                         reg = <0x102>;
 103                 };
 104
 105                 cpu7: cpu@103 {
 106                         compatible = "arm,cortex-a15";
 107                         device_type = "cpu";
 108                         reg = <0x103>;
 109                 };
 110         };
 111
 112         memory {
 113                 /* 8GB max. with LPAE */
 114                 reg = <0 0x20000000 0x02 0>;
 115         };
 116
 117         timer {
 118                 compatible = "arm,armv7-timer";
 119                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 120                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 121                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 122                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 123                 clock-frequency = <24000000>;
 124                 arm,cpu-registers-not-fw-configured;
 125         };
 126
 127         clocks {
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 /*
 131                  * map 64 bit address range down to 32 bits,
 132                  * as the peripherals are all under 512MB.
 133                  */
 134                 ranges = <0 0 0 0x20000000>;
 135
 136                 osc24M: osc24M_clk {
 137                         #clock-cells = <0>;
 138                         compatible = "fixed-clock";
 139                         clock-frequency = <24000000>;
 140                         clock-output-names = "osc24M";
 141                 };
 142
 143                 osc32k: osc32k_clk {
 144                         #clock-cells = <0>;
 145                         compatible = "fixed-clock";
 146                         clock-frequency = <32768>;
 147                         clock-output-names = "osc32k";
 148                 };
 149
 150                 usb_mod_clk: clk@00a08000 {
 151                         #clock-cells = <1>;
 152                         #reset-cells = <1>;
 153                         compatible = "allwinner,sun9i-a80-usb-mod-clk";
 154                         reg = <0x00a08000 0x4>;
 155                         clocks = <&ahb1_gates 1>;
 156                         clock-output-names = "usb0_ahb", "usb_ohci0",
 157                                              "usb1_ahb", "usb_ohci1",
 158                                              "usb2_ahb", "usb_ohci2";
 159                 };
 160
 161                 usb_phy_clk: clk@00a08004 {
 162                         #clock-cells = <1>;
 163                         #reset-cells = <1>;
 164                         compatible = "allwinner,sun9i-a80-usb-phy-clk";
 165                         reg = <0x00a08004 0x4>;
 166                         clocks = <&ahb1_gates 1>;
 167                         clock-output-names = "usb_phy0", "usb_hsic1_480M",
 168                                              "usb_phy1", "usb_hsic2_480M",
 169                                              "usb_phy2", "usb_hsic_12M";
 170                 };
 171
 172                 pll4: clk@0600000c {
 173                         #clock-cells = <0>;
 174                         compatible = "allwinner,sun9i-a80-pll4-clk";
 175                         reg = <0x0600000c 0x4>;
 176                         clocks = <&osc24M>;
 177                         clock-output-names = "pll4";
 178                 };
 179
 180                 pll12: clk@0600002c {
 181                         #clock-cells = <0>;
 182                         compatible = "allwinner,sun9i-a80-pll4-clk";
 183                         reg = <0x0600002c 0x4>;
 184                         clocks = <&osc24M>;
 185                         clock-output-names = "pll12";
 186                 };
 187
 188                 gt_clk: clk@0600005c {
 189                         #clock-cells = <0>;
 190                         compatible = "allwinner,sun9i-a80-gt-clk";
 191                         reg = <0x0600005c 0x4>;
 192                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 193                         clock-output-names = "gt";
 194                 };
 195
 196                 ahb0: clk@06000060 {
 197                         #clock-cells = <0>;
 198                         compatible = "allwinner,sun9i-a80-ahb-clk";
 199                         reg = <0x06000060 0x4>;
 200                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 201                         clock-output-names = "ahb0";
 202                 };
 203
 204                 ahb1: clk@06000064 {
 205                         #clock-cells = <0>;
 206                         compatible = "allwinner,sun9i-a80-ahb-clk";
 207                         reg = <0x06000064 0x4>;
 208                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 209                         clock-output-names = "ahb1";
 210                 };
 211
 212                 ahb2: clk@06000068 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun9i-a80-ahb-clk";
 215                         reg = <0x06000068 0x4>;
 216                         clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
 217                         clock-output-names = "ahb2";
 218                 };
 219
 220                 apb0: clk@06000070 {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun9i-a80-apb0-clk";
 223                         reg = <0x06000070 0x4>;
 224                         clocks = <&osc24M>, <&pll4>;
 225                         clock-output-names = "apb0";
 226                 };
 227
 228                 apb1: clk@06000074 {
 229                         #clock-cells = <0>;
 230                         compatible = "allwinner,sun9i-a80-apb1-clk";
 231                         reg = <0x06000074 0x4>;
 232                         clocks = <&osc24M>, <&pll4>;
 233                         clock-output-names = "apb1";
 234                 };
 235
 236                 cci400_clk: clk@06000078 {
 237                         #clock-cells = <0>;
 238                         compatible = "allwinner,sun9i-a80-gt-clk";
 239                         reg = <0x06000078 0x4>;
 240                         clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
 241                         clock-output-names = "cci400";
 242                 };
 243
 244                 mmc0_clk: clk@06000410 {
 245                         #clock-cells = <1>;
 246                         compatible = "allwinner,sun9i-a80-mmc-clk";
 247                         reg = <0x06000410 0x4>;
 248                         clocks = <&osc24M>, <&pll4>;
 249                         clock-output-names = "mmc0", "mmc0_output",
 250                                              "mmc0_sample";
 251                 };
 252
 253                 mmc1_clk: clk@06000414 {
 254                         #clock-cells = <1>;
 255                         compatible = "allwinner,sun9i-a80-mmc-clk";
 256                         reg = <0x06000414 0x4>;
 257                         clocks = <&osc24M>, <&pll4>;
 258                         clock-output-names = "mmc1", "mmc1_output",
 259                                              "mmc1_sample";
 260                 };
 261
 262                 mmc2_clk: clk@06000418 {
 263                         #clock-cells = <1>;
 264                         compatible = "allwinner,sun9i-a80-mmc-clk";
 265                         reg = <0x06000418 0x4>;
 266                         clocks = <&osc24M>, <&pll4>;
 267                         clock-output-names = "mmc2", "mmc2_output",
 268                                              "mmc2_sample";
 269                 };
 270
 271                 mmc3_clk: clk@0600041c {
 272                         #clock-cells = <1>;
 273                         compatible = "allwinner,sun9i-a80-mmc-clk";
 274                         reg = <0x0600041c 0x4>;
 275                         clocks = <&osc24M>, <&pll4>;
 276                         clock-output-names = "mmc3", "mmc3_output",
 277                                              "mmc3_sample";
 278                 };
 279
 280                 ahb0_gates: clk@06000580 {
 281                         #clock-cells = <1>;
 282                         compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
 283                         reg = <0x06000580 0x4>;
 284                         clocks = <&ahb0>;
 285                         clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
 286                                         <14>, <15>, <16>, <18>, <20>, <21>,
 287                                         <22>, <23>;
 288                         clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
 289                                         "ahb0_ss", "ahb0_sd", "ahb0_nand1",
 290                                         "ahb0_nand0", "ahb0_sdram",
 291                                         "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
 292                                         "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
 293                                         "ahb0_spi3";
 294                 };
 295
 296                 ahb1_gates: clk@06000584 {
 297                         #clock-cells = <1>;
 298                         compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
 299                         reg = <0x06000584 0x4>;
 300                         clocks = <&ahb1>;
 301                         clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
 302                         clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
 303                                         "ahb1_gmac", "ahb1_msgbox",
 304                                         "ahb1_spinlock", "ahb1_hstimer",
 305                                         "ahb1_dma";
 306                 };
 307
 308                 ahb2_gates: clk@06000588 {
 309                         #clock-cells = <1>;
 310                         compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
 311                         reg = <0x06000588 0x4>;
 312                         clocks = <&ahb2>;
 313                         clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
 314                                         <11>;
 315                         clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
 316                                         "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
 317                                         "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
 318                 };
 319
 320                 apb0_gates: clk@06000590 {
 321                         #clock-cells = <1>;
 322                         compatible = "allwinner,sun9i-a80-apb0-gates-clk";
 323                         reg = <0x06000590 0x4>;
 324                         clocks = <&apb0>;
 325                         clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
 326                                         <17>, <18>, <19>;
 327                         clock-output-names = "apb0_spdif", "apb0_pio",
 328                                         "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
 329                                         "apb0_lradc", "apb0_gpadc", "apb0_twd",
 330                                         "apb0_cirtx";
 331                 };
 332
 333                 apb1_gates: clk@06000594 {
 334                         #clock-cells = <1>;
 335                         compatible = "allwinner,sun9i-a80-apb1-gates-clk";
 336                         reg = <0x06000594 0x4>;
 337                         clocks = <&apb1>;
 338                         clock-indices = <0>, <1>, <2>, <3>, <4>,
 339                                         <16>, <17>, <18>, <19>, <20>, <21>;
 340                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 341                                         "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
 342                                         "apb1_uart0", "apb1_uart1",
 343                                         "apb1_uart2", "apb1_uart3",
 344                                         "apb1_uart4", "apb1_uart5";
 345                 };
 346         };
 347
 348         soc {
 349                 compatible = "simple-bus";
 350                 #address-cells = <1>;
 351                 #size-cells = <1>;
 352                 /*
 353                  * map 64 bit address range down to 32 bits,
 354                  * as the peripherals are all under 512MB.
 355                  */
 356                 ranges = <0 0 0 0x20000000>;
 357
 358                 ehci0: usb@00a00000 {
 359                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 360                         reg = <0x00a00000 0x100>;
 361                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 362                         clocks = <&usb_mod_clk 1>;
 363                         resets = <&usb_mod_clk 17>;
 364                         phys = <&usbphy1>;
 365                         phy-names = "usb";
 366                         status = "disabled";
 367                 };
 368
 369                 ohci0: usb@00a00400 {
 370                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 371                         reg = <0x00a00400 0x100>;
 372                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 373                         clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
 374                         resets = <&usb_mod_clk 17>;
 375                         phys = <&usbphy1>;
 376                         phy-names = "usb";
 377                         status = "disabled";
 378                 };
 379
 380                 usbphy1: phy@00a00800 {
 381                         compatible = "allwinner,sun9i-a80-usb-phy";
 382                         reg = <0x00a00800 0x4>;
 383                         clocks = <&usb_phy_clk 1>;
 384                         clock-names = "phy";
 385                         resets = <&usb_phy_clk 17>;
 386                         reset-names = "phy";
 387                         status = "disabled";
 388                         #phy-cells = <0>;
 389                 };
 390
 391                 ehci1: usb@00a01000 {
 392                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 393                         reg = <0x00a01000 0x100>;
 394                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 395                         clocks = <&usb_mod_clk 3>;
 396                         resets = <&usb_mod_clk 18>;
 397                         phys = <&usbphy2>;
 398                         phy-names = "usb";
 399                         status = "disabled";
 400                 };
 401
 402                 usbphy2: phy@00a01800 {
 403                         compatible = "allwinner,sun9i-a80-usb-phy";
 404                         reg = <0x00a01800 0x4>;
 405                         clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
 406                                  <&usb_phy_clk 3>;
 407                         clock-names = "hsic_480M", "hsic_12M", "phy";
 408                         resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
 409                         reset-names = "hsic", "phy";
 410                         status = "disabled";
 411                         #phy-cells = <0>;
 412                         /* usb1 is always used with HSIC */
 413                         phy_type = "hsic";
 414                 };
 415
 416                 ehci2: usb@00a02000 {
 417                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
 418                         reg = <0x00a02000 0x100>;
 419                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 420                         clocks = <&usb_mod_clk 5>;
 421                         resets = <&usb_mod_clk 19>;
 422                         phys = <&usbphy3>;
 423                         phy-names = "usb";
 424                         status = "disabled";
 425                 };
 426
 427                 ohci2: usb@00a02400 {
 428                         compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
 429                         reg = <0x00a02400 0x100>;
 430                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
 432                         resets = <&usb_mod_clk 19>;
 433                         phys = <&usbphy3>;
 434                         phy-names = "usb";
 435                         status = "disabled";
 436                 };
 437
 438                 usbphy3: phy@00a02800 {
 439                         compatible = "allwinner,sun9i-a80-usb-phy";
 440                         reg = <0x00a02800 0x4>;
 441                         clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
 442                                  <&usb_phy_clk 5>;
 443                         clock-names = "hsic_480M", "hsic_12M", "phy";
 444                         resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
 445                         reset-names = "hsic", "phy";
 446                         status = "disabled";
 447                         #phy-cells = <0>;
 448                 };
 449
 450                 mmc0: mmc@01c0f000 {
 451                         compatible = "allwinner,sun5i-a13-mmc";
 452                         reg = <0x01c0f000 0x1000>;
 453                         clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
 454                                  <&mmc0_clk 1>, <&mmc0_clk 2>;
 455                         clock-names = "ahb", "mmc", "output", "sample";
 456                         resets = <&mmc_config_clk 0>;
 457                         reset-names = "ahb";
 458                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 459                         status = "disabled";
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                 };
 463
 464                 mmc1: mmc@01c10000 {
 465                         compatible = "allwinner,sun5i-a13-mmc";
 466                         reg = <0x01c10000 0x1000>;
 467                         clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
 468                                  <&mmc1_clk 1>, <&mmc1_clk 2>;
 469                         clock-names = "ahb", "mmc", "output", "sample";
 470                         resets = <&mmc_config_clk 1>;
 471                         reset-names = "ahb";
 472                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 473                         status = "disabled";
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                 };
 477
 478                 mmc2: mmc@01c11000 {
 479                         compatible = "allwinner,sun5i-a13-mmc";
 480                         reg = <0x01c11000 0x1000>;
 481                         clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
 482                                  <&mmc2_clk 1>, <&mmc2_clk 2>;
 483                         clock-names = "ahb", "mmc", "output", "sample";
 484                         resets = <&mmc_config_clk 2>;
 485                         reset-names = "ahb";
 486                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 487                         status = "disabled";
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                 };
 491
 492                 mmc3: mmc@01c12000 {
 493                         compatible = "allwinner,sun5i-a13-mmc";
 494                         reg = <0x01c12000 0x1000>;
 495                         clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
 496                                  <&mmc3_clk 1>, <&mmc3_clk 2>;
 497                         clock-names = "ahb", "mmc", "output", "sample";
 498                         resets = <&mmc_config_clk 3>;
 499                         reset-names = "ahb";
 500                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 501                         status = "disabled";
 502                         #address-cells = <1>;
 503                         #size-cells = <0>;
 504                 };
 505
 506                 mmc_config_clk: clk@01c13000 {
 507                         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 508                         reg = <0x01c13000 0x10>;
 509                         clocks = <&ahb0_gates 8>;
 510                         clock-names = "ahb";
 511                         resets = <&ahb0_resets 8>;
 512                         reset-names = "ahb";
 513                         #clock-cells = <1>;
 514                         #reset-cells = <1>;
 515                         clock-output-names = "mmc0_config", "mmc1_config",
 516                                              "mmc2_config", "mmc3_config";
 517                 };
 518
 519                 gic: interrupt-controller@01c41000 {
 520                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 521                         reg = <0x01c41000 0x1000>,
 522                               <0x01c42000 0x1000>,
 523                               <0x01c44000 0x2000>,
 524                               <0x01c46000 0x2000>;
 525                         interrupt-controller;
 526                         #interrupt-cells = <3>;
 527                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 528                 };
 529
 530                 ahb0_resets: reset@060005a0 {
 531                         #reset-cells = <1>;
 532                         compatible = "allwinner,sun6i-a31-clock-reset";
 533                         reg = <0x060005a0 0x4>;
 534                 };
 535
 536                 ahb1_resets: reset@060005a4 {
 537                         #reset-cells = <1>;
 538                         compatible = "allwinner,sun6i-a31-clock-reset";
 539                         reg = <0x060005a4 0x4>;
 540                 };
 541
 542                 ahb2_resets: reset@060005a8 {
 543                         #reset-cells = <1>;
 544                         compatible = "allwinner,sun6i-a31-clock-reset";
 545                         reg = <0x060005a8 0x4>;
 546                 };
 547
 548                 apb0_resets: reset@060005b0 {
 549                         #reset-cells = <1>;
 550                         compatible = "allwinner,sun6i-a31-clock-reset";
 551                         reg = <0x060005b0 0x4>;
 552                 };
 553
 554                 apb1_resets: reset@060005b4 {
 555                         #reset-cells = <1>;
 556                         compatible = "allwinner,sun6i-a31-clock-reset";
 557                         reg = <0x060005b4 0x4>;
 558                 };
 559
 560                 timer@06000c00 {
 561                         compatible = "allwinner,sun4i-a10-timer";
 562                         reg = <0x06000c00 0xa0>;
 563                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 564                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 566                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 567                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 568                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 569
 570                         clocks = <&osc24M>;
 571                 };
 572
 573                 pio: pinctrl@06000800 {
 574                         compatible = "allwinner,sun9i-a80-pinctrl";
 575                         reg = <0x06000800 0x400>;
 576                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 577                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 578                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 579                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 580                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 581                         clocks = <&apb0_gates 5>;
 582                         gpio-controller;
 583                         interrupt-controller;
 584                         #interrupt-cells = <2>;
 585                         #size-cells = <0>;
 586                         #gpio-cells = <3>;
 587
 588                         i2c3_pins_a: i2c3@0 {
 589                                 allwinner,pins = "PG10", "PG11";
 590                                 allwinner,function = "i2c3";
 591                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 592                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 593                         };
 594
 595                         mmc0_pins: mmc0 {
 596                                 allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
 597                                                  "PF4", "PF5";
 598                                 allwinner,function = "mmc0";
 599                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 600                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 601                         };
 602
 603                         mmc2_8bit_pins: mmc2_8bit {
 604                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 605                                                  "PC10", "PC11", "PC12",
 606                                                  "PC13", "PC14", "PC15";
 607                                 allwinner,function = "mmc2";
 608                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 609                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 610                         };
 611
 612                         uart0_pins_a: uart0@0 {
 613                                 allwinner,pins = "PH12", "PH13";
 614                                 allwinner,function = "uart0";
 615                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 616                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 617                         };
 618
 619                         uart4_pins_a: uart4@0 {
 620                                 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
 621                                 allwinner,function = "uart4";
 622                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 623                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 624                         };
 625                 };
 626
 627                 uart0: serial@07000000 {
 628                         compatible = "snps,dw-apb-uart";
 629                         reg = <0x07000000 0x400>;
 630                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 631                         reg-shift = <2>;
 632                         reg-io-width = <4>;
 633                         clocks = <&apb1_gates 16>;
 634                         resets = <&apb1_resets 16>;
 635                         status = "disabled";
 636                 };
 637
 638                 uart1: serial@07000400 {
 639                         compatible = "snps,dw-apb-uart";
 640                         reg = <0x07000400 0x400>;
 641                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 642                         reg-shift = <2>;
 643                         reg-io-width = <4>;
 644                         clocks = <&apb1_gates 17>;
 645                         resets = <&apb1_resets 17>;
 646                         status = "disabled";
 647                 };
 648
 649                 uart2: serial@07000800 {
 650                         compatible = "snps,dw-apb-uart";
 651                         reg = <0x07000800 0x400>;
 652                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 653                         reg-shift = <2>;
 654                         reg-io-width = <4>;
 655                         clocks = <&apb1_gates 18>;
 656                         resets = <&apb1_resets 18>;
 657                         status = "disabled";
 658                 };
 659
 660                 uart3: serial@07000c00 {
 661                         compatible = "snps,dw-apb-uart";
 662                         reg = <0x07000c00 0x400>;
 663                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 664                         reg-shift = <2>;
 665                         reg-io-width = <4>;
 666                         clocks = <&apb1_gates 19>;
 667                         resets = <&apb1_resets 19>;
 668                         status = "disabled";
 669                 };
 670
 671                 uart4: serial@07001000 {
 672                         compatible = "snps,dw-apb-uart";
 673                         reg = <0x07001000 0x400>;
 674                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 675                         reg-shift = <2>;
 676                         reg-io-width = <4>;
 677                         clocks = <&apb1_gates 20>;
 678                         resets = <&apb1_resets 20>;
 679                         status = "disabled";
 680                 };
 681
 682                 uart5: serial@07001400 {
 683                         compatible = "snps,dw-apb-uart";
 684                         reg = <0x07001400 0x400>;
 685                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 686                         reg-shift = <2>;
 687                         reg-io-width = <4>;
 688                         clocks = <&apb1_gates 21>;
 689                         resets = <&apb1_resets 21>;
 690                         status = "disabled";
 691                 };
 692
 693                 i2c0: i2c@07002800 {
 694                         compatible = "allwinner,sun6i-a31-i2c";
 695                         reg = <0x07002800 0x400>;
 696                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 697                         clocks = <&apb1_gates 0>;
 698                         resets = <&apb1_resets 0>;
 699                         status = "disabled";
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702                 };
 703
 704                 i2c1: i2c@07002c00 {
 705                         compatible = "allwinner,sun6i-a31-i2c";
 706                         reg = <0x07002c00 0x400>;
 707                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 708                         clocks = <&apb1_gates 1>;
 709                         resets = <&apb1_resets 1>;
 710                         status = "disabled";
 711                         #address-cells = <1>;
 712                         #size-cells = <0>;
 713                 };
 714
 715                 i2c2: i2c@07003000 {
 716                         compatible = "allwinner,sun6i-a31-i2c";
 717                         reg = <0x07003000 0x400>;
 718                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 719                         clocks = <&apb1_gates 2>;
 720                         resets = <&apb1_resets 2>;
 721                         status = "disabled";
 722                         #address-cells = <1>;
 723                         #size-cells = <0>;
 724                 };
 725
 726                 i2c3: i2c@07003400 {
 727                         compatible = "allwinner,sun6i-a31-i2c";
 728                         reg = <0x07003400 0x400>;
 729                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 730                         clocks = <&apb1_gates 3>;
 731                         resets = <&apb1_resets 3>;
 732                         status = "disabled";
 733                         #address-cells = <1>;
 734                         #size-cells = <0>;
 735                 };
 736
 737                 i2c4: i2c@07003800 {
 738                         compatible = "allwinner,sun6i-a31-i2c";
 739                         reg = <0x07003800 0x400>;
 740                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 741                         clocks = <&apb1_gates 4>;
 742                         resets = <&apb1_resets 4>;
 743                         status = "disabled";
 744                         #address-cells = <1>;
 745                         #size-cells = <0>;
 746                 };
 747
 748                 r_wdt: watchdog@08001000 {
 749                         compatible = "allwinner,sun6i-a31-wdt";
 750                         reg = <0x08001000 0x20>;
 751                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 752                 };
 753
 754                 r_uart: serial@08002800 {
 755                         compatible = "snps,dw-apb-uart";
 756                         reg = <0x08002800 0x400>;
 757                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 758                         reg-shift = <2>;
 759                         reg-io-width = <4>;
 760                         clocks = <&osc24M>;
 761                         status = "disabled";
 762                 };
 763         };
 764 };