arch/arm/include/asm/arch-am33xx/hardware.h

   1 /*
   2  * hardware.h
   3  *
   4  * hardware specific header
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __AM33XX_HARDWARE_H
  12 #define __AM33XX_HARDWARE_H
  13
  14 #include <config.h>
  15 #include <asm/arch/omap.h>
  16 #ifdef CONFIG_AM33XX
  17 #include <asm/arch/hardware_am33xx.h>
  18 #elif defined(CONFIG_TI814X)
  19 #include <asm/arch/hardware_ti814x.h>
  20 #endif
  21
  22 /*
  23  * Common hardware definitions
  24  */
  25
  26 /* DM Timer base addresses */
  27 #define DM_TIMER0_BASE                  0x4802C000
  28 #define DM_TIMER1_BASE                  0x4802E000
  29 #define DM_TIMER2_BASE                  0x48040000
  30 #define DM_TIMER3_BASE                  0x48042000
  31 #define DM_TIMER4_BASE                  0x48044000
  32 #define DM_TIMER5_BASE                  0x48046000
  33 #define DM_TIMER6_BASE                  0x48048000
  34 #define DM_TIMER7_BASE                  0x4804A000
  35
  36 /* GPIO Base address */
  37 #define GPIO0_BASE                      0x48032000
  38 #define GPIO1_BASE                      0x4804C000
  39
  40 /* BCH Error Location Module */
  41 #define ELM_BASE                        0x48080000
  42
  43 /* EMIF Base address */
  44 #define EMIF4_0_CFG_BASE                0x4C000000
  45 #define EMIF4_1_CFG_BASE                0x4D000000
  46
  47 /* PLL related registers */
  48 #define CM_PER                          0x44E00000
  49 #define CM_WKUP                         0x44E00400
  50 #define CM_DPLL                         0x44E00500
  51 #define CM_DEVICE                       0x44E00700
  52 #define CM_RTC                          0x44E00800
  53 #define CM_CEFUSE                       0x44E00A00
  54 #define PRM_DEVICE                      0x44E00F00
  55
  56 /* VTP Base address */
  57 #define VTP1_CTRL_ADDR                  0x48140E10
  58
  59 /* DDR Base address */
  60 #define DDR_CTRL_ADDR                   0x44E10E04
  61 #define DDR_CONTROL_BASE_ADDR           0x44E11404
  62 #define DDR_PHY_CMD_ADDR2               0x47C0C800
  63 #define DDR_PHY_DATA_ADDR2              0x47C0C8C8
  64
  65 /* UART */
  66 #define DEFAULT_UART_BASE               UART0_BASE
  67
  68 #define DDRPHY_0_CONFIG_BASE            (CTRL_BASE + 0x1400)
  69 #define DDRPHY_CONFIG_BASE              DDRPHY_0_CONFIG_BASE
  70
  71 /* GPMC Base address */
  72 #define GPMC_BASE                       0x50000000
  73
  74 /* CPSW Config space */
  75 #define CPSW_BASE                       0x4A100000
  76
  77 /* OTG */
  78 #define USB0_OTG_BASE                   0x47401000
  79 #define USB1_OTG_BASE                   0x47401800
  80
  81 #endif /* __AM33XX_HARDWARE_H */