arch/arm/include/asm/arch-am33xx/hardware.h

   1 /*
   2  * hardware.h
   3  *
   4  * hardware specific header
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #ifndef __AM33XX_HARDWARE_H
  20 #define __AM33XX_HARDWARE_H
  21
  22 #include <asm/arch/omap.h>
  23 #ifdef CONFIG_AM33XX
  24 #include <asm/arch/hardware_am33xx.h>
  25 #elif defined(CONFIG_TI814X)
  26 #include <asm/arch/hardware_ti814x.h>
  27 #endif
  28
  29 /* Module base addresses */
  30 #define UART0_BASE                      0x44E09000
  31
  32 /* DM Timer base addresses */
  33 #define DM_TIMER0_BASE                  0x4802C000
  34 #define DM_TIMER1_BASE                  0x4802E000
  35 #define DM_TIMER2_BASE                  0x48040000
  36 #define DM_TIMER3_BASE                  0x48042000
  37 #define DM_TIMER4_BASE                  0x48044000
  38 #define DM_TIMER5_BASE                  0x48046000
  39 #define DM_TIMER6_BASE                  0x48048000
  40 #define DM_TIMER7_BASE                  0x4804A000
  41
  42 /* GPIO Base address */
  43 #define GPIO0_BASE                      0x48032000
  44 #define GPIO1_BASE                      0x4804C000
  45 #define GPIO2_BASE                      0x481AC000
  46
  47 /* BCH Error Location Module */
  48 #define ELM_BASE                        0x48080000
  49
  50 /* Watchdog Timer */
  51 #define WDT_BASE                        0x44E35000
  52
  53 /* Control Module Base Address */
  54 #define CTRL_BASE                       0x44E10000
  55 #define CTRL_DEVICE_BASE                0x44E10600
  56
  57 /* PRCM Base Address */
  58 #define PRCM_BASE                       0x44E00000
  59
  60 /* EMIF Base address */
  61 #define EMIF4_0_CFG_BASE                0x4C000000
  62 #define EMIF4_1_CFG_BASE                0x4D000000
  63
  64 /* PLL related registers */
  65 #define CM_PER                          0x44E00000
  66 #define CM_WKUP                         0x44E00400
  67 #define CM_DPLL                         0x44E00500
  68 #define CM_DEVICE                       0x44E00700
  69 #define CM_RTC                          0x44E00800
  70 #define CM_CEFUSE                       0x44E00A00
  71 #define PRM_DEVICE                      0x44E00F00
  72
  73 /* VTP Base address */
  74 #define VTP1_CTRL_ADDR                  0x48140E10
  75
  76 /* DDR Base address */
  77 #define DDR_CTRL_ADDR                   0x44E10E04
  78 #define DDR_CONTROL_BASE_ADDR           0x44E11404
  79 #define DDR_PHY_CMD_ADDR2               0x47C0C800
  80 #define DDR_PHY_DATA_ADDR2              0x47C0C8C8
  81
  82 /* UART */
  83 #define DEFAULT_UART_BASE               UART0_BASE
  84
  85 #define DDRPHY_0_CONFIG_BASE            (CTRL_BASE + 0x1400)
  86 #define DDRPHY_CONFIG_BASE              DDRPHY_0_CONFIG_BASE
  87
  88 /* GPMC Base address */
  89 #define GPMC_BASE                       0x50000000
  90
  91 /* CPSW Config space */
  92 #define CPSW_BASE                       0x4A100000
  93 #define CPSW_MDIO_BASE                  0x4A101000
  94
  95 /* RTC base address */
  96 #define RTC_BASE                        0x44E3E000
  97
  98 /* OTG */
  99 #define USB0_OTG_BASE                   0x47401000
 100 #define USB1_OTG_BASE                   0x47401800
 101
 102 #endif /* __AM33XX_HARDWARE_H */