2 * (C) Copyright 2006-2008
3 * Texas Instruments, <www.ti.com>
6 * Mansoor Ahamed <mansoor.ahamed@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
43 #endif /* __ASSEMBLY__ */
49 * Definitions is as per the following format
50 * #define <PART>_GPMC_CONFIG<x> <value>
52 * PART is the part name e.g. STNOR - Intel Strata Flash
53 * x is GPMC config registers from 1 to 6 (there will be 6 macros)
54 * Value is corresponding value
56 * For every valid PRCM configuration there should be only one definition of
57 * the same. if values are independent of the board, this definition will be
58 * present in this file if values are dependent on the board, then this should
59 * go into corresponding mem-boardName.h file
61 * Currently valid part Names are (PART):
62 * STNOR - Intel Strata Flash
63 * SMNAND - Samsung NAND
64 * MPDB - H4 MPDB board
66 * MNAND - Micron Large page x16 NAND
67 * ONNAND - Samsung One NAND
69 * include/configs/file.h contains the defn - for all CS we are interested
70 * #define OMAP34XX_GPMC_CSx PART
71 * #define OMAP34XX_GPMC_CSx_SIZE Size
72 * #define OMAP34XX_GPMC_CSx_MAP Map
75 * PART - Part Name as defined above
76 * SIZE - how big is the mapping to be
77 * GPMC_SIZE_128M - 0x8
81 * MAP - Map this CS to which address(GPMC address space)- Absolute address
82 * >>24 before being used.
84 #define GPMC_SIZE_256M 0x0
85 #define GPMC_SIZE_128M 0x8
86 #define GPMC_SIZE_64M 0xC
87 #define GPMC_SIZE_32M 0xE
88 #define GPMC_SIZE_16M 0xF
90 #define SMNAND_GPMC_CONFIG1 0x00000800
91 #define SMNAND_GPMC_CONFIG2 0x00141400
92 #define SMNAND_GPMC_CONFIG3 0x00141400
93 #define SMNAND_GPMC_CONFIG4 0x0F010F01
94 #define SMNAND_GPMC_CONFIG5 0x010C1414
95 #define SMNAND_GPMC_CONFIG6 0x1F0F0A80
96 #define SMNAND_GPMC_CONFIG7 0x00000C44
99 #ifdef CONFIG_AM33XX /* SA 8-Bit Nand */
100 #define M_NAND_GPMC_CONFIG1 0x00000800
102 #define M_NAND_GPMC_CONFIG1 0x00001810
104 #define M_NAND_GPMC_CONFIG2 0x001e1e00
105 #define M_NAND_GPMC_CONFIG3 0x001e1e00
106 #define M_NAND_GPMC_CONFIG4 0x16051807
107 #define M_NAND_GPMC_CONFIG5 0x00151e1e
108 #define M_NAND_GPMC_CONFIG6 0x16000f80
109 #define M_NAND_GPMC_CONFIG7 0x00000008
111 #define STNOR_GPMC_CONFIG1 0x3
112 #define STNOR_GPMC_CONFIG2 0x00151501
113 #define STNOR_GPMC_CONFIG3 0x00060602
114 #define STNOR_GPMC_CONFIG4 0x11091109
115 #define STNOR_GPMC_CONFIG5 0x01141F1F
116 #define STNOR_GPMC_CONFIG6 0x000004c4
118 #define SIBNOR_GPMC_CONFIG1 0x1200
119 #define SIBNOR_GPMC_CONFIG2 0x001f1f00
120 #define SIBNOR_GPMC_CONFIG3 0x00080802
121 #define SIBNOR_GPMC_CONFIG4 0x1C091C09
122 #define SIBNOR_GPMC_CONFIG5 0x01131F1F
123 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
125 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
126 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
127 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
128 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
129 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
130 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
132 #define MPDB_GPMC_CONFIG1 0x00011000
133 #define MPDB_GPMC_CONFIG2 0x001f1f01
134 #define MPDB_GPMC_CONFIG3 0x00080803
135 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a
136 #define MPDB_GPMC_CONFIG5 0x041f1F1F
137 #define MPDB_GPMC_CONFIG6 0x1F0F04C4
139 #define P2_GPMC_CONFIG1 0x0
140 #define P2_GPMC_CONFIG2 0x0
141 #define P2_GPMC_CONFIG3 0x0
142 #define P2_GPMC_CONFIG4 0x0
143 #define P2_GPMC_CONFIG5 0x0
144 #define P2_GPMC_CONFIG6 0x0
146 #define ONENAND_GPMC_CONFIG1 0x00001200
147 #define ONENAND_GPMC_CONFIG2 0x000F0F01
148 #define ONENAND_GPMC_CONFIG3 0x00030301
149 #define ONENAND_GPMC_CONFIG4 0x0F040F04
150 #define ONENAND_GPMC_CONFIG5 0x010F1010
151 #define ONENAND_GPMC_CONFIG6 0x1F060000
153 #define NET_GPMC_CONFIG1 0x00001000
154 #define NET_GPMC_CONFIG2 0x001e1e01
155 #define NET_GPMC_CONFIG3 0x00080300
156 #define NET_GPMC_CONFIG4 0x1c091c09
157 #define NET_GPMC_CONFIG5 0x04181f1f
158 #define NET_GPMC_CONFIG6 0x00000FCF
159 #define NET_GPMC_CONFIG7 0x00000f6c
161 /* max number of GPMC Chip Selects */
162 #define GPMC_MAX_CS 8
163 /* max number of GPMC regs */
164 #define GPMC_MAX_REG 7
167 #define PISMO1_NAND 2
170 #define PISMO1_ONENAND 5
172 #define PISMO2_NAND_CS0 7
173 #define PISMO2_NAND_CS1 8
175 /* make it readable for the gpmc_init */
176 #define PISMO1_NOR_BASE FLASH_BASE
177 #define PISMO1_NAND_BASE NAND_BASE
178 #define PISMO1_NAND_SIZE GPMC_SIZE_256M
180 #endif /* endif _MEM_H_ */