arch/arm/include/asm/arch-at91/sama5d3_smc.h

   1 /*
   2  * Copyright (C) 2012 Atmel Corporation.
   3  *
   4  * Static Memory Controllers (SMC) - System peripherals registers.
   5  * Based on SAMA5D3 datasheet.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #ifndef SAMA5D3_SMC_H
  14 #define SAMA5D3_SMC_H
  15
  16 #ifdef __ASSEMBLY__
  17 #define AT91_ASM_SMC_SETUP0     (ATMEL_BASE_SMC + 0x600)
  18 #define AT91_ASM_SMC_PULSE0     (ATMEL_BASE_SMC + 0x604)
  19 #define AT91_ASM_SMC_CYCLE0     (ATMEL_BASE_SMC + 0x608)
  20 #define AT91_ASM_SMC_MODE0      (ATMEL_BASE_SMC + 0x60C)
  21 #else
  22 struct at91_cs {
  23         u32     reserved[96];
  24         u32     setup;          /* 0x600 SMC Setup Register */
  25         u32     pulse;          /* 0x604 SMC Pulse Register */
  26         u32     cycle;          /* 0x608 SMC Cycle Register */
  27         u32     timings;        /* 0x60C SMC Cycle Register */
  28         u32     mode;           /* 0x610 SMC Mode Register */
  29 };
  30
  31 struct at91_smc {
  32         struct at91_cs cs[4];
  33 };
  34 #endif /*  __ASSEMBLY__ */
  35
  36 #define AT91_SMC_SETUP_NWE(x)           (x & 0x3f)
  37 #define AT91_SMC_SETUP_NCS_WR(x)        ((x & 0x3f) << 8)
  38 #define AT91_SMC_SETUP_NRD(x)           ((x & 0x3f) << 16)
  39 #define AT91_SMC_SETUP_NCS_RD(x)        ((x & 0x3f) << 24)
  40
  41 #define AT91_SMC_PULSE_NWE(x)           (x & 0x3f)
  42 #define AT91_SMC_PULSE_NCS_WR(x)        ((x & 0x3f) << 8)
  43 #define AT91_SMC_PULSE_NRD(x)           ((x & 0x3f) << 16)
  44 #define AT91_SMC_PULSE_NCS_RD(x)        ((x & 0x3f) << 24)
  45
  46 #define AT91_SMC_CYCLE_NWE(x)           (x & 0x1ff)
  47 #define AT91_SMC_CYCLE_NRD(x)           ((x & 0x1ff) << 16)
  48
  49 #define AT91_SMC_TIMINGS_TCLR(x)        (x & 0xf)
  50 #define AT91_SMC_TIMINGS_TADL(x)        ((x & 0xf) << 4)
  51 #define AT91_SMC_TIMINGS_TAR(x)         ((x & 0xf) << 8)
  52 #define AT91_SMC_TIMINGS_OCMS(x)        ((x & 0x1) << 12)
  53 #define AT91_SMC_TIMINGS_TRR(x)         ((x & 0xf) << 16)
  54 #define AT91_SMC_TIMINGS_TWB(x)         ((x & 0xf) << 24)
  55 #define AT91_SMC_TIMINGS_RBNSEL(x)      ((x & 0xf) << 28)
  56 #define AT91_SMC_TIMINGS_NFSEL(x)       ((x & 0x1) << 31)
  57
  58 #define AT91_SMC_MODE_RM_NCS            0x00000000
  59 #define AT91_SMC_MODE_RM_NRD            0x00000001
  60 #define AT91_SMC_MODE_WM_NCS            0x00000000
  61 #define AT91_SMC_MODE_WM_NWE            0x00000002
  62
  63 #define AT91_SMC_MODE_EXNW_DISABLE      0x00000000
  64 #define AT91_SMC_MODE_EXNW_FROZEN       0x00000020
  65 #define AT91_SMC_MODE_EXNW_READY        0x00000030
  66
  67 #define AT91_SMC_MODE_BAT               0x00000100
  68 #define AT91_SMC_MODE_DBW_8             0x00000000
  69 #define AT91_SMC_MODE_DBW_16            0x00001000
  70 #define AT91_SMC_MODE_DBW_32            0x00002000
  71 #define AT91_SMC_MODE_TDF_CYCLE(x)      ((x & 0xf) << 16)
  72 #define AT91_SMC_MODE_TDF               0x00100000
  73 #define AT91_SMC_MODE_PMEN              0x01000000
  74 #define AT91_SMC_MODE_PS_4              0x00000000
  75 #define AT91_SMC_MODE_PS_8              0x10000000
  76 #define AT91_SMC_MODE_PS_16             0x20000000
  77 #define AT91_SMC_MODE_PS_32             0x30000000
  78
  79 #endif