arch/arm/include/asm/arch-fsl-lsch3/config.h

   1 /*
   2  * Copyright 2014, Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
   8 #define _ASM_ARMV8_FSL_LSCH3_CONFIG_
   9
  10 #include <fsl_ddrc_version.h>
  11 #define CONFIG_MP
  12 #define CONFIG_SYS_FSL_OCRAM_BASE       0x18000000      /* initial RAM */
  13 /* Link Definitions */
  14 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  15
  16 #define CONFIG_SYS_IMMR                         0x01000000
  17 #define CONFIG_SYS_FSL_DDR_ADDR                 (CONFIG_SYS_IMMR + 0x00080000)
  18 #define CONFIG_SYS_FSL_DDR2_ADDR                (CONFIG_SYS_IMMR + 0x00090000)
  19 #define CONFIG_SYS_FSL_DDR3_ADDR                0x08210000
  20 #define CONFIG_SYS_FSL_GUTS_ADDR                (CONFIG_SYS_IMMR + 0x00E00000)
  21 #define CONFIG_SYS_FSL_PMU_ADDR                 (CONFIG_SYS_IMMR + 0x00E30000)
  22 #define CONFIG_SYS_FSL_RST_ADDR                 (CONFIG_SYS_IMMR + 0x00E60000)
  23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR        (CONFIG_SYS_IMMR + 0x00300000)
  24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR        (CONFIG_SYS_IMMR + 0x00310000)
  25 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR        (CONFIG_SYS_IMMR + 0x00370000)
  26 #define CONFIG_SYS_IFC_ADDR                     (CONFIG_SYS_IMMR + 0x01240000)
  27 #define CONFIG_SYS_NS16550_COM1                 (CONFIG_SYS_IMMR + 0x011C0500)
  28 #define CONFIG_SYS_NS16550_COM2                 (CONFIG_SYS_IMMR + 0x011C0600)
  29 #define CONFIG_SYS_FSL_TIMER_ADDR               0x023d0000
  30 #define CONFIG_SYS_FSL_PMU_CLTBENR              (CONFIG_SYS_FSL_PMU_ADDR + \
  31                                                  0x18A0)
  32
  33 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01000000)
  34 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01010000)
  35 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01020000)
  36 #define I2C4_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01030000)
  37
  38 /* Generic Interrupt Controller Definitions */
  39 #define GICD_BASE               0x06000000
  40 #define GICR_BASE               0x06100000
  41
  42 /* SMMU Defintions */
  43 #define SMMU_BASE               0x05000000 /* GR0 Base */
  44
  45 /* DDR */
  46 #define CONFIG_SYS_FSL_DDR_LE
  47 #define CONFIG_VERY_BIG_RAM
  48 #ifdef CONFIG_SYS_FSL_DDR4
  49 #define CONFIG_SYS_FSL_DDRC_GEN4
  50 #else
  51 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3    /* Enable Freescale ARM DDR3 driver */
  52 #endif
  53 #define CONFIG_SYS_FSL_DDR              /* Freescale DDR driver */
  54 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
  55 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
  56 #define CONFIG_SYS_FSL_DDR_VER          FSL_DDR_VER_5_0
  57
  58
  59 /* IFC */
  60 #define CONFIG_SYS_FSL_IFC_LE
  61
  62 #ifdef CONFIG_LS2085A
  63 #define CONFIG_MAX_CPUS                         16
  64 #define CONFIG_SYS_FSL_IFC_BANK_COUNT           8
  65 #define CONFIG_NUM_DDR_CONTROLLERS              3
  66 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS           { 1, 1, 4, 4 }
  67 #else
  68 #error SoC not defined
  69 #endif
  70
  71 #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */