arch/arm/include/asm/arch-hi6220/hi6220.h

   1 /*
   2  * (C) Copyright 2015 Linaro
   3  * Peter Griffin <peter.griffin@linaro.org>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __HI6220_H__
   9 #define __HI6220_H__
  10
  11 #include "hi6220_regs_alwayson.h"
  12
  13 #define HI6220_MMC0_BASE                        0xF723D000
  14 #define HI6220_MMC1_BASE                        0xF723E000
  15
  16 #define HI6220_PMUSSI_BASE                      0xF8000000
  17
  18 #define HI6220_PERI_BASE                        0xF7030000
  19
  20 struct peri_sc_periph_regs {
  21         u32 ctrl1;              /*0x0*/
  22         u32 ctrl2;
  23         u32 ctrl3;
  24         u32 ctrl4;
  25         u32 ctrl5;
  26         u32 ctrl6;
  27         u32 ctrl8;
  28         u32 ctrl9;
  29         u32 ctrl10;
  30         u32 ctrl12;
  31         u32 ctrl13;
  32         u32 ctrl14;
  33
  34         u32 unknown_1[8];
  35
  36         u32 ddr_ctrl0;          /*0x50*/
  37
  38         u32 unknown_2[16];
  39
  40         u32 stat1;              /*0x94*/
  41
  42         u32 unknown_3[90];
  43
  44         u32 clk0_en;            /*0x200*/
  45         u32 clk0_dis;
  46         u32 clk0_stat;
  47
  48         u32 unknown_4;
  49
  50         u32 clk1_en;            /*0x210*/
  51         u32 clk1_dis;
  52         u32 clk1_stat;
  53
  54         u32 unknown_5;
  55
  56         u32 clk2_en;            /*0x220*/
  57         u32 clk2_dis;
  58         u32 clk2_stat;
  59
  60         u32 unknown_6;
  61
  62         u32 clk3_en;            /*0x230*/
  63         u32 clk3_dis;
  64         u32 clk3_stat;
  65
  66         u32 unknown_7;
  67
  68         u32 clk8_en;            /*0x240*/
  69         u32 clk8_dis;
  70         u32 clk8_stat;
  71
  72         u32 unknown_8;
  73
  74         u32 clk9_en;            /*0x250*/
  75         u32 clk9_dis;
  76         u32 clk9_stat;
  77
  78         u32 unknown_9;
  79
  80         u32 clk10_en;           /*0x260*/
  81         u32 clk10_dis;
  82         u32 clk10_stat;
  83
  84         u32 unknown_10;
  85
  86         u32 clk12_en;           /*0x270*/
  87         u32 clk12_dis;
  88         u32 clk12_stat;
  89
  90         u32 unknown_11[33];
  91
  92         u32 rst0_en;            /*0x300*/
  93         u32 rst0_dis;
  94         u32 rst0_stat;
  95
  96         u32 unknown_12;
  97
  98         u32 rst1_en;            /*0x310*/
  99         u32 rst1_dis;
 100         u32 rst1_stat;
 101
 102         u32 unknown_13;
 103
 104         u32 rst2_en;            /*0x320*/
 105         u32 rst2_dis;
 106         u32 rst2_stat;
 107
 108         u32 unknown_14;
 109
 110         u32 rst3_en;            /*0x330*/
 111         u32 rst3_dis;
 112         u32 rst3_stat;
 113
 114         u32 unknown_15;
 115
 116         u32 rst8_en;            /*0x340*/
 117         u32 rst8_dis;
 118         u32 rst8_stat;
 119
 120         u32 unknown_16[45];
 121
 122         u32 clk0_sel;           /*0x400*/
 123
 124         u32 unknown_17[36];
 125
 126         u32 clkcfg8bit1;        /*0x494*/
 127         u32 clkcfg8bit2;
 128
 129         u32 unknown_18[538];
 130
 131         u32 reserved8_addr;     /*0xd04*/
 132 };
 133
 134
 135 /* CTRL1 bit definitions */
 136
 137 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N                    (1 << 0)
 138 #define PERI_CTRL1_HIFI_INT_MASK                        (1 << 1)
 139 #define PERI_CTRL1_HIFI_ALL_INT_MASK                    (1 << 2)
 140 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK                (1 << 16)
 141 #define PERI_CTRL1_HIFI_INT_MASK_MSK                    (1 << 17)
 142 #define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK                (1 << 18)
 143
 144
 145 /* CTRL2 bit definitions */
 146
 147 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0         (1 << 0)
 148 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1         (1 << 2)
 149 #define PERI_CTRL2_NAND_SYS_MEM_SEL                     (1 << 6)
 150 #define PERI_CTRL2_G3D_DDRT_AXI_SEL                     (1 << 7)
 151 #define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL               (1 << 8)
 152 #define PERI_CTRL2_CODEC_SSI_MASTER_CHECK               (1 << 9)
 153 #define PERI_CTRL2_FUNC_TEST_SOFT                       (1 << 12)
 154 #define PERI_CTRL2_CSSYS_TS_ENABLE                      (1 << 15)
 155 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMA                   (1 << 16)
 156 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW                  (1 << 20)
 157 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS                  (1 << 22)
 158 #define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N                 (1 << 26)
 159 #define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N                 (1 << 27)
 160 #define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN                  (1 << 28)
 161
 162 /* CTRL3 bit definitions */
 163
 164 #define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR                (1 << 0)
 165 #define PERI_CTRL3_HIFI_HARQMEMRMP_EN                   (1 << 12)
 166 #define PERI_CTRL3_HARQMEM_SYS_MED_SEL                  (1 << 13)
 167 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP1                   (1 << 14)
 168 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP2                   (1 << 16)
 169 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP3                   (1 << 18)
 170 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP4                   (1 << 20)
 171 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP5                   (1 << 22)
 172 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP6                   (1 << 24)
 173
 174 /* CTRL4 bit definitions */
 175
 176 #define PERI_CTRL4_PICO_FSELV                           (1 << 0)
 177 #define PERI_CTRL4_FPGA_EXT_PHY_SEL                     (1 << 3)
 178 #define PERI_CTRL4_PICO_REFCLKSEL                       (1 << 4)
 179 #define PERI_CTRL4_PICO_SIDDQ                           (1 << 6)
 180 #define PERI_CTRL4_PICO_SUSPENDM_SLEEPM                 (1 << 7)
 181 #define PERI_CTRL4_PICO_OGDISABLE                       (1 << 8)
 182 #define PERI_CTRL4_PICO_COMMONONN                       (1 << 9)
 183 #define PERI_CTRL4_PICO_VBUSVLDEXT                      (1 << 10)
 184 #define PERI_CTRL4_PICO_VBUSVLDEXTSEL                   (1 << 11)
 185 #define PERI_CTRL4_PICO_VATESTENB                       (1 << 12)
 186 #define PERI_CTRL4_PICO_SUSPENDM                        (1 << 14)
 187 #define PERI_CTRL4_PICO_SLEEPM                          (1 << 15)
 188 #define PERI_CTRL4_BC11_C                               (1 << 16)
 189 #define PERI_CTRL4_BC11_B                               (1 << 17)
 190 #define PERI_CTRL4_BC11_A                               (1 << 18)
 191 #define PERI_CTRL4_BC11_GND                             (1 << 19)
 192 #define PERI_CTRL4_BC11_FLOAT                           (1 << 20)
 193 #define PERI_CTRL4_OTG_PHY_SEL                          (1 << 21)
 194 #define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE            (1 << 22)
 195 #define PERI_CTRL4_OTG_DM_PULLDOWN                      (1 << 24)
 196 #define PERI_CTRL4_OTG_DP_PULLDOWN                      (1 << 25)
 197 #define PERI_CTRL4_OTG_IDPULLUP                         (1 << 26)
 198 #define PERI_CTRL4_OTG_DRVBUS                           (1 << 27)
 199 #define PERI_CTRL4_OTG_SESSEND                          (1 << 28)
 200 #define PERI_CTRL4_OTG_BVALID                           (1 << 29)
 201 #define PERI_CTRL4_OTG_AVALID                           (1 << 30)
 202 #define PERI_CTRL4_OTG_VBUSVALID                        (1 << 31)
 203
 204 /* CTRL5 bit definitions */
 205
 206 #define PERI_CTRL5_USBOTG_RES_SEL                       (1 << 3)
 207 #define PERI_CTRL5_PICOPHY_ACAENB                       (1 << 4)
 208 #define PERI_CTRL5_PICOPHY_BC_MODE                      (1 << 5)
 209 #define PERI_CTRL5_PICOPHY_CHRGSEL                      (1 << 6)
 210 #define PERI_CTRL5_PICOPHY_VDATSRCEND                   (1 << 7)
 211 #define PERI_CTRL5_PICOPHY_VDATDETENB                   (1 << 8)
 212 #define PERI_CTRL5_PICOPHY_DCDENB                       (1 << 9)
 213 #define PERI_CTRL5_PICOPHY_IDDIG                        (1 << 10)
 214 #define PERI_CTRL5_DBG_MUX                              (1 << 11)
 215
 216 /* CTRL6 bit definitions */
 217
 218 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA               (1 << 0)
 219 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW              (1 << 4)
 220 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS              (1 << 6)
 221 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N             (1 << 10)
 222 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N             (1 << 11)
 223 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN              (1 << 12)
 224
 225 /* CTRL8 bit definitions */
 226
 227 #define PERI_CTRL8_PICOPHY_TXRISETUNE0                  (1 << 0)
 228 #define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0             (1 << 2)
 229 #define PERI_CTRL8_PICOPHY_TXRESTUNE0                   (1 << 4)
 230 #define PERI_CTRL8_PICOPHY_TXHSSVTUNE0                  (1 << 6)
 231 #define PERI_CTRL8_PICOPHY_COMPDISTUNE0                 (1 << 8)
 232 #define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0           (1 << 11)
 233 #define PERI_CTRL8_PICOPHY_OTGTUNE0                     (1 << 12)
 234 #define PERI_CTRL8_PICOPHY_SQRXTUNE0                    (1 << 16)
 235 #define PERI_CTRL8_PICOPHY_TXVREFTUNE0                  (1 << 20)
 236 #define PERI_CTRL8_PICOPHY_TXFSLSTUNE0                  (1 << 28)
 237
 238 /* CTRL9 bit definitions */
 239
 240 #define PERI_CTRL9_PICOPLY_TESTCLKEN                    (1 << 0)
 241 #define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL               (1 << 1)
 242 #define PERI_CTRL9_PICOPLY_TESTADDR                     (1 << 4)
 243 #define PERI_CTRL9_PICOPLY_TESTDATAIN                   (1 << 8)
 244
 245 /* CLK0 EN/DIS/STAT bit definitions */
 246
 247 #define PERI_CLK0_MMC0                                  (1 << 0)
 248 #define PERI_CLK0_MMC1                                  (1 << 1)
 249 #define PERI_CLK0_MMC2                                  (1 << 2)
 250 #define PERI_CLK0_NANDC                                 (1 << 3)
 251 #define PERI_CLK0_USBOTG                                (1 << 4)
 252 #define PERI_CLK0_PICOPHY                               (1 << 5)
 253 #define PERI_CLK0_PLL                                   (1 << 6)
 254
 255 /* CLK1 EN/DIS/STAT bit definitions */
 256
 257 #define PERI_CLK1_HIFI                                  (1 << 0)
 258 #define PERI_CLK1_DIGACODEC                             (1 << 5)
 259
 260 /* CLK2 EN/DIS/STAT bit definitions */
 261
 262 #define PERI_CLK2_IPF                                   (1 << 0)
 263 #define PERI_CLK2_SOCP                                  (1 << 1)
 264 #define PERI_CLK2_DMAC                                  (1 << 2)
 265 #define PERI_CLK2_SECENG                                (1 << 3)
 266 #define PERI_CLK2_HPM0                                  (1 << 5)
 267 #define PERI_CLK2_HPM1                                  (1 << 6)
 268 #define PERI_CLK2_HPM2                                  (1 << 7)
 269 #define PERI_CLK2_HPM3                                  (1 << 8)
 270
 271 /* CLK8 EN/DIS/STAT bit definitions */
 272
 273 #define PERI_CLK8_RS0                                   (1 << 0)
 274 #define PERI_CLK8_RS2                                   (1 << 1)
 275 #define PERI_CLK8_RS3                                   (1 << 2)
 276 #define PERI_CLK8_MS0                                   (1 << 3)
 277 #define PERI_CLK8_MS2                                   (1 << 5)
 278 #define PERI_CLK8_XG2RAM0                               (1 << 6)
 279 #define PERI_CLK8_X2SRAM                                (1 << 7)
 280 #define PERI_CLK8_SRAM                                  (1 << 8)
 281 #define PERI_CLK8_ROM                                   (1 << 9)
 282 #define PERI_CLK8_HARQ                                  (1 << 10)
 283 #define PERI_CLK8_MMU                                   (1 << 11)
 284 #define PERI_CLK8_DDRC                                  (1 << 12)
 285 #define PERI_CLK8_DDRPHY                                (1 << 13)
 286 #define PERI_CLK8_DDRPHY_REF                            (1 << 14)
 287 #define PERI_CLK8_X2X_SYSNOC                            (1 << 15)
 288 #define PERI_CLK8_X2X_CCPU                              (1 << 16)
 289 #define PERI_CLK8_DDRT                                  (1 << 17)
 290 #define PERI_CLK8_DDRPACK_RS                            (1 << 18)
 291
 292 /* CLK9 EN/DIS/STAT bit definitions */
 293
 294 #define PERI_CLK9_CARM_DAP                              (1 << 0)
 295 #define PERI_CLK9_CARM_ATB                              (1 << 1)
 296 #define PERI_CLK9_CARM_LBUS                             (1 << 2)
 297 #define PERI_CLK9_CARM_KERNEL                           (1 << 3)
 298
 299 /* CLK10 EN/DIS/STAT bit definitions */
 300
 301 #define PERI_CLK10_IPF_CCPU                             (1 << 0)
 302 #define PERI_CLK10_SOCP_CCPU                            (1 << 1)
 303 #define PERI_CLK10_SECENG_CCPU                          (1 << 2)
 304 #define PERI_CLK10_HARQ_CCPU                            (1 << 3)
 305 #define PERI_CLK10_IPF_MCU                              (1 << 16)
 306 #define PERI_CLK10_SOCP_MCU                             (1 << 17)
 307 #define PERI_CLK10_SECENG_MCU                           (1 << 18)
 308 #define PERI_CLK10_HARQ_MCU                             (1 << 19)
 309
 310 /* CLK12 EN/DIS/STAT bit definitions */
 311
 312 #define PERI_CLK12_HIFI_SRC                             (1 << 0)
 313 #define PERI_CLK12_MMC0_SRC                             (1 << 1)
 314 #define PERI_CLK12_MMC1_SRC                             (1 << 2)
 315 #define PERI_CLK12_MMC2_SRC                             (1 << 3)
 316 #define PERI_CLK12_SYSPLL_DIV                           (1 << 4)
 317 #define PERI_CLK12_TPIU_SRC                             (1 << 5)
 318 #define PERI_CLK12_MMC0_HF                              (1 << 6)
 319 #define PERI_CLK12_MMC1_HF                              (1 << 7)
 320 #define PERI_CLK12_PLL_TEST_SRC                         (1 << 8)
 321 #define PERI_CLK12_CODEC_SOC                            (1 << 9)
 322 #define PERI_CLK12_MEDIA                                (1 << 10)
 323
 324 /* RST0 EN/DIS/STAT bit definitions */
 325
 326 #define PERI_RST0_MMC0                                  (1 << 0)
 327 #define PERI_RST0_MMC1                                  (1 << 1)
 328 #define PERI_RST0_MMC2                                  (1 << 2)
 329 #define PERI_RST0_NANDC                                 (1 << 3)
 330 #define PERI_RST0_USBOTG_BUS                            (1 << 4)
 331 #define PERI_RST0_POR_PICOPHY                           (1 << 5)
 332 #define PERI_RST0_USBOTG                                (1 << 6)
 333 #define PERI_RST0_USBOTG_32K                            (1 << 7)
 334
 335 /* RST1 EN/DIS/STAT bit definitions */
 336
 337 #define PERI_RST1_HIFI                                  (1 << 0)
 338 #define PERI_RST1_DIGACODEC                             (1 << 5)
 339
 340 /* RST2 EN/DIS/STAT bit definitions */
 341
 342 #define PERI_RST2_IPF                                   (1 << 0)
 343 #define PERI_RST2_SOCP                                  (1 << 1)
 344 #define PERI_RST2_DMAC                                  (1 << 2)
 345 #define PERI_RST2_SECENG                                (1 << 3)
 346 #define PERI_RST2_ABB                                   (1 << 4)
 347 #define PERI_RST2_HPM0                                  (1 << 5)
 348 #define PERI_RST2_HPM1                                  (1 << 6)
 349 #define PERI_RST2_HPM2                                  (1 << 7)
 350 #define PERI_RST2_HPM3                                  (1 << 8)
 351
 352 /* RST3 EN/DIS/STAT bit definitions */
 353
 354 #define PERI_RST3_CSSYS                                 (1 << 0)
 355 #define PERI_RST3_I2C0                                  (1 << 1)
 356 #define PERI_RST3_I2C1                                  (1 << 2)
 357 #define PERI_RST3_I2C2                                  (1 << 3)
 358 #define PERI_RST3_I2C3                                  (1 << 4)
 359 #define PERI_RST3_UART1                                 (1 << 5)
 360 #define PERI_RST3_UART2                                 (1 << 6)
 361 #define PERI_RST3_UART3                                 (1 << 7)
 362 #define PERI_RST3_UART4                                 (1 << 8)
 363 #define PERI_RST3_SSP                                   (1 << 9)
 364 #define PERI_RST3_PWM                                   (1 << 10)
 365 #define PERI_RST3_BLPWM                                 (1 << 11)
 366 #define PERI_RST3_TSENSOR                               (1 << 12)
 367 #define PERI_RST3_DAPB                                  (1 << 18)
 368 #define PERI_RST3_HKADC                                 (1 << 19)
 369 #define PERI_RST3_CODEC                                 (1 << 20)
 370
 371 /* RST8 EN/DIS/STAT bit definitions */
 372
 373 #define PERI_RST8_RS0                                   (1 << 0)
 374 #define PERI_RST8_RS2                                   (1 << 1)
 375 #define PERI_RST8_RS3                                   (1 << 2)
 376 #define PERI_RST8_MS0                                   (1 << 3)
 377 #define PERI_RST8_MS2                                   (1 << 5)
 378 #define PERI_RST8_XG2RAM0                               (1 << 6)
 379 #define PERI_RST8_X2SRAM_TZMA                           (1 << 7)
 380 #define PERI_RST8_SRAM                                  (1 << 8)
 381 #define PERI_RST8_HARQ                                  (1 << 10)
 382 #define PERI_RST8_DDRC                                  (1 << 12)
 383 #define PERI_RST8_DDRC_APB                              (1 << 13)
 384 #define PERI_RST8_DDRPACK_APB                           (1 << 14)
 385 #define PERI_RST8_DDRT                                  (1 << 17)
 386
 387 #endif /*__HI62220_H__*/